41 lines
1.1 KiB
Systemverilog
Executable File
41 lines
1.1 KiB
Systemverilog
Executable File
module avalon_mm_passthrough #(
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parameter ADDR_WIDTH = 8
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) (
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// Avalon Clock Input
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input logic CLK,
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// Avalon Reset Input
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input logic RESET,
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// Avalon-MM Slave Signals
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input logic AVL_READ, // Avalon-MM Read
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input logic AVL_WRITE, // Avalon-MM Write
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input logic [ADDR_WIDTH-1:0] AVL_ADDR, // Avalon-MM Address
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input logic [31:0] AVL_WRITEDATA, // Avalon-MM Write Data
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output logic [31:0] AVL_READDATA, // Avalon-MM Read Data
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// Avalon Clock Input
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output logic PASS_CLK,
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// Avalon Reset Input
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output logic PASS_RESET,
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// Avalon-MM Slave Signals
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output logic PASS_READ, // Avalon-MM Read
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output logic PASS_WRITE, // Avalon-MM Write
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output logic [ADDR_WIDTH-1:0] PASS_ADDR, // Avalon-MM Address
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output logic [31:0] PASS_WRITEDATA, // Avalon-MM Write Data
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input logic [31:0] PASS_READDATA // Avalon-MM Read Data
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);
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assign PASS_CLK = CLK;
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assign PASS_RESET = RESET;
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assign PASS_READ = AVL_READ;
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assign PASS_WRITE = AVL_WRITE;
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assign PASS_ADDR = AVL_ADDR;
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assign PASS_WRITEDATA = AVL_WRITEDATA;
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assign AVL_READDATA = PASS_READDATA;
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endmodule
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