39 lines
1.1 KiB
Verilog
39 lines
1.1 KiB
Verilog
// $File: //acds/rel/18.1std/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $
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// $Revision: #1 $
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// $Date: 2018/07/18 $
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// $Author: psgswbuild $
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//-------------------------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module altera_dcfifo_synchronizer_bundle(
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clk,
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reset_n,
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din,
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dout
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);
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parameter WIDTH = 1;
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parameter DEPTH = 3;
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input clk;
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input reset_n;
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input [WIDTH-1:0] din;
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output [WIDTH-1:0] dout;
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genvar i;
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generate
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for (i=0; i<WIDTH; i=i+1)
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begin : sync
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altera_std_synchronizer_nocut #(.depth(DEPTH))
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u (
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.clk(clk),
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.reset_n(reset_n),
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.din(din[i]),
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.dout(dout[i])
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);
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end
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endgenerate
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endmodule
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