72 lines
4.2 KiB
Tcl
72 lines
4.2 KiB
Tcl
# (C) 2001-2018 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files from any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License Subscription
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# Agreement, Intel FPGA IP License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Intel and sold by
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# Intel or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# $File: //acds/main/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.sdc $
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# $Revision: #1 $
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# $Date: 2014/04/09 $
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# $Author: kespence $
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#------------------------------------------------------------------------------
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# -----------------------------------------------------------------------------
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# Altera timing constraints for Avalon clock domain crossing (CDC) paths.
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# The purpose of these constraints is to remove the false paths and replace with timing bounded
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# requirements for compilation.
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#
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# ***Important note ***
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#
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# The clocks involved in this transfer must be kept synchronous and no false path
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# should be set on these paths for these constraints to apply correctly.
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# -----------------------------------------------------------------------------
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set crosser_entity "altera_avalon_st_clock_crosser:"
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set_max_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] 100
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set_min_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -100
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set sync_entity "altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:"
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set_max_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] 100
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set_min_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -100
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if { [ is_project_open ] && [ string equal -nocase on [ get_global_assignment -name TIMEQUEST2 ] ] } {
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set_net_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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set_net_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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} else {
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set_net_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -max 2
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set_net_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -max 2
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}
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# -----------------------------------------------------------------------------
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# This procedure constrains the skew between the token and data bits, and should
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# be called from the top level SDC, once per instance of the clock crosser.
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#
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# The hierarchy path to the handshake clock crosser instance is required as an
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# argument.
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#
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# In practice, the token and data bits tend to be placed close together, making
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# excessive skew less of an issue.
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# -----------------------------------------------------------------------------
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proc constrain_alt_handshake_clock_crosser_skew { path } {
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set in_regs [ get_registers $path|*altera_avalon_st_clock_crosser*|in_data_buffer* ]
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set out_regs [ get_registers $path|*altera_avalon_st_clock_crosser*|out_data_buffer* ]
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set in_regs [ add_to_collection $in_regs [ get_registers $path|*altera_avalon_st_clock_crosser*|in_data_toggle ] ]
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set out_regs [ add_to_collection $out_regs [ get_registers $path|*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:in_to_out_synchronizer|din_s1 ] ]
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if { [ is_project_open ] && [ string equal -nocase on [ get_global_assignment -name TIMEQUEST2 ] ] } {
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set_max_skew -from $in_regs -to $out_regs -get_skew_value_from_clock_period dst_clock_period -skew_value_multiplier 0.8
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} else {
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set_max_skew -from $in_regs -to $out_regs 1.5
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}
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}
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