719 lines
23 KiB
Verilog
Executable File
719 lines
23 KiB
Verilog
Executable File
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module ECE385_sdram_input_efifo_module (
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// inputs:
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clk,
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rd,
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reset_n,
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wr,
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wr_data,
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// outputs:
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almost_empty,
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almost_full,
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empty,
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full,
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rd_data
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)
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;
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output almost_empty;
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output almost_full;
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output empty;
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output full;
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output [ 61: 0] rd_data;
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input clk;
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input rd;
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input reset_n;
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input wr;
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input [ 61: 0] wr_data;
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wire almost_empty;
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wire almost_full;
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wire empty;
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reg [ 1: 0] entries;
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reg [ 61: 0] entry_0;
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reg [ 61: 0] entry_1;
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wire full;
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reg rd_address;
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reg [ 61: 0] rd_data;
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wire [ 1: 0] rdwr;
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reg wr_address;
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assign rdwr = {rd, wr};
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assign full = entries == 2;
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assign almost_full = entries >= 1;
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assign empty = entries == 0;
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assign almost_empty = entries <= 1;
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always @(entry_0 or entry_1 or rd_address)
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begin
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case (rd_address) // synthesis parallel_case full_case
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1'd0: begin
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rd_data = entry_0;
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end // 1'd0
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1'd1: begin
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rd_data = entry_1;
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end // 1'd1
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default: begin
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end // default
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endcase // rd_address
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end
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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begin
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wr_address <= 0;
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rd_address <= 0;
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entries <= 0;
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end
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else
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case (rdwr) // synthesis parallel_case full_case
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2'd1: begin
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// Write data
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if (!full)
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begin
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entries <= entries + 1;
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wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
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end
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end // 2'd1
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2'd2: begin
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// Read data
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if (!empty)
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begin
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entries <= entries - 1;
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rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
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end
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end // 2'd2
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2'd3: begin
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wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
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rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
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end // 2'd3
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default: begin
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end // default
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endcase // rdwr
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end
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always @(posedge clk)
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begin
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//Write data
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if (wr & !full)
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case (wr_address) // synthesis parallel_case full_case
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1'd0: begin
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entry_0 <= wr_data;
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end // 1'd0
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1'd1: begin
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entry_1 <= wr_data;
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end // 1'd1
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default: begin
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end // default
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endcase // wr_address
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end
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endmodule
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module ECE385_sdram (
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// inputs:
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az_addr,
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az_be_n,
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az_cs,
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az_data,
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az_rd_n,
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az_wr_n,
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clk,
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reset_n,
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// outputs:
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za_data,
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za_valid,
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za_waitrequest,
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zs_addr,
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zs_ba,
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zs_cas_n,
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zs_cke,
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zs_cs_n,
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zs_dq,
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zs_dqm,
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zs_ras_n,
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zs_we_n
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)
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;
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output [ 31: 0] za_data;
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output za_valid;
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output za_waitrequest;
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output [ 12: 0] zs_addr;
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output [ 1: 0] zs_ba;
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output zs_cas_n;
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output zs_cke;
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output zs_cs_n;
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inout [ 31: 0] zs_dq;
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output [ 3: 0] zs_dqm;
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output zs_ras_n;
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output zs_we_n;
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input [ 24: 0] az_addr;
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input [ 3: 0] az_be_n;
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input az_cs;
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input [ 31: 0] az_data;
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input az_rd_n;
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input az_wr_n;
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input clk;
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input reset_n;
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wire [ 23: 0] CODE;
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reg ack_refresh_request;
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reg [ 24: 0] active_addr;
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wire [ 1: 0] active_bank;
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reg active_cs_n;
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reg [ 31: 0] active_data;
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reg [ 3: 0] active_dqm;
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reg active_rnw;
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wire almost_empty;
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wire almost_full;
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wire bank_match;
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wire [ 9: 0] cas_addr;
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wire clk_en;
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wire [ 3: 0] cmd_all;
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wire [ 2: 0] cmd_code;
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wire cs_n;
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wire csn_decode;
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wire csn_match;
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wire [ 24: 0] f_addr;
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wire [ 1: 0] f_bank;
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wire f_cs_n;
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wire [ 31: 0] f_data;
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wire [ 3: 0] f_dqm;
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wire f_empty;
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reg f_pop;
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wire f_rnw;
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wire f_select;
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wire [ 61: 0] fifo_read_data;
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reg [ 12: 0] i_addr;
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reg [ 3: 0] i_cmd;
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reg [ 2: 0] i_count;
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reg [ 2: 0] i_next;
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reg [ 2: 0] i_refs;
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reg [ 2: 0] i_state;
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reg init_done;
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reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
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reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
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reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
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reg [ 2: 0] m_count;
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reg [ 31: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
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reg [ 3: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
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reg [ 8: 0] m_next;
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reg [ 8: 0] m_state;
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reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
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wire pending;
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wire rd_strobe;
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reg [ 1: 0] rd_valid;
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reg [ 13: 0] refresh_counter;
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reg refresh_request;
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wire rnw_match;
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wire row_match;
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wire [ 23: 0] txt_code;
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reg za_cannotrefresh;
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reg [ 31: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
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reg za_valid;
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wire za_waitrequest;
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wire [ 12: 0] zs_addr;
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wire [ 1: 0] zs_ba;
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wire zs_cas_n;
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wire zs_cke;
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wire zs_cs_n;
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wire [ 31: 0] zs_dq;
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wire [ 3: 0] zs_dqm;
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wire zs_ras_n;
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wire zs_we_n;
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assign clk_en = 1;
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//s1, which is an e_avalon_slave
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assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
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assign zs_addr = m_addr;
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assign zs_cke = clk_en;
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assign zs_dq = oe?m_data:{32{1'bz}};
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assign zs_dqm = m_dqm;
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assign zs_ba = m_bank;
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assign f_select = f_pop & pending;
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assign f_cs_n = 1'b0;
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assign cs_n = f_select ? f_cs_n : active_cs_n;
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assign csn_decode = cs_n;
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assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
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ECE385_sdram_input_efifo_module the_ECE385_sdram_input_efifo_module
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(
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.almost_empty (almost_empty),
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.almost_full (almost_full),
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.clk (clk),
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.empty (f_empty),
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.full (za_waitrequest),
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.rd (f_select),
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.rd_data (fifo_read_data),
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.reset_n (reset_n),
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.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
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.wr_data ({az_wr_n, az_addr, az_wr_n ? 4'b0 : az_be_n, az_data})
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);
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assign f_bank = {f_addr[24],f_addr[10]};
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// Refresh/init counter.
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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refresh_counter <= 10000;
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else if (refresh_counter == 0)
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refresh_counter <= 499;
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else
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refresh_counter <= refresh_counter - 1'b1;
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end
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// Refresh request signal.
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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refresh_request <= 0;
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else if (1)
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refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
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end
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// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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za_cannotrefresh <= 0;
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else if (1)
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za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
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end
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// Initialization-done flag.
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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init_done <= 0;
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else if (1)
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init_done <= init_done | (i_state == 3'b101);
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end
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// **** Init FSM ****
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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begin
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i_state <= 3'b000;
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i_next <= 3'b000;
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i_cmd <= 4'b1111;
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i_addr <= {13{1'b1}};
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i_count <= {3{1'b0}};
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end
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else
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begin
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i_addr <= {13{1'b1}};
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case (i_state) // synthesis parallel_case full_case
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3'b000: begin
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i_cmd <= 4'b1111;
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i_refs <= 3'b0;
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//Wait for refresh count-down after reset
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if (refresh_counter == 0)
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i_state <= 3'b001;
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end // 3'b000
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3'b001: begin
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i_state <= 3'b011;
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i_cmd <= {{1{1'b0}},3'h2};
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i_count <= 0;
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i_next <= 3'b010;
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end // 3'b001
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3'b010: begin
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i_cmd <= {{1{1'b0}},3'h1};
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i_refs <= i_refs + 1'b1;
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i_state <= 3'b011;
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i_count <= 3;
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// Count up init_refresh_commands
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if (i_refs == 3'h1)
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i_next <= 3'b111;
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else
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i_next <= 3'b010;
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end // 3'b010
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3'b011: begin
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i_cmd <= {{1{1'b0}},3'h7};
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//WAIT til safe to Proceed...
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if (i_count > 1)
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i_count <= i_count - 1'b1;
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else
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i_state <= i_next;
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end // 3'b011
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3'b101: begin
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i_state <= 3'b101;
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end // 3'b101
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3'b111: begin
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i_state <= 3'b011;
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i_cmd <= {{1{1'b0}},3'h0};
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i_addr <= {{3{1'b0}},1'b0,2'b00,3'h2,4'h0};
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i_count <= 4;
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i_next <= 3'b101;
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end // 3'b111
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default: begin
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i_state <= 3'b000;
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end // default
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endcase // i_state
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end
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end
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assign active_bank = {active_addr[24],active_addr[10]};
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assign csn_match = active_cs_n == f_cs_n;
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assign rnw_match = active_rnw == f_rnw;
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assign bank_match = active_bank == f_bank;
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assign row_match = {active_addr[23 : 11]} == {f_addr[23 : 11]};
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assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
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assign cas_addr = f_select ? { {3{1'b0}},f_addr[9 : 0] } : { {3{1'b0}},active_addr[9 : 0] };
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// **** Main FSM ****
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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begin
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m_state <= 9'b000000001;
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m_next <= 9'b000000001;
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m_cmd <= 4'b1111;
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m_bank <= 2'b00;
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m_addr <= 13'b0000000000000;
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m_data <= 32'b00000000000000000000000000000000;
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m_dqm <= 4'b0000;
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m_count <= 3'b000;
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ack_refresh_request <= 1'b0;
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f_pop <= 1'b0;
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oe <= 1'b0;
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end
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else
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begin
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f_pop <= 1'b0;
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oe <= 1'b0;
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case (m_state) // synthesis parallel_case full_case
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9'b000000001: begin
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//Wait for init-fsm to be done...
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if (init_done)
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begin
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//Hold bus if another cycle ended to arf.
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if (refresh_request)
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m_cmd <= {{1{1'b0}},3'h7};
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else
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m_cmd <= 4'b1111;
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ack_refresh_request <= 1'b0;
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//Wait for a read/write request.
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if (refresh_request)
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begin
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m_state <= 9'b001000000;
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m_next <= 9'b010000000;
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m_count <= 0;
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active_cs_n <= 1'b1;
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end
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else if (!f_empty)
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begin
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f_pop <= 1'b1;
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active_cs_n <= f_cs_n;
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active_rnw <= f_rnw;
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active_addr <= f_addr;
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active_data <= f_data;
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active_dqm <= f_dqm;
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m_state <= 9'b000000010;
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end
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end
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else
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begin
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m_addr <= i_addr;
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m_state <= 9'b000000001;
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m_next <= 9'b000000001;
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m_cmd <= i_cmd;
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end
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end // 9'b000000001
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9'b000000010: begin
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m_state <= 9'b000000100;
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m_cmd <= {csn_decode,3'h3};
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m_bank <= active_bank;
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m_addr <= active_addr[23 : 11];
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m_data <= active_data;
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m_dqm <= active_dqm;
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m_count <= 1;
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m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
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end // 9'b000000010
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9'b000000100: begin
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// precharge all if arf, else precharge csn_decode
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if (m_next == 9'b010000000)
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m_cmd <= {{1{1'b0}},3'h7};
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else
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m_cmd <= {csn_decode,3'h7};
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//Count down til safe to Proceed...
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if (m_count > 1)
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m_count <= m_count - 1'b1;
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else
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m_state <= m_next;
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end // 9'b000000100
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9'b000001000: begin
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m_cmd <= {csn_decode,3'h5};
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m_bank <= f_select ? f_bank : active_bank;
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m_dqm <= f_select ? f_dqm : active_dqm;
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m_addr <= cas_addr;
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//Do we have a transaction pending?
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if (pending)
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begin
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//if we need to ARF, bail, else spin
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if (refresh_request)
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begin
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m_state <= 9'b000000100;
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m_next <= 9'b000000001;
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m_count <= 1;
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end
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else
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begin
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f_pop <= 1'b1;
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active_cs_n <= f_cs_n;
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active_rnw <= f_rnw;
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active_addr <= f_addr;
|
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active_data <= f_data;
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active_dqm <= f_dqm;
|
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end
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end
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else
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begin
|
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//correctly end RD spin cycle if fifo mt
|
|
if (~pending & f_pop)
|
|
m_cmd <= {csn_decode,3'h7};
|
|
m_state <= 9'b100000000;
|
|
end
|
|
end // 9'b000001000
|
|
|
|
9'b000010000: begin
|
|
m_cmd <= {csn_decode,3'h4};
|
|
oe <= 1'b1;
|
|
m_data <= f_select ? f_data : active_data;
|
|
m_dqm <= f_select ? f_dqm : active_dqm;
|
|
m_bank <= f_select ? f_bank : active_bank;
|
|
m_addr <= cas_addr;
|
|
//Do we have a transaction pending?
|
|
if (pending)
|
|
begin
|
|
//if we need to ARF, bail, else spin
|
|
if (refresh_request)
|
|
begin
|
|
m_state <= 9'b000000100;
|
|
m_next <= 9'b000000001;
|
|
m_count <= 1;
|
|
end
|
|
else
|
|
begin
|
|
f_pop <= 1'b1;
|
|
active_cs_n <= f_cs_n;
|
|
active_rnw <= f_rnw;
|
|
active_addr <= f_addr;
|
|
active_data <= f_data;
|
|
active_dqm <= f_dqm;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
//correctly end WR spin cycle if fifo empty
|
|
if (~pending & f_pop)
|
|
begin
|
|
m_cmd <= {csn_decode,3'h7};
|
|
oe <= 1'b0;
|
|
end
|
|
m_state <= 9'b100000000;
|
|
end
|
|
end // 9'b000010000
|
|
|
|
9'b000100000: begin
|
|
m_cmd <= {csn_decode,3'h7};
|
|
//Count down til safe to Proceed...
|
|
if (m_count > 1)
|
|
m_count <= m_count - 1'b1;
|
|
else
|
|
begin
|
|
m_state <= 9'b001000000;
|
|
m_count <= 0;
|
|
end
|
|
end // 9'b000100000
|
|
|
|
9'b001000000: begin
|
|
m_state <= 9'b000000100;
|
|
m_addr <= {13{1'b1}};
|
|
// precharge all if arf, else precharge csn_decode
|
|
if (refresh_request)
|
|
m_cmd <= {{1{1'b0}},3'h2};
|
|
else
|
|
m_cmd <= {csn_decode,3'h2};
|
|
end // 9'b001000000
|
|
|
|
9'b010000000: begin
|
|
ack_refresh_request <= 1'b1;
|
|
m_state <= 9'b000000100;
|
|
m_cmd <= {{1{1'b0}},3'h1};
|
|
m_count <= 3;
|
|
m_next <= 9'b000000001;
|
|
end // 9'b010000000
|
|
|
|
9'b100000000: begin
|
|
m_cmd <= {csn_decode,3'h7};
|
|
//if we need to ARF, bail, else spin
|
|
if (refresh_request)
|
|
m_state <= 9'b000000001;
|
|
else //wait for fifo to have contents
|
|
if (!f_empty)
|
|
//Are we 'pending' yet?
|
|
if (csn_match && rnw_match && bank_match && row_match)
|
|
begin
|
|
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
|
|
f_pop <= 1'b1;
|
|
active_cs_n <= f_cs_n;
|
|
active_rnw <= f_rnw;
|
|
active_addr <= f_addr;
|
|
active_data <= f_data;
|
|
active_dqm <= f_dqm;
|
|
end
|
|
else
|
|
begin
|
|
m_state <= 9'b001000000;
|
|
m_next <= 9'b000000001;
|
|
m_count <= 0;
|
|
end
|
|
end // 9'b100000000
|
|
|
|
// synthesis translate_off
|
|
|
|
default: begin
|
|
m_state <= m_state;
|
|
m_cmd <= 4'b1111;
|
|
f_pop <= 1'b0;
|
|
oe <= 1'b0;
|
|
end // default
|
|
|
|
// synthesis translate_on
|
|
endcase // m_state
|
|
end
|
|
end
|
|
|
|
|
|
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
|
|
//Track RD Req's based on cas_latency w/shift reg
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
rd_valid <= {2{1'b0}};
|
|
else
|
|
rd_valid <= (rd_valid << 1) | { {1{1'b0}}, rd_strobe };
|
|
end
|
|
|
|
|
|
// Register dq data.
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
za_data <= 0;
|
|
else
|
|
za_data <= zs_dq;
|
|
end
|
|
|
|
|
|
// Delay za_valid to match registered data.
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
za_valid <= 0;
|
|
else if (1)
|
|
za_valid <= rd_valid[1];
|
|
end
|
|
|
|
|
|
assign cmd_code = m_cmd[2 : 0];
|
|
assign cmd_all = m_cmd;
|
|
|
|
//synthesis translate_off
|
|
//////////////// SIMULATION-ONLY CONTENTS
|
|
initial
|
|
begin
|
|
$write("\n");
|
|
$write("This reference design requires a vendor simulation model.\n");
|
|
$write("To simulate accesses to SDRAM, you must:\n");
|
|
$write(" - Download the vendor model\n");
|
|
$write(" - Install the model in the system_sim directory\n");
|
|
$write(" - `include the vendor model in the the top-level system file,\n");
|
|
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
|
|
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
|
|
$write(" (because this simulation is zero-delay based)\n");
|
|
$write("\n");
|
|
end
|
|
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
|
|
(cmd_code == 3'h1)? 24'h415246 :
|
|
(cmd_code == 3'h2)? 24'h505245 :
|
|
(cmd_code == 3'h3)? 24'h414354 :
|
|
(cmd_code == 3'h4)? 24'h205752 :
|
|
(cmd_code == 3'h5)? 24'h205244 :
|
|
(cmd_code == 3'h6)? 24'h425354 :
|
|
(cmd_code == 3'h7)? 24'h4e4f50 :
|
|
24'h424144;
|
|
|
|
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
|
|
|
|
//////////////// END SIMULATION-ONLY CONTENTS
|
|
|
|
//synthesis translate_on
|
|
|
|
endmodule
|
|
|