345 lines
12 KiB
Verilog
Executable File
345 lines
12 KiB
Verilog
Executable File
//altpll_avalon avalon_use_separate_sysclk="YES" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 c2 c3 clk configupdate inclk0 locked phasecounterselect phasedone phasestep phaseupdown read readdata reset scanclk scanclkena scandata scandataout scandone write writedata bandwidth_type="AUTO" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="-3000" clk2_divide_by=1 clk2_duty_cycle=50 clk2_multiply_by=2 clk2_phase_shift="0" clk3_divide_by=2 clk3_duty_cycle=50 clk3_multiply_by=1 clk3_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
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//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_altiobuf_bidir 2018:09:12:13:04:24:SJ cbx_altiobuf_in 2018:09:12:13:04:24:SJ cbx_altiobuf_out 2018:09:12:13:04:24:SJ cbx_altpll 2018:09:12:13:04:24:SJ cbx_altpll_avalon 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_lpm_shiftreg 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 2018 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details.
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//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
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//VERSION_BEGIN 18.1 cbx_mgl 2018:09:12:13:10:36:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
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//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
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//VERSION_BEGIN 18.1 cbx_mgl 2018:09:12:13:10:36:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
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//synthesis_resources = reg 3
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
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module ECE385_nios2_pll_dffpipe_l2c
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(
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clock,
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clrn,
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d,
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q) /* synthesis synthesis_clearbox=1 */;
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input clock;
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input clrn;
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input [0:0] d;
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output [0:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 clock;
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tri1 clrn;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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reg [0:0] dffe4a;
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reg [0:0] dffe5a;
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reg [0:0] dffe6a;
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wire ena;
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wire prn;
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wire sclr;
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// synopsys translate_off
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initial
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dffe4a = 0;
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// synopsys translate_on
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always @ ( posedge clock or negedge prn or negedge clrn)
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if (prn == 1'b0) dffe4a <= {1{1'b1}};
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else if (clrn == 1'b0) dffe4a <= 1'b0;
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else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
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// synopsys translate_off
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initial
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dffe5a = 0;
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// synopsys translate_on
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always @ ( posedge clock or negedge prn or negedge clrn)
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if (prn == 1'b0) dffe5a <= {1{1'b1}};
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else if (clrn == 1'b0) dffe5a <= 1'b0;
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else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
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// synopsys translate_off
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initial
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dffe6a = 0;
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// synopsys translate_on
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always @ ( posedge clock or negedge prn or negedge clrn)
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if (prn == 1'b0) dffe6a <= {1{1'b1}};
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else if (clrn == 1'b0) dffe6a <= 1'b0;
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else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
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assign
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ena = 1'b1,
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prn = 1'b1,
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q = dffe6a,
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sclr = 1'b0;
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endmodule //ECE385_nios2_pll_dffpipe_l2c
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//synthesis_resources = reg 3
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module ECE385_nios2_pll_stdsync_sv6
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(
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clk,
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din,
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dout,
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reset_n) /* synthesis synthesis_clearbox=1 */;
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input clk;
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input din;
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output dout;
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input reset_n;
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wire [0:0] wire_dffpipe3_q;
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ECE385_nios2_pll_dffpipe_l2c dffpipe3
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(
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.clock(clk),
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.clrn(reset_n),
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.d(din),
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.q(wire_dffpipe3_q));
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assign
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dout = wire_dffpipe3_q;
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endmodule //ECE385_nios2_pll_stdsync_sv6
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//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="-3000" clk2_divide_by=1 clk2_duty_cycle=50 clk2_multiply_by=2 clk2_phase_shift="0" clk3_divide_by=2 clk3_duty_cycle=50 clk3_multiply_by=1 clk3_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
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//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_altiobuf_bidir 2018:09:12:13:04:24:SJ cbx_altiobuf_in 2018:09:12:13:04:24:SJ cbx_altiobuf_out 2018:09:12:13:04:24:SJ cbx_altpll 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
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//synthesis_resources = cycloneive_pll 1 reg 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
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module ECE385_nios2_pll_altpll_8tn2
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(
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areset,
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clk,
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inclk,
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locked) /* synthesis synthesis_clearbox=1 */;
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input areset;
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output [4:0] clk;
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input [1:0] inclk;
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output locked;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 areset;
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tri0 [1:0] inclk;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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reg pll_lock_sync;
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wire [4:0] wire_pll7_clk;
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wire wire_pll7_fbout;
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wire wire_pll7_locked;
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// synopsys translate_off
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initial
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pll_lock_sync = 0;
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// synopsys translate_on
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always @ ( posedge wire_pll7_locked or posedge areset)
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if (areset == 1'b1) pll_lock_sync <= 1'b0;
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else pll_lock_sync <= 1'b1;
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cycloneive_pll pll7
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(
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.activeclock(),
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.areset(areset),
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.clk(wire_pll7_clk),
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.clkbad(),
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.fbin(wire_pll7_fbout),
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.fbout(wire_pll7_fbout),
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.inclk(inclk),
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.locked(wire_pll7_locked),
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.phasedone(),
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.scandataout(),
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.scandone(),
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.vcooverrange(),
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.vcounderrange()
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.clkswitch(1'b0),
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.configupdate(1'b0),
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.pfdena(1'b1),
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.phasecounterselect({3{1'b0}}),
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.phasestep(1'b0),
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.phaseupdown(1'b0),
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.scanclk(1'b0),
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.scanclkena(1'b1),
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.scandata(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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);
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defparam
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pll7.bandwidth_type = "auto",
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pll7.clk0_divide_by = 2,
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pll7.clk0_duty_cycle = 50,
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pll7.clk0_multiply_by = 5,
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pll7.clk0_phase_shift = "0",
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pll7.clk1_divide_by = 1,
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pll7.clk1_duty_cycle = 50,
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pll7.clk1_multiply_by = 1,
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pll7.clk1_phase_shift = "-3000",
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pll7.clk2_divide_by = 1,
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pll7.clk2_duty_cycle = 50,
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pll7.clk2_multiply_by = 2,
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pll7.clk2_phase_shift = "0",
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pll7.clk3_divide_by = 2,
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pll7.clk3_duty_cycle = 50,
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pll7.clk3_multiply_by = 1,
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pll7.clk3_phase_shift = "0",
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pll7.compensate_clock = "clk0",
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pll7.inclk0_input_frequency = 20000,
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pll7.operation_mode = "normal",
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pll7.pll_type = "auto",
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pll7.lpm_type = "cycloneive_pll";
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assign
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clk = {wire_pll7_clk[4:0]},
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locked = (wire_pll7_locked & pll_lock_sync);
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endmodule //ECE385_nios2_pll_altpll_8tn2
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//synthesis_resources = cycloneive_pll 1 reg 6
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module ECE385_nios2_pll
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(
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address,
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areset,
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c0,
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c1,
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c2,
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c3,
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clk,
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configupdate,
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inclk0,
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locked,
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phasecounterselect,
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phasedone,
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phasestep,
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phaseupdown,
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read,
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readdata,
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reset,
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scanclk,
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scanclkena,
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scandata,
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scandataout,
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scandone,
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write,
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writedata) /* synthesis synthesis_clearbox=1 */;
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input [1:0] address;
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input areset;
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output c0;
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output c1;
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output c2;
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output c3;
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input clk;
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input configupdate;
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input inclk0;
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output locked;
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input [3:0] phasecounterselect;
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output phasedone;
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input phasestep;
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input phaseupdown;
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input read;
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output [31:0] readdata;
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input reset;
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input scanclk;
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input scanclkena;
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input scandata;
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output scandataout;
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output scandone;
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input write;
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input [31:0] writedata;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 inclk0;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire wire_stdsync2_dout;
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wire [4:0] wire_sd1_clk;
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wire wire_sd1_locked;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
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reg pfdena_reg;
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wire wire_pfdena_reg_ena;
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reg prev_reset;
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wire w_locked;
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wire w_pfdena;
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wire w_phasedone;
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wire w_pll_areset_in;
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wire w_reset;
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wire w_select_control;
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wire w_select_status;
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ECE385_nios2_pll_stdsync_sv6 stdsync2
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(
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.clk(clk),
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.din(wire_sd1_locked),
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.dout(wire_stdsync2_dout),
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.reset_n((~ reset)));
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ECE385_nios2_pll_altpll_8tn2 sd1
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(
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.areset((w_pll_areset_in | areset)),
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.clk(wire_sd1_clk),
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.inclk({{1{1'b0}}, inclk0}),
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.locked(wire_sd1_locked));
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// synopsys translate_off
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initial
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pfdena_reg = {1{1'b1}};
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// synopsys translate_on
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always @ ( posedge clk or posedge reset)
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if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
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else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
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assign
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wire_pfdena_reg_ena = (write & w_select_control);
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// synopsys translate_off
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initial
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prev_reset = 0;
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// synopsys translate_on
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always @ ( posedge clk or posedge reset)
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if (reset == 1'b1) prev_reset <= 1'b0;
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else prev_reset <= w_reset;
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assign
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c0 = wire_sd1_clk[0],
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c1 = wire_sd1_clk[1],
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c2 = wire_sd1_clk[2],
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c3 = wire_sd1_clk[3],
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locked = wire_sd1_locked,
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phasedone = 1'b0,
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readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
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scandataout = 1'b0,
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scandone = 1'b0,
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w_locked = wire_stdsync2_dout,
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w_pfdena = pfdena_reg,
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w_phasedone = 1'b1,
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w_pll_areset_in = prev_reset,
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w_reset = ((write & w_select_control) & writedata[0]),
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w_select_control = ((~ address[1]) & address[0]),
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w_select_status = ((~ address[1]) & (~ address[0]));
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endmodule //ECE385_nios2_pll
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//VALID FILE
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