97 lines
3.6 KiB
Systemverilog
97 lines
3.6 KiB
Systemverilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// (C) 2001-2014 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
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// $Revision: #1 $
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// $Date: 2018/07/18 $
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// $Author: psgswbuild $
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// ------------------------------------------
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// Merlin Multiplexer
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// ------------------------------------------
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`timescale 1 ns / 1 ns
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// ------------------------------------------
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// Generation parameters:
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// output_name: ECE385_mm_interconnect_2_rsp_mux
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// NUM_INPUTS: 1
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// ARBITRATION_SHARES: 1
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// ARBITRATION_SCHEME "no-arb"
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// PIPELINE_ARB: 0
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// PKT_TRANS_LOCK: 72 (arbitration locking enabled)
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// ST_DATA_W: 108
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// ST_CHANNEL_W: 14
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// ------------------------------------------
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module ECE385_mm_interconnect_2_rsp_mux
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(
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// ----------------------
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// Sinks
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// ----------------------
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input sink0_valid,
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input [108-1 : 0] sink0_data,
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input [14-1: 0] sink0_channel,
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input sink0_startofpacket,
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input sink0_endofpacket,
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output sink0_ready,
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// ----------------------
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// Source
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// ----------------------
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output src_valid,
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output [108-1 : 0] src_data,
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output [14-1 : 0] src_channel,
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output src_startofpacket,
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output src_endofpacket,
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input src_ready,
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// ----------------------
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// Clock & Reset
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// ----------------------
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input clk,
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input reset
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);
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localparam PAYLOAD_W = 108 + 14 + 2;
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localparam NUM_INPUTS = 1;
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localparam SHARE_COUNTER_W = 1;
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localparam PIPELINE_ARB = 0;
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localparam ST_DATA_W = 108;
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localparam ST_CHANNEL_W = 14;
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localparam PKT_TRANS_LOCK = 72;
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assign src_valid = sink0_valid;
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assign src_data = sink0_data;
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assign src_channel = sink0_channel;
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assign src_startofpacket = sink0_startofpacket;
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assign src_endofpacket = sink0_endofpacket;
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assign sink0_ready = src_ready;
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endmodule
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