539 lines
20 KiB
Systemverilog
539 lines
20 KiB
Systemverilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// (C) 2001-2014 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
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// $Revision: #1 $
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// $Date: 2018/07/18 $
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// $Author: psgswbuild $
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// ------------------------------------------
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// Merlin Multiplexer
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// ------------------------------------------
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`timescale 1 ns / 1 ns
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// ------------------------------------------
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// Generation parameters:
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// output_name: ECE385_mm_interconnect_2_cmd_mux
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// NUM_INPUTS: 14
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// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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// ARBITRATION_SCHEME "round-robin"
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// PIPELINE_ARB: 1
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// PKT_TRANS_LOCK: 72 (arbitration locking enabled)
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// ST_DATA_W: 108
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// ST_CHANNEL_W: 14
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// ------------------------------------------
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module ECE385_mm_interconnect_2_cmd_mux
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(
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// ----------------------
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// Sinks
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// ----------------------
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input sink0_valid,
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input [108-1 : 0] sink0_data,
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input [14-1: 0] sink0_channel,
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input sink0_startofpacket,
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input sink0_endofpacket,
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output sink0_ready,
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input sink1_valid,
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input [108-1 : 0] sink1_data,
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input [14-1: 0] sink1_channel,
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input sink1_startofpacket,
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input sink1_endofpacket,
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output sink1_ready,
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input sink2_valid,
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input [108-1 : 0] sink2_data,
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input [14-1: 0] sink2_channel,
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input sink2_startofpacket,
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input sink2_endofpacket,
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output sink2_ready,
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input sink3_valid,
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input [108-1 : 0] sink3_data,
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input [14-1: 0] sink3_channel,
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input sink3_startofpacket,
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input sink3_endofpacket,
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output sink3_ready,
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input sink4_valid,
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input [108-1 : 0] sink4_data,
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input [14-1: 0] sink4_channel,
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input sink4_startofpacket,
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input sink4_endofpacket,
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output sink4_ready,
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input sink5_valid,
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input [108-1 : 0] sink5_data,
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input [14-1: 0] sink5_channel,
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input sink5_startofpacket,
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input sink5_endofpacket,
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output sink5_ready,
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input sink6_valid,
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input [108-1 : 0] sink6_data,
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input [14-1: 0] sink6_channel,
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input sink6_startofpacket,
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input sink6_endofpacket,
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output sink6_ready,
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input sink7_valid,
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input [108-1 : 0] sink7_data,
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input [14-1: 0] sink7_channel,
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input sink7_startofpacket,
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input sink7_endofpacket,
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output sink7_ready,
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input sink8_valid,
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input [108-1 : 0] sink8_data,
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input [14-1: 0] sink8_channel,
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input sink8_startofpacket,
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input sink8_endofpacket,
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output sink8_ready,
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input sink9_valid,
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input [108-1 : 0] sink9_data,
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input [14-1: 0] sink9_channel,
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input sink9_startofpacket,
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input sink9_endofpacket,
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output sink9_ready,
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input sink10_valid,
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input [108-1 : 0] sink10_data,
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input [14-1: 0] sink10_channel,
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input sink10_startofpacket,
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input sink10_endofpacket,
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output sink10_ready,
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input sink11_valid,
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input [108-1 : 0] sink11_data,
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input [14-1: 0] sink11_channel,
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input sink11_startofpacket,
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input sink11_endofpacket,
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output sink11_ready,
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input sink12_valid,
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input [108-1 : 0] sink12_data,
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input [14-1: 0] sink12_channel,
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input sink12_startofpacket,
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input sink12_endofpacket,
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output sink12_ready,
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input sink13_valid,
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input [108-1 : 0] sink13_data,
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input [14-1: 0] sink13_channel,
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input sink13_startofpacket,
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input sink13_endofpacket,
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output sink13_ready,
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// ----------------------
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// Source
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// ----------------------
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output src_valid,
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output [108-1 : 0] src_data,
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output [14-1 : 0] src_channel,
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output src_startofpacket,
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output src_endofpacket,
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input src_ready,
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// ----------------------
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// Clock & Reset
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// ----------------------
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input clk,
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input reset
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);
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localparam PAYLOAD_W = 108 + 14 + 2;
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localparam NUM_INPUTS = 14;
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localparam SHARE_COUNTER_W = 1;
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localparam PIPELINE_ARB = 1;
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localparam ST_DATA_W = 108;
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localparam ST_CHANNEL_W = 14;
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localparam PKT_TRANS_LOCK = 72;
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// ------------------------------------------
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// Signals
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// ------------------------------------------
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wire [NUM_INPUTS - 1 : 0] request;
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wire [NUM_INPUTS - 1 : 0] valid;
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wire [NUM_INPUTS - 1 : 0] grant;
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wire [NUM_INPUTS - 1 : 0] next_grant;
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reg [NUM_INPUTS - 1 : 0] saved_grant;
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reg [PAYLOAD_W - 1 : 0] src_payload;
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wire last_cycle;
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reg packet_in_progress;
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reg update_grant;
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wire [PAYLOAD_W - 1 : 0] sink0_payload;
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wire [PAYLOAD_W - 1 : 0] sink1_payload;
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wire [PAYLOAD_W - 1 : 0] sink2_payload;
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wire [PAYLOAD_W - 1 : 0] sink3_payload;
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wire [PAYLOAD_W - 1 : 0] sink4_payload;
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wire [PAYLOAD_W - 1 : 0] sink5_payload;
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wire [PAYLOAD_W - 1 : 0] sink6_payload;
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wire [PAYLOAD_W - 1 : 0] sink7_payload;
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wire [PAYLOAD_W - 1 : 0] sink8_payload;
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wire [PAYLOAD_W - 1 : 0] sink9_payload;
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wire [PAYLOAD_W - 1 : 0] sink10_payload;
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wire [PAYLOAD_W - 1 : 0] sink11_payload;
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wire [PAYLOAD_W - 1 : 0] sink12_payload;
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wire [PAYLOAD_W - 1 : 0] sink13_payload;
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assign valid[0] = sink0_valid;
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assign valid[1] = sink1_valid;
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assign valid[2] = sink2_valid;
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assign valid[3] = sink3_valid;
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assign valid[4] = sink4_valid;
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assign valid[5] = sink5_valid;
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assign valid[6] = sink6_valid;
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assign valid[7] = sink7_valid;
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assign valid[8] = sink8_valid;
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assign valid[9] = sink9_valid;
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assign valid[10] = sink10_valid;
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assign valid[11] = sink11_valid;
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assign valid[12] = sink12_valid;
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assign valid[13] = sink13_valid;
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wire [NUM_INPUTS - 1 : 0] eop;
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assign eop[0] = sink0_endofpacket;
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assign eop[1] = sink1_endofpacket;
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assign eop[2] = sink2_endofpacket;
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assign eop[3] = sink3_endofpacket;
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assign eop[4] = sink4_endofpacket;
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assign eop[5] = sink5_endofpacket;
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assign eop[6] = sink6_endofpacket;
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assign eop[7] = sink7_endofpacket;
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assign eop[8] = sink8_endofpacket;
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assign eop[9] = sink9_endofpacket;
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assign eop[10] = sink10_endofpacket;
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assign eop[11] = sink11_endofpacket;
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assign eop[12] = sink12_endofpacket;
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assign eop[13] = sink13_endofpacket;
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// ------------------------------------------
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// ------------------------------------------
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// Grant Logic & Updates
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// ------------------------------------------
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// ------------------------------------------
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reg [NUM_INPUTS - 1 : 0] lock;
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always @* begin
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lock[0] = sink0_data[72];
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lock[1] = sink1_data[72];
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lock[2] = sink2_data[72];
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lock[3] = sink3_data[72];
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lock[4] = sink4_data[72];
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lock[5] = sink5_data[72];
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lock[6] = sink6_data[72];
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lock[7] = sink7_data[72];
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lock[8] = sink8_data[72];
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lock[9] = sink9_data[72];
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lock[10] = sink10_data[72];
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lock[11] = sink11_data[72];
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lock[12] = sink12_data[72];
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lock[13] = sink13_data[72];
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end
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reg [NUM_INPUTS - 1 : 0] locked = '0;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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locked <= '0;
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end
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else begin
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locked <= next_grant & lock;
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end
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end
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assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
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// ------------------------------------------
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// We're working on a packet at any time valid is high, except
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// when this is the endofpacket.
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// ------------------------------------------
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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packet_in_progress <= 1'b0;
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end
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else begin
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if (last_cycle)
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packet_in_progress <= 1'b0;
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else if (src_valid)
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packet_in_progress <= 1'b1;
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end
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end
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// ------------------------------------------
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// Shares
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//
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// Special case: all-equal shares _should_ be optimized into assigning a
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// constant to next_grant_share.
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// Special case: all-1's shares _should_ result in the share counter
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// being optimized away.
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// ------------------------------------------
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// Input | arb shares | counter load value
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// 0 | 1 | 0
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// 1 | 1 | 0
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// 2 | 1 | 0
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// 3 | 1 | 0
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// 4 | 1 | 0
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// 5 | 1 | 0
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// 6 | 1 | 0
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// 7 | 1 | 0
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// 8 | 1 | 0
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// 9 | 1 | 0
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// 10 | 1 | 0
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// 11 | 1 | 0
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// 12 | 1 | 0
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// 13 | 1 | 0
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wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0;
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// ------------------------------------------
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// Choose the share value corresponding to the grant.
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// ------------------------------------------
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reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
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always @* begin
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next_grant_share =
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share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
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share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
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share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
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share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
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share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
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share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
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share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
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share_7 & { SHARE_COUNTER_W {next_grant[7]} } |
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share_8 & { SHARE_COUNTER_W {next_grant[8]} } |
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share_9 & { SHARE_COUNTER_W {next_grant[9]} } |
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share_10 & { SHARE_COUNTER_W {next_grant[10]} } |
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share_11 & { SHARE_COUNTER_W {next_grant[11]} } |
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share_12 & { SHARE_COUNTER_W {next_grant[12]} } |
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share_13 & { SHARE_COUNTER_W {next_grant[13]} };
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end
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// ------------------------------------------
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// Flag to indicate first packet of an arb sequence.
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// ------------------------------------------
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// ------------------------------------------
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// Compute the next share-count value.
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// ------------------------------------------
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reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
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reg [SHARE_COUNTER_W - 1 : 0] share_count;
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reg share_count_zero_flag;
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always @* begin
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// Update the counter, but don't decrement below 0.
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p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
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end
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// ------------------------------------------
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// Update the share counter and share-counter=zero flag.
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// ------------------------------------------
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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share_count <= '0;
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share_count_zero_flag <= 1'b1;
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end
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else begin
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if (update_grant) begin
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share_count <= next_grant_share;
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share_count_zero_flag <= (next_grant_share == '0);
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end
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else if (last_cycle) begin
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share_count <= p1_share_count;
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share_count_zero_flag <= (p1_share_count == '0);
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end
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end
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end
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always @* begin
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update_grant = 0;
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// ------------------------------------------
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// The pipeline delays grant by one cycle, so
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// we have to calculate the update_grant signal
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// one cycle ahead of time.
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//
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// Possible optimization: omit the first clause
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// "if (!packet_in_progress & ~src_valid) ..."
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// cost: one idle cycle at the the beginning of each
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// grant cycle.
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// benefit: save a small amount of logic.
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// ------------------------------------------
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if (!packet_in_progress & !src_valid)
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update_grant = 1;
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if (last_cycle && share_count_zero_flag)
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update_grant = 1;
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end
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wire save_grant;
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assign save_grant = update_grant;
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assign grant = saved_grant;
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always @(posedge clk, posedge reset) begin
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if (reset)
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saved_grant <= '0;
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else if (save_grant)
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saved_grant <= next_grant;
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end
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// ------------------------------------------
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// ------------------------------------------
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// Arbitrator
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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// Create a request vector that stays high during
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// the packet for unpipelined arbitration.
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//
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// The pipelined arbitration scheme does not require
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// request to be held high during the packet.
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// ------------------------------------------
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reg [NUM_INPUTS - 1 : 0] prev_request;
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always @(posedge clk, posedge reset) begin
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if (reset)
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prev_request <= '0;
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else
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prev_request <= request & ~(valid & eop);
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end
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assign request = (PIPELINE_ARB == 1) ? valid | locked :
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prev_request | valid | locked;
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wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
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altera_merlin_arbitrator
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#(
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.NUM_REQUESTERS(NUM_INPUTS),
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.SCHEME ("round-robin"),
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.PIPELINE (1)
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) arb (
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.clk (clk),
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.reset (reset),
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.request (request),
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.grant (next_grant_from_arb),
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.save_top_priority (src_valid),
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.increment_top_priority (update_grant)
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);
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assign next_grant = next_grant_from_arb;
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// ------------------------------------------
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// ------------------------------------------
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// Mux
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//
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// Implemented as a sum of products.
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// ------------------------------------------
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// ------------------------------------------
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assign sink0_ready = src_ready && grant[0];
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assign sink1_ready = src_ready && grant[1];
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assign sink2_ready = src_ready && grant[2];
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assign sink3_ready = src_ready && grant[3];
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assign sink4_ready = src_ready && grant[4];
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assign sink5_ready = src_ready && grant[5];
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assign sink6_ready = src_ready && grant[6];
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assign sink7_ready = src_ready && grant[7];
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assign sink8_ready = src_ready && grant[8];
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assign sink9_ready = src_ready && grant[9];
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assign sink10_ready = src_ready && grant[10];
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assign sink11_ready = src_ready && grant[11];
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assign sink12_ready = src_ready && grant[12];
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assign sink13_ready = src_ready && grant[13];
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assign src_valid = |(grant & valid);
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always @* begin
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src_payload =
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sink0_payload & {PAYLOAD_W {grant[0]} } |
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sink1_payload & {PAYLOAD_W {grant[1]} } |
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sink2_payload & {PAYLOAD_W {grant[2]} } |
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sink3_payload & {PAYLOAD_W {grant[3]} } |
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sink4_payload & {PAYLOAD_W {grant[4]} } |
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sink5_payload & {PAYLOAD_W {grant[5]} } |
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sink6_payload & {PAYLOAD_W {grant[6]} } |
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sink7_payload & {PAYLOAD_W {grant[7]} } |
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sink8_payload & {PAYLOAD_W {grant[8]} } |
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sink9_payload & {PAYLOAD_W {grant[9]} } |
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sink10_payload & {PAYLOAD_W {grant[10]} } |
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sink11_payload & {PAYLOAD_W {grant[11]} } |
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sink12_payload & {PAYLOAD_W {grant[12]} } |
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sink13_payload & {PAYLOAD_W {grant[13]} };
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end
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// ------------------------------------------
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// Mux Payload Mapping
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// ------------------------------------------
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assign sink0_payload = {sink0_channel,sink0_data,
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sink0_startofpacket,sink0_endofpacket};
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assign sink1_payload = {sink1_channel,sink1_data,
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sink1_startofpacket,sink1_endofpacket};
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assign sink2_payload = {sink2_channel,sink2_data,
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sink2_startofpacket,sink2_endofpacket};
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assign sink3_payload = {sink3_channel,sink3_data,
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sink3_startofpacket,sink3_endofpacket};
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assign sink4_payload = {sink4_channel,sink4_data,
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sink4_startofpacket,sink4_endofpacket};
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assign sink5_payload = {sink5_channel,sink5_data,
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sink5_startofpacket,sink5_endofpacket};
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assign sink6_payload = {sink6_channel,sink6_data,
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sink6_startofpacket,sink6_endofpacket};
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assign sink7_payload = {sink7_channel,sink7_data,
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sink7_startofpacket,sink7_endofpacket};
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assign sink8_payload = {sink8_channel,sink8_data,
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sink8_startofpacket,sink8_endofpacket};
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assign sink9_payload = {sink9_channel,sink9_data,
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sink9_startofpacket,sink9_endofpacket};
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assign sink10_payload = {sink10_channel,sink10_data,
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|
sink10_startofpacket,sink10_endofpacket};
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assign sink11_payload = {sink11_channel,sink11_data,
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sink11_startofpacket,sink11_endofpacket};
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assign sink12_payload = {sink12_channel,sink12_data,
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|
sink12_startofpacket,sink12_endofpacket};
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assign sink13_payload = {sink13_channel,sink13_data,
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|
sink13_startofpacket,sink13_endofpacket};
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|
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assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
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endmodule
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