4077 lines
360 KiB
Verilog
4077 lines
360 KiB
Verilog
// ECE385_mm_interconnect_2.v
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// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
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// will probably be lost.
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//
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// Generated using ACDS version 18.1 625
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`timescale 1 ps / 1 ps
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module ECE385_mm_interconnect_2 (
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input wire clk_0_clk_clk, // clk_0_clk.clk
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input wire eth0_rx_dma_reset_reset_bridge_in_reset_reset, // eth0_rx_dma_reset_reset_bridge_in_reset.reset
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input wire [31:0] eth0_rx_dma_descriptor_read_address, // eth0_rx_dma_descriptor_read.address
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output wire eth0_rx_dma_descriptor_read_waitrequest, // .waitrequest
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input wire eth0_rx_dma_descriptor_read_read, // .read
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output wire [31:0] eth0_rx_dma_descriptor_read_readdata, // .readdata
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output wire eth0_rx_dma_descriptor_read_readdatavalid, // .readdatavalid
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input wire [31:0] eth0_rx_dma_descriptor_write_address, // eth0_rx_dma_descriptor_write.address
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output wire eth0_rx_dma_descriptor_write_waitrequest, // .waitrequest
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input wire eth0_rx_dma_descriptor_write_write, // .write
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input wire [31:0] eth0_rx_dma_descriptor_write_writedata, // .writedata
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input wire [31:0] eth0_rx_dma_m_write_address, // eth0_rx_dma_m_write.address
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output wire eth0_rx_dma_m_write_waitrequest, // .waitrequest
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input wire eth0_rx_dma_m_write_write, // .write
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input wire [7:0] eth0_rx_dma_m_write_writedata, // .writedata
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input wire [31:0] eth0_tx_dma_descriptor_read_address, // eth0_tx_dma_descriptor_read.address
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output wire eth0_tx_dma_descriptor_read_waitrequest, // .waitrequest
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input wire eth0_tx_dma_descriptor_read_read, // .read
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output wire [31:0] eth0_tx_dma_descriptor_read_readdata, // .readdata
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output wire eth0_tx_dma_descriptor_read_readdatavalid, // .readdatavalid
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input wire [31:0] eth0_tx_dma_descriptor_write_address, // eth0_tx_dma_descriptor_write.address
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output wire eth0_tx_dma_descriptor_write_waitrequest, // .waitrequest
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input wire eth0_tx_dma_descriptor_write_write, // .write
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input wire [31:0] eth0_tx_dma_descriptor_write_writedata, // .writedata
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input wire [31:0] eth0_tx_dma_m_read_address, // eth0_tx_dma_m_read.address
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output wire eth0_tx_dma_m_read_waitrequest, // .waitrequest
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input wire eth0_tx_dma_m_read_read, // .read
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output wire [31:0] eth0_tx_dma_m_read_readdata, // .readdata
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output wire eth0_tx_dma_m_read_readdatavalid, // .readdatavalid
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input wire [31:0] eth1_rx_dma_descriptor_read_address, // eth1_rx_dma_descriptor_read.address
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output wire eth1_rx_dma_descriptor_read_waitrequest, // .waitrequest
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input wire eth1_rx_dma_descriptor_read_read, // .read
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output wire [31:0] eth1_rx_dma_descriptor_read_readdata, // .readdata
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output wire eth1_rx_dma_descriptor_read_readdatavalid, // .readdatavalid
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input wire [31:0] eth1_rx_dma_descriptor_write_address, // eth1_rx_dma_descriptor_write.address
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output wire eth1_rx_dma_descriptor_write_waitrequest, // .waitrequest
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input wire eth1_rx_dma_descriptor_write_write, // .write
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input wire [31:0] eth1_rx_dma_descriptor_write_writedata, // .writedata
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input wire [31:0] eth1_rx_dma_m_write_address, // eth1_rx_dma_m_write.address
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output wire eth1_rx_dma_m_write_waitrequest, // .waitrequest
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input wire eth1_rx_dma_m_write_write, // .write
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input wire [7:0] eth1_rx_dma_m_write_writedata, // .writedata
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input wire [31:0] eth1_tx_dma_descriptor_read_address, // eth1_tx_dma_descriptor_read.address
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output wire eth1_tx_dma_descriptor_read_waitrequest, // .waitrequest
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input wire eth1_tx_dma_descriptor_read_read, // .read
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output wire [31:0] eth1_tx_dma_descriptor_read_readdata, // .readdata
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output wire eth1_tx_dma_descriptor_read_readdatavalid, // .readdatavalid
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input wire [31:0] eth1_tx_dma_descriptor_write_address, // eth1_tx_dma_descriptor_write.address
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output wire eth1_tx_dma_descriptor_write_waitrequest, // .waitrequest
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input wire eth1_tx_dma_descriptor_write_write, // .write
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input wire [31:0] eth1_tx_dma_descriptor_write_writedata, // .writedata
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input wire [31:0] eth1_tx_dma_m_read_address, // eth1_tx_dma_m_read.address
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output wire eth1_tx_dma_m_read_waitrequest, // .waitrequest
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input wire eth1_tx_dma_m_read_read, // .read
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output wire [31:0] eth1_tx_dma_m_read_readdata, // .readdata
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output wire eth1_tx_dma_m_read_readdatavalid, // .readdatavalid
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input wire [31:0] nios2_dma_descriptor_read_address, // nios2_dma_descriptor_read.address
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output wire nios2_dma_descriptor_read_waitrequest, // .waitrequest
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input wire nios2_dma_descriptor_read_read, // .read
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output wire [31:0] nios2_dma_descriptor_read_readdata, // .readdata
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output wire nios2_dma_descriptor_read_readdatavalid, // .readdatavalid
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input wire [31:0] nios2_dma_descriptor_write_address, // nios2_dma_descriptor_write.address
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output wire nios2_dma_descriptor_write_waitrequest, // .waitrequest
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input wire nios2_dma_descriptor_write_write, // .write
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input wire [31:0] nios2_dma_descriptor_write_writedata, // .writedata
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output wire [15:0] nios2_onchip_mem_s2_address, // nios2_onchip_mem_s2.address
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output wire nios2_onchip_mem_s2_write, // .write
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input wire [31:0] nios2_onchip_mem_s2_readdata, // .readdata
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output wire [31:0] nios2_onchip_mem_s2_writedata, // .writedata
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output wire [3:0] nios2_onchip_mem_s2_byteenable, // .byteenable
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output wire nios2_onchip_mem_s2_chipselect, // .chipselect
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output wire nios2_onchip_mem_s2_clken // .clken
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);
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wire eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest; // eth0_rx_dma_descriptor_read_agent:av_waitrequest -> eth0_rx_dma_descriptor_read_translator:uav_waitrequest
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wire [31:0] eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdata; // eth0_rx_dma_descriptor_read_agent:av_readdata -> eth0_rx_dma_descriptor_read_translator:uav_readdata
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wire eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess; // eth0_rx_dma_descriptor_read_translator:uav_debugaccess -> eth0_rx_dma_descriptor_read_agent:av_debugaccess
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wire [31:0] eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_address; // eth0_rx_dma_descriptor_read_translator:uav_address -> eth0_rx_dma_descriptor_read_agent:av_address
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wire eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_read; // eth0_rx_dma_descriptor_read_translator:uav_read -> eth0_rx_dma_descriptor_read_agent:av_read
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wire [3:0] eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable; // eth0_rx_dma_descriptor_read_translator:uav_byteenable -> eth0_rx_dma_descriptor_read_agent:av_byteenable
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wire eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid; // eth0_rx_dma_descriptor_read_agent:av_readdatavalid -> eth0_rx_dma_descriptor_read_translator:uav_readdatavalid
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wire eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_lock; // eth0_rx_dma_descriptor_read_translator:uav_lock -> eth0_rx_dma_descriptor_read_agent:av_lock
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wire eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_write; // eth0_rx_dma_descriptor_read_translator:uav_write -> eth0_rx_dma_descriptor_read_agent:av_write
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wire [31:0] eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_writedata; // eth0_rx_dma_descriptor_read_translator:uav_writedata -> eth0_rx_dma_descriptor_read_agent:av_writedata
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wire [2:0] eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount; // eth0_rx_dma_descriptor_read_translator:uav_burstcount -> eth0_rx_dma_descriptor_read_agent:av_burstcount
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wire rsp_mux_src_valid; // rsp_mux:src_valid -> eth0_rx_dma_descriptor_read_agent:rp_valid
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wire [107:0] rsp_mux_src_data; // rsp_mux:src_data -> eth0_rx_dma_descriptor_read_agent:rp_data
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wire rsp_mux_src_ready; // eth0_rx_dma_descriptor_read_agent:rp_ready -> rsp_mux:src_ready
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wire [13:0] rsp_mux_src_channel; // rsp_mux:src_channel -> eth0_rx_dma_descriptor_read_agent:rp_channel
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wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> eth0_rx_dma_descriptor_read_agent:rp_startofpacket
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wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> eth0_rx_dma_descriptor_read_agent:rp_endofpacket
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wire eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest; // eth0_tx_dma_descriptor_read_agent:av_waitrequest -> eth0_tx_dma_descriptor_read_translator:uav_waitrequest
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wire [31:0] eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdata; // eth0_tx_dma_descriptor_read_agent:av_readdata -> eth0_tx_dma_descriptor_read_translator:uav_readdata
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wire eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess; // eth0_tx_dma_descriptor_read_translator:uav_debugaccess -> eth0_tx_dma_descriptor_read_agent:av_debugaccess
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wire [31:0] eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_address; // eth0_tx_dma_descriptor_read_translator:uav_address -> eth0_tx_dma_descriptor_read_agent:av_address
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wire eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_read; // eth0_tx_dma_descriptor_read_translator:uav_read -> eth0_tx_dma_descriptor_read_agent:av_read
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wire [3:0] eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable; // eth0_tx_dma_descriptor_read_translator:uav_byteenable -> eth0_tx_dma_descriptor_read_agent:av_byteenable
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wire eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid; // eth0_tx_dma_descriptor_read_agent:av_readdatavalid -> eth0_tx_dma_descriptor_read_translator:uav_readdatavalid
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wire eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_lock; // eth0_tx_dma_descriptor_read_translator:uav_lock -> eth0_tx_dma_descriptor_read_agent:av_lock
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wire eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_write; // eth0_tx_dma_descriptor_read_translator:uav_write -> eth0_tx_dma_descriptor_read_agent:av_write
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wire [31:0] eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_writedata; // eth0_tx_dma_descriptor_read_translator:uav_writedata -> eth0_tx_dma_descriptor_read_agent:av_writedata
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wire [2:0] eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount; // eth0_tx_dma_descriptor_read_translator:uav_burstcount -> eth0_tx_dma_descriptor_read_agent:av_burstcount
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wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> eth0_tx_dma_descriptor_read_agent:rp_valid
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wire [107:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> eth0_tx_dma_descriptor_read_agent:rp_data
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wire rsp_mux_001_src_ready; // eth0_tx_dma_descriptor_read_agent:rp_ready -> rsp_mux_001:src_ready
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wire [13:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> eth0_tx_dma_descriptor_read_agent:rp_channel
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wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> eth0_tx_dma_descriptor_read_agent:rp_startofpacket
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wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> eth0_tx_dma_descriptor_read_agent:rp_endofpacket
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wire eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest; // eth1_rx_dma_descriptor_read_agent:av_waitrequest -> eth1_rx_dma_descriptor_read_translator:uav_waitrequest
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wire [31:0] eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdata; // eth1_rx_dma_descriptor_read_agent:av_readdata -> eth1_rx_dma_descriptor_read_translator:uav_readdata
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wire eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess; // eth1_rx_dma_descriptor_read_translator:uav_debugaccess -> eth1_rx_dma_descriptor_read_agent:av_debugaccess
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wire [31:0] eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_address; // eth1_rx_dma_descriptor_read_translator:uav_address -> eth1_rx_dma_descriptor_read_agent:av_address
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wire eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_read; // eth1_rx_dma_descriptor_read_translator:uav_read -> eth1_rx_dma_descriptor_read_agent:av_read
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wire [3:0] eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable; // eth1_rx_dma_descriptor_read_translator:uav_byteenable -> eth1_rx_dma_descriptor_read_agent:av_byteenable
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wire eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid; // eth1_rx_dma_descriptor_read_agent:av_readdatavalid -> eth1_rx_dma_descriptor_read_translator:uav_readdatavalid
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wire eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_lock; // eth1_rx_dma_descriptor_read_translator:uav_lock -> eth1_rx_dma_descriptor_read_agent:av_lock
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wire eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_write; // eth1_rx_dma_descriptor_read_translator:uav_write -> eth1_rx_dma_descriptor_read_agent:av_write
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wire [31:0] eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_writedata; // eth1_rx_dma_descriptor_read_translator:uav_writedata -> eth1_rx_dma_descriptor_read_agent:av_writedata
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wire [2:0] eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount; // eth1_rx_dma_descriptor_read_translator:uav_burstcount -> eth1_rx_dma_descriptor_read_agent:av_burstcount
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wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> eth1_rx_dma_descriptor_read_agent:rp_valid
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wire [107:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> eth1_rx_dma_descriptor_read_agent:rp_data
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wire rsp_mux_002_src_ready; // eth1_rx_dma_descriptor_read_agent:rp_ready -> rsp_mux_002:src_ready
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wire [13:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> eth1_rx_dma_descriptor_read_agent:rp_channel
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wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> eth1_rx_dma_descriptor_read_agent:rp_startofpacket
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wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> eth1_rx_dma_descriptor_read_agent:rp_endofpacket
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wire eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest; // eth1_tx_dma_descriptor_read_agent:av_waitrequest -> eth1_tx_dma_descriptor_read_translator:uav_waitrequest
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wire [31:0] eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdata; // eth1_tx_dma_descriptor_read_agent:av_readdata -> eth1_tx_dma_descriptor_read_translator:uav_readdata
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wire eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess; // eth1_tx_dma_descriptor_read_translator:uav_debugaccess -> eth1_tx_dma_descriptor_read_agent:av_debugaccess
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wire [31:0] eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_address; // eth1_tx_dma_descriptor_read_translator:uav_address -> eth1_tx_dma_descriptor_read_agent:av_address
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wire eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_read; // eth1_tx_dma_descriptor_read_translator:uav_read -> eth1_tx_dma_descriptor_read_agent:av_read
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wire [3:0] eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable; // eth1_tx_dma_descriptor_read_translator:uav_byteenable -> eth1_tx_dma_descriptor_read_agent:av_byteenable
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wire eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid; // eth1_tx_dma_descriptor_read_agent:av_readdatavalid -> eth1_tx_dma_descriptor_read_translator:uav_readdatavalid
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wire eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_lock; // eth1_tx_dma_descriptor_read_translator:uav_lock -> eth1_tx_dma_descriptor_read_agent:av_lock
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wire eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_write; // eth1_tx_dma_descriptor_read_translator:uav_write -> eth1_tx_dma_descriptor_read_agent:av_write
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wire [31:0] eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_writedata; // eth1_tx_dma_descriptor_read_translator:uav_writedata -> eth1_tx_dma_descriptor_read_agent:av_writedata
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wire [2:0] eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount; // eth1_tx_dma_descriptor_read_translator:uav_burstcount -> eth1_tx_dma_descriptor_read_agent:av_burstcount
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wire rsp_mux_003_src_valid; // rsp_mux_003:src_valid -> eth1_tx_dma_descriptor_read_agent:rp_valid
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wire [107:0] rsp_mux_003_src_data; // rsp_mux_003:src_data -> eth1_tx_dma_descriptor_read_agent:rp_data
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wire rsp_mux_003_src_ready; // eth1_tx_dma_descriptor_read_agent:rp_ready -> rsp_mux_003:src_ready
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wire [13:0] rsp_mux_003_src_channel; // rsp_mux_003:src_channel -> eth1_tx_dma_descriptor_read_agent:rp_channel
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wire rsp_mux_003_src_startofpacket; // rsp_mux_003:src_startofpacket -> eth1_tx_dma_descriptor_read_agent:rp_startofpacket
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wire rsp_mux_003_src_endofpacket; // rsp_mux_003:src_endofpacket -> eth1_tx_dma_descriptor_read_agent:rp_endofpacket
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wire nios2_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest; // nios2_dma_descriptor_read_agent:av_waitrequest -> nios2_dma_descriptor_read_translator:uav_waitrequest
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wire [31:0] nios2_dma_descriptor_read_translator_avalon_universal_master_0_readdata; // nios2_dma_descriptor_read_agent:av_readdata -> nios2_dma_descriptor_read_translator:uav_readdata
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wire nios2_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess; // nios2_dma_descriptor_read_translator:uav_debugaccess -> nios2_dma_descriptor_read_agent:av_debugaccess
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wire [31:0] nios2_dma_descriptor_read_translator_avalon_universal_master_0_address; // nios2_dma_descriptor_read_translator:uav_address -> nios2_dma_descriptor_read_agent:av_address
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wire nios2_dma_descriptor_read_translator_avalon_universal_master_0_read; // nios2_dma_descriptor_read_translator:uav_read -> nios2_dma_descriptor_read_agent:av_read
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wire [3:0] nios2_dma_descriptor_read_translator_avalon_universal_master_0_byteenable; // nios2_dma_descriptor_read_translator:uav_byteenable -> nios2_dma_descriptor_read_agent:av_byteenable
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wire nios2_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid; // nios2_dma_descriptor_read_agent:av_readdatavalid -> nios2_dma_descriptor_read_translator:uav_readdatavalid
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wire nios2_dma_descriptor_read_translator_avalon_universal_master_0_lock; // nios2_dma_descriptor_read_translator:uav_lock -> nios2_dma_descriptor_read_agent:av_lock
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wire nios2_dma_descriptor_read_translator_avalon_universal_master_0_write; // nios2_dma_descriptor_read_translator:uav_write -> nios2_dma_descriptor_read_agent:av_write
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wire [31:0] nios2_dma_descriptor_read_translator_avalon_universal_master_0_writedata; // nios2_dma_descriptor_read_translator:uav_writedata -> nios2_dma_descriptor_read_agent:av_writedata
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wire [2:0] nios2_dma_descriptor_read_translator_avalon_universal_master_0_burstcount; // nios2_dma_descriptor_read_translator:uav_burstcount -> nios2_dma_descriptor_read_agent:av_burstcount
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wire rsp_mux_004_src_valid; // rsp_mux_004:src_valid -> nios2_dma_descriptor_read_agent:rp_valid
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wire [107:0] rsp_mux_004_src_data; // rsp_mux_004:src_data -> nios2_dma_descriptor_read_agent:rp_data
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wire rsp_mux_004_src_ready; // nios2_dma_descriptor_read_agent:rp_ready -> rsp_mux_004:src_ready
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wire [13:0] rsp_mux_004_src_channel; // rsp_mux_004:src_channel -> nios2_dma_descriptor_read_agent:rp_channel
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wire rsp_mux_004_src_startofpacket; // rsp_mux_004:src_startofpacket -> nios2_dma_descriptor_read_agent:rp_startofpacket
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wire rsp_mux_004_src_endofpacket; // rsp_mux_004:src_endofpacket -> nios2_dma_descriptor_read_agent:rp_endofpacket
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wire eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest; // eth0_rx_dma_descriptor_write_agent:av_waitrequest -> eth0_rx_dma_descriptor_write_translator:uav_waitrequest
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wire [31:0] eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdata; // eth0_rx_dma_descriptor_write_agent:av_readdata -> eth0_rx_dma_descriptor_write_translator:uav_readdata
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wire eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess; // eth0_rx_dma_descriptor_write_translator:uav_debugaccess -> eth0_rx_dma_descriptor_write_agent:av_debugaccess
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wire [31:0] eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_address; // eth0_rx_dma_descriptor_write_translator:uav_address -> eth0_rx_dma_descriptor_write_agent:av_address
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wire eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_read; // eth0_rx_dma_descriptor_write_translator:uav_read -> eth0_rx_dma_descriptor_write_agent:av_read
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wire [3:0] eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable; // eth0_rx_dma_descriptor_write_translator:uav_byteenable -> eth0_rx_dma_descriptor_write_agent:av_byteenable
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wire eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid; // eth0_rx_dma_descriptor_write_agent:av_readdatavalid -> eth0_rx_dma_descriptor_write_translator:uav_readdatavalid
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wire eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_lock; // eth0_rx_dma_descriptor_write_translator:uav_lock -> eth0_rx_dma_descriptor_write_agent:av_lock
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wire eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_write; // eth0_rx_dma_descriptor_write_translator:uav_write -> eth0_rx_dma_descriptor_write_agent:av_write
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wire [31:0] eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_writedata; // eth0_rx_dma_descriptor_write_translator:uav_writedata -> eth0_rx_dma_descriptor_write_agent:av_writedata
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wire [2:0] eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount; // eth0_rx_dma_descriptor_write_translator:uav_burstcount -> eth0_rx_dma_descriptor_write_agent:av_burstcount
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wire rsp_mux_005_src_valid; // rsp_mux_005:src_valid -> eth0_rx_dma_descriptor_write_agent:rp_valid
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wire [107:0] rsp_mux_005_src_data; // rsp_mux_005:src_data -> eth0_rx_dma_descriptor_write_agent:rp_data
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wire rsp_mux_005_src_ready; // eth0_rx_dma_descriptor_write_agent:rp_ready -> rsp_mux_005:src_ready
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wire [13:0] rsp_mux_005_src_channel; // rsp_mux_005:src_channel -> eth0_rx_dma_descriptor_write_agent:rp_channel
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wire rsp_mux_005_src_startofpacket; // rsp_mux_005:src_startofpacket -> eth0_rx_dma_descriptor_write_agent:rp_startofpacket
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wire rsp_mux_005_src_endofpacket; // rsp_mux_005:src_endofpacket -> eth0_rx_dma_descriptor_write_agent:rp_endofpacket
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wire eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest; // eth0_tx_dma_descriptor_write_agent:av_waitrequest -> eth0_tx_dma_descriptor_write_translator:uav_waitrequest
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wire [31:0] eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdata; // eth0_tx_dma_descriptor_write_agent:av_readdata -> eth0_tx_dma_descriptor_write_translator:uav_readdata
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wire eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess; // eth0_tx_dma_descriptor_write_translator:uav_debugaccess -> eth0_tx_dma_descriptor_write_agent:av_debugaccess
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wire [31:0] eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_address; // eth0_tx_dma_descriptor_write_translator:uav_address -> eth0_tx_dma_descriptor_write_agent:av_address
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wire eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_read; // eth0_tx_dma_descriptor_write_translator:uav_read -> eth0_tx_dma_descriptor_write_agent:av_read
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wire [3:0] eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable; // eth0_tx_dma_descriptor_write_translator:uav_byteenable -> eth0_tx_dma_descriptor_write_agent:av_byteenable
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wire eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid; // eth0_tx_dma_descriptor_write_agent:av_readdatavalid -> eth0_tx_dma_descriptor_write_translator:uav_readdatavalid
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wire eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_lock; // eth0_tx_dma_descriptor_write_translator:uav_lock -> eth0_tx_dma_descriptor_write_agent:av_lock
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wire eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_write; // eth0_tx_dma_descriptor_write_translator:uav_write -> eth0_tx_dma_descriptor_write_agent:av_write
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wire [31:0] eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_writedata; // eth0_tx_dma_descriptor_write_translator:uav_writedata -> eth0_tx_dma_descriptor_write_agent:av_writedata
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wire [2:0] eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount; // eth0_tx_dma_descriptor_write_translator:uav_burstcount -> eth0_tx_dma_descriptor_write_agent:av_burstcount
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wire rsp_mux_006_src_valid; // rsp_mux_006:src_valid -> eth0_tx_dma_descriptor_write_agent:rp_valid
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wire [107:0] rsp_mux_006_src_data; // rsp_mux_006:src_data -> eth0_tx_dma_descriptor_write_agent:rp_data
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wire rsp_mux_006_src_ready; // eth0_tx_dma_descriptor_write_agent:rp_ready -> rsp_mux_006:src_ready
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wire [13:0] rsp_mux_006_src_channel; // rsp_mux_006:src_channel -> eth0_tx_dma_descriptor_write_agent:rp_channel
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wire rsp_mux_006_src_startofpacket; // rsp_mux_006:src_startofpacket -> eth0_tx_dma_descriptor_write_agent:rp_startofpacket
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wire rsp_mux_006_src_endofpacket; // rsp_mux_006:src_endofpacket -> eth0_tx_dma_descriptor_write_agent:rp_endofpacket
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wire eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest; // eth1_rx_dma_descriptor_write_agent:av_waitrequest -> eth1_rx_dma_descriptor_write_translator:uav_waitrequest
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wire [31:0] eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdata; // eth1_rx_dma_descriptor_write_agent:av_readdata -> eth1_rx_dma_descriptor_write_translator:uav_readdata
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wire eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess; // eth1_rx_dma_descriptor_write_translator:uav_debugaccess -> eth1_rx_dma_descriptor_write_agent:av_debugaccess
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wire [31:0] eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_address; // eth1_rx_dma_descriptor_write_translator:uav_address -> eth1_rx_dma_descriptor_write_agent:av_address
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wire eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_read; // eth1_rx_dma_descriptor_write_translator:uav_read -> eth1_rx_dma_descriptor_write_agent:av_read
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wire [3:0] eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable; // eth1_rx_dma_descriptor_write_translator:uav_byteenable -> eth1_rx_dma_descriptor_write_agent:av_byteenable
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wire eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid; // eth1_rx_dma_descriptor_write_agent:av_readdatavalid -> eth1_rx_dma_descriptor_write_translator:uav_readdatavalid
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wire eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_lock; // eth1_rx_dma_descriptor_write_translator:uav_lock -> eth1_rx_dma_descriptor_write_agent:av_lock
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wire eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_write; // eth1_rx_dma_descriptor_write_translator:uav_write -> eth1_rx_dma_descriptor_write_agent:av_write
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wire [31:0] eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_writedata; // eth1_rx_dma_descriptor_write_translator:uav_writedata -> eth1_rx_dma_descriptor_write_agent:av_writedata
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wire [2:0] eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount; // eth1_rx_dma_descriptor_write_translator:uav_burstcount -> eth1_rx_dma_descriptor_write_agent:av_burstcount
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wire rsp_mux_007_src_valid; // rsp_mux_007:src_valid -> eth1_rx_dma_descriptor_write_agent:rp_valid
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wire [107:0] rsp_mux_007_src_data; // rsp_mux_007:src_data -> eth1_rx_dma_descriptor_write_agent:rp_data
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wire rsp_mux_007_src_ready; // eth1_rx_dma_descriptor_write_agent:rp_ready -> rsp_mux_007:src_ready
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wire [13:0] rsp_mux_007_src_channel; // rsp_mux_007:src_channel -> eth1_rx_dma_descriptor_write_agent:rp_channel
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wire rsp_mux_007_src_startofpacket; // rsp_mux_007:src_startofpacket -> eth1_rx_dma_descriptor_write_agent:rp_startofpacket
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wire rsp_mux_007_src_endofpacket; // rsp_mux_007:src_endofpacket -> eth1_rx_dma_descriptor_write_agent:rp_endofpacket
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wire eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest; // eth1_tx_dma_descriptor_write_agent:av_waitrequest -> eth1_tx_dma_descriptor_write_translator:uav_waitrequest
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wire [31:0] eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdata; // eth1_tx_dma_descriptor_write_agent:av_readdata -> eth1_tx_dma_descriptor_write_translator:uav_readdata
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wire eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess; // eth1_tx_dma_descriptor_write_translator:uav_debugaccess -> eth1_tx_dma_descriptor_write_agent:av_debugaccess
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wire [31:0] eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_address; // eth1_tx_dma_descriptor_write_translator:uav_address -> eth1_tx_dma_descriptor_write_agent:av_address
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wire eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_read; // eth1_tx_dma_descriptor_write_translator:uav_read -> eth1_tx_dma_descriptor_write_agent:av_read
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wire [3:0] eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable; // eth1_tx_dma_descriptor_write_translator:uav_byteenable -> eth1_tx_dma_descriptor_write_agent:av_byteenable
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wire eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid; // eth1_tx_dma_descriptor_write_agent:av_readdatavalid -> eth1_tx_dma_descriptor_write_translator:uav_readdatavalid
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wire eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_lock; // eth1_tx_dma_descriptor_write_translator:uav_lock -> eth1_tx_dma_descriptor_write_agent:av_lock
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wire eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_write; // eth1_tx_dma_descriptor_write_translator:uav_write -> eth1_tx_dma_descriptor_write_agent:av_write
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wire [31:0] eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_writedata; // eth1_tx_dma_descriptor_write_translator:uav_writedata -> eth1_tx_dma_descriptor_write_agent:av_writedata
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wire [2:0] eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount; // eth1_tx_dma_descriptor_write_translator:uav_burstcount -> eth1_tx_dma_descriptor_write_agent:av_burstcount
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wire rsp_mux_008_src_valid; // rsp_mux_008:src_valid -> eth1_tx_dma_descriptor_write_agent:rp_valid
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wire [107:0] rsp_mux_008_src_data; // rsp_mux_008:src_data -> eth1_tx_dma_descriptor_write_agent:rp_data
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wire rsp_mux_008_src_ready; // eth1_tx_dma_descriptor_write_agent:rp_ready -> rsp_mux_008:src_ready
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wire [13:0] rsp_mux_008_src_channel; // rsp_mux_008:src_channel -> eth1_tx_dma_descriptor_write_agent:rp_channel
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wire rsp_mux_008_src_startofpacket; // rsp_mux_008:src_startofpacket -> eth1_tx_dma_descriptor_write_agent:rp_startofpacket
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wire rsp_mux_008_src_endofpacket; // rsp_mux_008:src_endofpacket -> eth1_tx_dma_descriptor_write_agent:rp_endofpacket
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wire nios2_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest; // nios2_dma_descriptor_write_agent:av_waitrequest -> nios2_dma_descriptor_write_translator:uav_waitrequest
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wire [31:0] nios2_dma_descriptor_write_translator_avalon_universal_master_0_readdata; // nios2_dma_descriptor_write_agent:av_readdata -> nios2_dma_descriptor_write_translator:uav_readdata
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wire nios2_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess; // nios2_dma_descriptor_write_translator:uav_debugaccess -> nios2_dma_descriptor_write_agent:av_debugaccess
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wire [31:0] nios2_dma_descriptor_write_translator_avalon_universal_master_0_address; // nios2_dma_descriptor_write_translator:uav_address -> nios2_dma_descriptor_write_agent:av_address
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wire nios2_dma_descriptor_write_translator_avalon_universal_master_0_read; // nios2_dma_descriptor_write_translator:uav_read -> nios2_dma_descriptor_write_agent:av_read
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wire [3:0] nios2_dma_descriptor_write_translator_avalon_universal_master_0_byteenable; // nios2_dma_descriptor_write_translator:uav_byteenable -> nios2_dma_descriptor_write_agent:av_byteenable
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wire nios2_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid; // nios2_dma_descriptor_write_agent:av_readdatavalid -> nios2_dma_descriptor_write_translator:uav_readdatavalid
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wire nios2_dma_descriptor_write_translator_avalon_universal_master_0_lock; // nios2_dma_descriptor_write_translator:uav_lock -> nios2_dma_descriptor_write_agent:av_lock
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wire nios2_dma_descriptor_write_translator_avalon_universal_master_0_write; // nios2_dma_descriptor_write_translator:uav_write -> nios2_dma_descriptor_write_agent:av_write
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wire [31:0] nios2_dma_descriptor_write_translator_avalon_universal_master_0_writedata; // nios2_dma_descriptor_write_translator:uav_writedata -> nios2_dma_descriptor_write_agent:av_writedata
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wire [2:0] nios2_dma_descriptor_write_translator_avalon_universal_master_0_burstcount; // nios2_dma_descriptor_write_translator:uav_burstcount -> nios2_dma_descriptor_write_agent:av_burstcount
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wire rsp_mux_009_src_valid; // rsp_mux_009:src_valid -> nios2_dma_descriptor_write_agent:rp_valid
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wire [107:0] rsp_mux_009_src_data; // rsp_mux_009:src_data -> nios2_dma_descriptor_write_agent:rp_data
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wire rsp_mux_009_src_ready; // nios2_dma_descriptor_write_agent:rp_ready -> rsp_mux_009:src_ready
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wire [13:0] rsp_mux_009_src_channel; // rsp_mux_009:src_channel -> nios2_dma_descriptor_write_agent:rp_channel
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wire rsp_mux_009_src_startofpacket; // rsp_mux_009:src_startofpacket -> nios2_dma_descriptor_write_agent:rp_startofpacket
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wire rsp_mux_009_src_endofpacket; // rsp_mux_009:src_endofpacket -> nios2_dma_descriptor_write_agent:rp_endofpacket
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wire eth0_tx_dma_m_read_translator_avalon_universal_master_0_waitrequest; // eth0_tx_dma_m_read_agent:av_waitrequest -> eth0_tx_dma_m_read_translator:uav_waitrequest
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wire [31:0] eth0_tx_dma_m_read_translator_avalon_universal_master_0_readdata; // eth0_tx_dma_m_read_agent:av_readdata -> eth0_tx_dma_m_read_translator:uav_readdata
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wire eth0_tx_dma_m_read_translator_avalon_universal_master_0_debugaccess; // eth0_tx_dma_m_read_translator:uav_debugaccess -> eth0_tx_dma_m_read_agent:av_debugaccess
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wire [31:0] eth0_tx_dma_m_read_translator_avalon_universal_master_0_address; // eth0_tx_dma_m_read_translator:uav_address -> eth0_tx_dma_m_read_agent:av_address
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wire eth0_tx_dma_m_read_translator_avalon_universal_master_0_read; // eth0_tx_dma_m_read_translator:uav_read -> eth0_tx_dma_m_read_agent:av_read
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wire [3:0] eth0_tx_dma_m_read_translator_avalon_universal_master_0_byteenable; // eth0_tx_dma_m_read_translator:uav_byteenable -> eth0_tx_dma_m_read_agent:av_byteenable
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wire eth0_tx_dma_m_read_translator_avalon_universal_master_0_readdatavalid; // eth0_tx_dma_m_read_agent:av_readdatavalid -> eth0_tx_dma_m_read_translator:uav_readdatavalid
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wire eth0_tx_dma_m_read_translator_avalon_universal_master_0_lock; // eth0_tx_dma_m_read_translator:uav_lock -> eth0_tx_dma_m_read_agent:av_lock
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wire eth0_tx_dma_m_read_translator_avalon_universal_master_0_write; // eth0_tx_dma_m_read_translator:uav_write -> eth0_tx_dma_m_read_agent:av_write
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wire [31:0] eth0_tx_dma_m_read_translator_avalon_universal_master_0_writedata; // eth0_tx_dma_m_read_translator:uav_writedata -> eth0_tx_dma_m_read_agent:av_writedata
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wire [2:0] eth0_tx_dma_m_read_translator_avalon_universal_master_0_burstcount; // eth0_tx_dma_m_read_translator:uav_burstcount -> eth0_tx_dma_m_read_agent:av_burstcount
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wire rsp_mux_010_src_valid; // rsp_mux_010:src_valid -> eth0_tx_dma_m_read_agent:rp_valid
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wire [107:0] rsp_mux_010_src_data; // rsp_mux_010:src_data -> eth0_tx_dma_m_read_agent:rp_data
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wire rsp_mux_010_src_ready; // eth0_tx_dma_m_read_agent:rp_ready -> rsp_mux_010:src_ready
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wire [13:0] rsp_mux_010_src_channel; // rsp_mux_010:src_channel -> eth0_tx_dma_m_read_agent:rp_channel
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wire rsp_mux_010_src_startofpacket; // rsp_mux_010:src_startofpacket -> eth0_tx_dma_m_read_agent:rp_startofpacket
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wire rsp_mux_010_src_endofpacket; // rsp_mux_010:src_endofpacket -> eth0_tx_dma_m_read_agent:rp_endofpacket
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wire eth1_tx_dma_m_read_translator_avalon_universal_master_0_waitrequest; // eth1_tx_dma_m_read_agent:av_waitrequest -> eth1_tx_dma_m_read_translator:uav_waitrequest
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wire [31:0] eth1_tx_dma_m_read_translator_avalon_universal_master_0_readdata; // eth1_tx_dma_m_read_agent:av_readdata -> eth1_tx_dma_m_read_translator:uav_readdata
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wire eth1_tx_dma_m_read_translator_avalon_universal_master_0_debugaccess; // eth1_tx_dma_m_read_translator:uav_debugaccess -> eth1_tx_dma_m_read_agent:av_debugaccess
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wire [31:0] eth1_tx_dma_m_read_translator_avalon_universal_master_0_address; // eth1_tx_dma_m_read_translator:uav_address -> eth1_tx_dma_m_read_agent:av_address
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wire eth1_tx_dma_m_read_translator_avalon_universal_master_0_read; // eth1_tx_dma_m_read_translator:uav_read -> eth1_tx_dma_m_read_agent:av_read
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wire [3:0] eth1_tx_dma_m_read_translator_avalon_universal_master_0_byteenable; // eth1_tx_dma_m_read_translator:uav_byteenable -> eth1_tx_dma_m_read_agent:av_byteenable
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wire eth1_tx_dma_m_read_translator_avalon_universal_master_0_readdatavalid; // eth1_tx_dma_m_read_agent:av_readdatavalid -> eth1_tx_dma_m_read_translator:uav_readdatavalid
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wire eth1_tx_dma_m_read_translator_avalon_universal_master_0_lock; // eth1_tx_dma_m_read_translator:uav_lock -> eth1_tx_dma_m_read_agent:av_lock
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wire eth1_tx_dma_m_read_translator_avalon_universal_master_0_write; // eth1_tx_dma_m_read_translator:uav_write -> eth1_tx_dma_m_read_agent:av_write
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wire [31:0] eth1_tx_dma_m_read_translator_avalon_universal_master_0_writedata; // eth1_tx_dma_m_read_translator:uav_writedata -> eth1_tx_dma_m_read_agent:av_writedata
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wire [2:0] eth1_tx_dma_m_read_translator_avalon_universal_master_0_burstcount; // eth1_tx_dma_m_read_translator:uav_burstcount -> eth1_tx_dma_m_read_agent:av_burstcount
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wire rsp_mux_011_src_valid; // rsp_mux_011:src_valid -> eth1_tx_dma_m_read_agent:rp_valid
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wire [107:0] rsp_mux_011_src_data; // rsp_mux_011:src_data -> eth1_tx_dma_m_read_agent:rp_data
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wire rsp_mux_011_src_ready; // eth1_tx_dma_m_read_agent:rp_ready -> rsp_mux_011:src_ready
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wire [13:0] rsp_mux_011_src_channel; // rsp_mux_011:src_channel -> eth1_tx_dma_m_read_agent:rp_channel
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wire rsp_mux_011_src_startofpacket; // rsp_mux_011:src_startofpacket -> eth1_tx_dma_m_read_agent:rp_startofpacket
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wire rsp_mux_011_src_endofpacket; // rsp_mux_011:src_endofpacket -> eth1_tx_dma_m_read_agent:rp_endofpacket
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wire eth0_rx_dma_m_write_translator_avalon_universal_master_0_waitrequest; // eth0_rx_dma_m_write_agent:av_waitrequest -> eth0_rx_dma_m_write_translator:uav_waitrequest
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wire [7:0] eth0_rx_dma_m_write_translator_avalon_universal_master_0_readdata; // eth0_rx_dma_m_write_agent:av_readdata -> eth0_rx_dma_m_write_translator:uav_readdata
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wire eth0_rx_dma_m_write_translator_avalon_universal_master_0_debugaccess; // eth0_rx_dma_m_write_translator:uav_debugaccess -> eth0_rx_dma_m_write_agent:av_debugaccess
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wire [31:0] eth0_rx_dma_m_write_translator_avalon_universal_master_0_address; // eth0_rx_dma_m_write_translator:uav_address -> eth0_rx_dma_m_write_agent:av_address
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wire eth0_rx_dma_m_write_translator_avalon_universal_master_0_read; // eth0_rx_dma_m_write_translator:uav_read -> eth0_rx_dma_m_write_agent:av_read
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wire [0:0] eth0_rx_dma_m_write_translator_avalon_universal_master_0_byteenable; // eth0_rx_dma_m_write_translator:uav_byteenable -> eth0_rx_dma_m_write_agent:av_byteenable
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wire eth0_rx_dma_m_write_translator_avalon_universal_master_0_readdatavalid; // eth0_rx_dma_m_write_agent:av_readdatavalid -> eth0_rx_dma_m_write_translator:uav_readdatavalid
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wire eth0_rx_dma_m_write_translator_avalon_universal_master_0_lock; // eth0_rx_dma_m_write_translator:uav_lock -> eth0_rx_dma_m_write_agent:av_lock
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wire eth0_rx_dma_m_write_translator_avalon_universal_master_0_write; // eth0_rx_dma_m_write_translator:uav_write -> eth0_rx_dma_m_write_agent:av_write
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wire [7:0] eth0_rx_dma_m_write_translator_avalon_universal_master_0_writedata; // eth0_rx_dma_m_write_translator:uav_writedata -> eth0_rx_dma_m_write_agent:av_writedata
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wire [0:0] eth0_rx_dma_m_write_translator_avalon_universal_master_0_burstcount; // eth0_rx_dma_m_write_translator:uav_burstcount -> eth0_rx_dma_m_write_agent:av_burstcount
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wire eth1_rx_dma_m_write_translator_avalon_universal_master_0_waitrequest; // eth1_rx_dma_m_write_agent:av_waitrequest -> eth1_rx_dma_m_write_translator:uav_waitrequest
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wire [7:0] eth1_rx_dma_m_write_translator_avalon_universal_master_0_readdata; // eth1_rx_dma_m_write_agent:av_readdata -> eth1_rx_dma_m_write_translator:uav_readdata
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wire eth1_rx_dma_m_write_translator_avalon_universal_master_0_debugaccess; // eth1_rx_dma_m_write_translator:uav_debugaccess -> eth1_rx_dma_m_write_agent:av_debugaccess
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wire [31:0] eth1_rx_dma_m_write_translator_avalon_universal_master_0_address; // eth1_rx_dma_m_write_translator:uav_address -> eth1_rx_dma_m_write_agent:av_address
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wire eth1_rx_dma_m_write_translator_avalon_universal_master_0_read; // eth1_rx_dma_m_write_translator:uav_read -> eth1_rx_dma_m_write_agent:av_read
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wire [0:0] eth1_rx_dma_m_write_translator_avalon_universal_master_0_byteenable; // eth1_rx_dma_m_write_translator:uav_byteenable -> eth1_rx_dma_m_write_agent:av_byteenable
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wire eth1_rx_dma_m_write_translator_avalon_universal_master_0_readdatavalid; // eth1_rx_dma_m_write_agent:av_readdatavalid -> eth1_rx_dma_m_write_translator:uav_readdatavalid
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wire eth1_rx_dma_m_write_translator_avalon_universal_master_0_lock; // eth1_rx_dma_m_write_translator:uav_lock -> eth1_rx_dma_m_write_agent:av_lock
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wire eth1_rx_dma_m_write_translator_avalon_universal_master_0_write; // eth1_rx_dma_m_write_translator:uav_write -> eth1_rx_dma_m_write_agent:av_write
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wire [7:0] eth1_rx_dma_m_write_translator_avalon_universal_master_0_writedata; // eth1_rx_dma_m_write_translator:uav_writedata -> eth1_rx_dma_m_write_agent:av_writedata
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wire [0:0] eth1_rx_dma_m_write_translator_avalon_universal_master_0_burstcount; // eth1_rx_dma_m_write_translator:uav_burstcount -> eth1_rx_dma_m_write_agent:av_burstcount
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wire [31:0] nios2_onchip_mem_s2_agent_m0_readdata; // nios2_onchip_mem_s2_translator:uav_readdata -> nios2_onchip_mem_s2_agent:m0_readdata
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wire nios2_onchip_mem_s2_agent_m0_waitrequest; // nios2_onchip_mem_s2_translator:uav_waitrequest -> nios2_onchip_mem_s2_agent:m0_waitrequest
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wire nios2_onchip_mem_s2_agent_m0_debugaccess; // nios2_onchip_mem_s2_agent:m0_debugaccess -> nios2_onchip_mem_s2_translator:uav_debugaccess
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wire [31:0] nios2_onchip_mem_s2_agent_m0_address; // nios2_onchip_mem_s2_agent:m0_address -> nios2_onchip_mem_s2_translator:uav_address
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wire [3:0] nios2_onchip_mem_s2_agent_m0_byteenable; // nios2_onchip_mem_s2_agent:m0_byteenable -> nios2_onchip_mem_s2_translator:uav_byteenable
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wire nios2_onchip_mem_s2_agent_m0_read; // nios2_onchip_mem_s2_agent:m0_read -> nios2_onchip_mem_s2_translator:uav_read
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wire nios2_onchip_mem_s2_agent_m0_readdatavalid; // nios2_onchip_mem_s2_translator:uav_readdatavalid -> nios2_onchip_mem_s2_agent:m0_readdatavalid
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wire nios2_onchip_mem_s2_agent_m0_lock; // nios2_onchip_mem_s2_agent:m0_lock -> nios2_onchip_mem_s2_translator:uav_lock
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wire [31:0] nios2_onchip_mem_s2_agent_m0_writedata; // nios2_onchip_mem_s2_agent:m0_writedata -> nios2_onchip_mem_s2_translator:uav_writedata
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wire nios2_onchip_mem_s2_agent_m0_write; // nios2_onchip_mem_s2_agent:m0_write -> nios2_onchip_mem_s2_translator:uav_write
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wire [2:0] nios2_onchip_mem_s2_agent_m0_burstcount; // nios2_onchip_mem_s2_agent:m0_burstcount -> nios2_onchip_mem_s2_translator:uav_burstcount
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wire nios2_onchip_mem_s2_agent_rf_source_valid; // nios2_onchip_mem_s2_agent:rf_source_valid -> nios2_onchip_mem_s2_agent_rsp_fifo:in_valid
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wire [108:0] nios2_onchip_mem_s2_agent_rf_source_data; // nios2_onchip_mem_s2_agent:rf_source_data -> nios2_onchip_mem_s2_agent_rsp_fifo:in_data
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wire nios2_onchip_mem_s2_agent_rf_source_ready; // nios2_onchip_mem_s2_agent_rsp_fifo:in_ready -> nios2_onchip_mem_s2_agent:rf_source_ready
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wire nios2_onchip_mem_s2_agent_rf_source_startofpacket; // nios2_onchip_mem_s2_agent:rf_source_startofpacket -> nios2_onchip_mem_s2_agent_rsp_fifo:in_startofpacket
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wire nios2_onchip_mem_s2_agent_rf_source_endofpacket; // nios2_onchip_mem_s2_agent:rf_source_endofpacket -> nios2_onchip_mem_s2_agent_rsp_fifo:in_endofpacket
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wire nios2_onchip_mem_s2_agent_rsp_fifo_out_valid; // nios2_onchip_mem_s2_agent_rsp_fifo:out_valid -> nios2_onchip_mem_s2_agent:rf_sink_valid
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wire [108:0] nios2_onchip_mem_s2_agent_rsp_fifo_out_data; // nios2_onchip_mem_s2_agent_rsp_fifo:out_data -> nios2_onchip_mem_s2_agent:rf_sink_data
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wire nios2_onchip_mem_s2_agent_rsp_fifo_out_ready; // nios2_onchip_mem_s2_agent:rf_sink_ready -> nios2_onchip_mem_s2_agent_rsp_fifo:out_ready
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wire nios2_onchip_mem_s2_agent_rsp_fifo_out_startofpacket; // nios2_onchip_mem_s2_agent_rsp_fifo:out_startofpacket -> nios2_onchip_mem_s2_agent:rf_sink_startofpacket
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wire nios2_onchip_mem_s2_agent_rsp_fifo_out_endofpacket; // nios2_onchip_mem_s2_agent_rsp_fifo:out_endofpacket -> nios2_onchip_mem_s2_agent:rf_sink_endofpacket
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wire cmd_mux_src_valid; // cmd_mux:src_valid -> nios2_onchip_mem_s2_agent:cp_valid
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wire [107:0] cmd_mux_src_data; // cmd_mux:src_data -> nios2_onchip_mem_s2_agent:cp_data
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wire cmd_mux_src_ready; // nios2_onchip_mem_s2_agent:cp_ready -> cmd_mux:src_ready
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wire [13:0] cmd_mux_src_channel; // cmd_mux:src_channel -> nios2_onchip_mem_s2_agent:cp_channel
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wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> nios2_onchip_mem_s2_agent:cp_startofpacket
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wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> nios2_onchip_mem_s2_agent:cp_endofpacket
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wire eth0_rx_dma_descriptor_read_agent_cp_valid; // eth0_rx_dma_descriptor_read_agent:cp_valid -> router:sink_valid
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wire [107:0] eth0_rx_dma_descriptor_read_agent_cp_data; // eth0_rx_dma_descriptor_read_agent:cp_data -> router:sink_data
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wire eth0_rx_dma_descriptor_read_agent_cp_ready; // router:sink_ready -> eth0_rx_dma_descriptor_read_agent:cp_ready
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wire eth0_rx_dma_descriptor_read_agent_cp_startofpacket; // eth0_rx_dma_descriptor_read_agent:cp_startofpacket -> router:sink_startofpacket
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wire eth0_rx_dma_descriptor_read_agent_cp_endofpacket; // eth0_rx_dma_descriptor_read_agent:cp_endofpacket -> router:sink_endofpacket
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wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
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wire [107:0] router_src_data; // router:src_data -> cmd_demux:sink_data
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wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
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wire [13:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
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wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
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wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
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wire eth0_tx_dma_descriptor_read_agent_cp_valid; // eth0_tx_dma_descriptor_read_agent:cp_valid -> router_001:sink_valid
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wire [107:0] eth0_tx_dma_descriptor_read_agent_cp_data; // eth0_tx_dma_descriptor_read_agent:cp_data -> router_001:sink_data
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wire eth0_tx_dma_descriptor_read_agent_cp_ready; // router_001:sink_ready -> eth0_tx_dma_descriptor_read_agent:cp_ready
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wire eth0_tx_dma_descriptor_read_agent_cp_startofpacket; // eth0_tx_dma_descriptor_read_agent:cp_startofpacket -> router_001:sink_startofpacket
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wire eth0_tx_dma_descriptor_read_agent_cp_endofpacket; // eth0_tx_dma_descriptor_read_agent:cp_endofpacket -> router_001:sink_endofpacket
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wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
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wire [107:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
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wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
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wire [13:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
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wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
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wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
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wire eth1_rx_dma_descriptor_read_agent_cp_valid; // eth1_rx_dma_descriptor_read_agent:cp_valid -> router_002:sink_valid
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wire [107:0] eth1_rx_dma_descriptor_read_agent_cp_data; // eth1_rx_dma_descriptor_read_agent:cp_data -> router_002:sink_data
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wire eth1_rx_dma_descriptor_read_agent_cp_ready; // router_002:sink_ready -> eth1_rx_dma_descriptor_read_agent:cp_ready
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wire eth1_rx_dma_descriptor_read_agent_cp_startofpacket; // eth1_rx_dma_descriptor_read_agent:cp_startofpacket -> router_002:sink_startofpacket
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wire eth1_rx_dma_descriptor_read_agent_cp_endofpacket; // eth1_rx_dma_descriptor_read_agent:cp_endofpacket -> router_002:sink_endofpacket
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wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid
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wire [107:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data
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wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready
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wire [13:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel
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wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
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wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
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wire eth1_tx_dma_descriptor_read_agent_cp_valid; // eth1_tx_dma_descriptor_read_agent:cp_valid -> router_003:sink_valid
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wire [107:0] eth1_tx_dma_descriptor_read_agent_cp_data; // eth1_tx_dma_descriptor_read_agent:cp_data -> router_003:sink_data
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wire eth1_tx_dma_descriptor_read_agent_cp_ready; // router_003:sink_ready -> eth1_tx_dma_descriptor_read_agent:cp_ready
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wire eth1_tx_dma_descriptor_read_agent_cp_startofpacket; // eth1_tx_dma_descriptor_read_agent:cp_startofpacket -> router_003:sink_startofpacket
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wire eth1_tx_dma_descriptor_read_agent_cp_endofpacket; // eth1_tx_dma_descriptor_read_agent:cp_endofpacket -> router_003:sink_endofpacket
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wire router_003_src_valid; // router_003:src_valid -> cmd_demux_003:sink_valid
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wire [107:0] router_003_src_data; // router_003:src_data -> cmd_demux_003:sink_data
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wire router_003_src_ready; // cmd_demux_003:sink_ready -> router_003:src_ready
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wire [13:0] router_003_src_channel; // router_003:src_channel -> cmd_demux_003:sink_channel
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wire router_003_src_startofpacket; // router_003:src_startofpacket -> cmd_demux_003:sink_startofpacket
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wire router_003_src_endofpacket; // router_003:src_endofpacket -> cmd_demux_003:sink_endofpacket
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wire nios2_dma_descriptor_read_agent_cp_valid; // nios2_dma_descriptor_read_agent:cp_valid -> router_004:sink_valid
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wire [107:0] nios2_dma_descriptor_read_agent_cp_data; // nios2_dma_descriptor_read_agent:cp_data -> router_004:sink_data
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wire nios2_dma_descriptor_read_agent_cp_ready; // router_004:sink_ready -> nios2_dma_descriptor_read_agent:cp_ready
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wire nios2_dma_descriptor_read_agent_cp_startofpacket; // nios2_dma_descriptor_read_agent:cp_startofpacket -> router_004:sink_startofpacket
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wire nios2_dma_descriptor_read_agent_cp_endofpacket; // nios2_dma_descriptor_read_agent:cp_endofpacket -> router_004:sink_endofpacket
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wire router_004_src_valid; // router_004:src_valid -> cmd_demux_004:sink_valid
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wire [107:0] router_004_src_data; // router_004:src_data -> cmd_demux_004:sink_data
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wire router_004_src_ready; // cmd_demux_004:sink_ready -> router_004:src_ready
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wire [13:0] router_004_src_channel; // router_004:src_channel -> cmd_demux_004:sink_channel
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wire router_004_src_startofpacket; // router_004:src_startofpacket -> cmd_demux_004:sink_startofpacket
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wire router_004_src_endofpacket; // router_004:src_endofpacket -> cmd_demux_004:sink_endofpacket
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wire eth0_rx_dma_descriptor_write_agent_cp_valid; // eth0_rx_dma_descriptor_write_agent:cp_valid -> router_005:sink_valid
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wire [107:0] eth0_rx_dma_descriptor_write_agent_cp_data; // eth0_rx_dma_descriptor_write_agent:cp_data -> router_005:sink_data
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wire eth0_rx_dma_descriptor_write_agent_cp_ready; // router_005:sink_ready -> eth0_rx_dma_descriptor_write_agent:cp_ready
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wire eth0_rx_dma_descriptor_write_agent_cp_startofpacket; // eth0_rx_dma_descriptor_write_agent:cp_startofpacket -> router_005:sink_startofpacket
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wire eth0_rx_dma_descriptor_write_agent_cp_endofpacket; // eth0_rx_dma_descriptor_write_agent:cp_endofpacket -> router_005:sink_endofpacket
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wire router_005_src_valid; // router_005:src_valid -> cmd_demux_005:sink_valid
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wire [107:0] router_005_src_data; // router_005:src_data -> cmd_demux_005:sink_data
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wire router_005_src_ready; // cmd_demux_005:sink_ready -> router_005:src_ready
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wire [13:0] router_005_src_channel; // router_005:src_channel -> cmd_demux_005:sink_channel
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wire router_005_src_startofpacket; // router_005:src_startofpacket -> cmd_demux_005:sink_startofpacket
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wire router_005_src_endofpacket; // router_005:src_endofpacket -> cmd_demux_005:sink_endofpacket
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wire eth0_tx_dma_descriptor_write_agent_cp_valid; // eth0_tx_dma_descriptor_write_agent:cp_valid -> router_006:sink_valid
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wire [107:0] eth0_tx_dma_descriptor_write_agent_cp_data; // eth0_tx_dma_descriptor_write_agent:cp_data -> router_006:sink_data
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wire eth0_tx_dma_descriptor_write_agent_cp_ready; // router_006:sink_ready -> eth0_tx_dma_descriptor_write_agent:cp_ready
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wire eth0_tx_dma_descriptor_write_agent_cp_startofpacket; // eth0_tx_dma_descriptor_write_agent:cp_startofpacket -> router_006:sink_startofpacket
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wire eth0_tx_dma_descriptor_write_agent_cp_endofpacket; // eth0_tx_dma_descriptor_write_agent:cp_endofpacket -> router_006:sink_endofpacket
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wire router_006_src_valid; // router_006:src_valid -> cmd_demux_006:sink_valid
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wire [107:0] router_006_src_data; // router_006:src_data -> cmd_demux_006:sink_data
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wire router_006_src_ready; // cmd_demux_006:sink_ready -> router_006:src_ready
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wire [13:0] router_006_src_channel; // router_006:src_channel -> cmd_demux_006:sink_channel
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wire router_006_src_startofpacket; // router_006:src_startofpacket -> cmd_demux_006:sink_startofpacket
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wire router_006_src_endofpacket; // router_006:src_endofpacket -> cmd_demux_006:sink_endofpacket
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wire eth1_rx_dma_descriptor_write_agent_cp_valid; // eth1_rx_dma_descriptor_write_agent:cp_valid -> router_007:sink_valid
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wire [107:0] eth1_rx_dma_descriptor_write_agent_cp_data; // eth1_rx_dma_descriptor_write_agent:cp_data -> router_007:sink_data
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wire eth1_rx_dma_descriptor_write_agent_cp_ready; // router_007:sink_ready -> eth1_rx_dma_descriptor_write_agent:cp_ready
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wire eth1_rx_dma_descriptor_write_agent_cp_startofpacket; // eth1_rx_dma_descriptor_write_agent:cp_startofpacket -> router_007:sink_startofpacket
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wire eth1_rx_dma_descriptor_write_agent_cp_endofpacket; // eth1_rx_dma_descriptor_write_agent:cp_endofpacket -> router_007:sink_endofpacket
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wire router_007_src_valid; // router_007:src_valid -> cmd_demux_007:sink_valid
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wire [107:0] router_007_src_data; // router_007:src_data -> cmd_demux_007:sink_data
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wire router_007_src_ready; // cmd_demux_007:sink_ready -> router_007:src_ready
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wire [13:0] router_007_src_channel; // router_007:src_channel -> cmd_demux_007:sink_channel
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wire router_007_src_startofpacket; // router_007:src_startofpacket -> cmd_demux_007:sink_startofpacket
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wire router_007_src_endofpacket; // router_007:src_endofpacket -> cmd_demux_007:sink_endofpacket
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wire eth1_tx_dma_descriptor_write_agent_cp_valid; // eth1_tx_dma_descriptor_write_agent:cp_valid -> router_008:sink_valid
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wire [107:0] eth1_tx_dma_descriptor_write_agent_cp_data; // eth1_tx_dma_descriptor_write_agent:cp_data -> router_008:sink_data
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wire eth1_tx_dma_descriptor_write_agent_cp_ready; // router_008:sink_ready -> eth1_tx_dma_descriptor_write_agent:cp_ready
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wire eth1_tx_dma_descriptor_write_agent_cp_startofpacket; // eth1_tx_dma_descriptor_write_agent:cp_startofpacket -> router_008:sink_startofpacket
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wire eth1_tx_dma_descriptor_write_agent_cp_endofpacket; // eth1_tx_dma_descriptor_write_agent:cp_endofpacket -> router_008:sink_endofpacket
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wire router_008_src_valid; // router_008:src_valid -> cmd_demux_008:sink_valid
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wire [107:0] router_008_src_data; // router_008:src_data -> cmd_demux_008:sink_data
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wire router_008_src_ready; // cmd_demux_008:sink_ready -> router_008:src_ready
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wire [13:0] router_008_src_channel; // router_008:src_channel -> cmd_demux_008:sink_channel
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wire router_008_src_startofpacket; // router_008:src_startofpacket -> cmd_demux_008:sink_startofpacket
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wire router_008_src_endofpacket; // router_008:src_endofpacket -> cmd_demux_008:sink_endofpacket
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wire nios2_dma_descriptor_write_agent_cp_valid; // nios2_dma_descriptor_write_agent:cp_valid -> router_009:sink_valid
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wire [107:0] nios2_dma_descriptor_write_agent_cp_data; // nios2_dma_descriptor_write_agent:cp_data -> router_009:sink_data
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wire nios2_dma_descriptor_write_agent_cp_ready; // router_009:sink_ready -> nios2_dma_descriptor_write_agent:cp_ready
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wire nios2_dma_descriptor_write_agent_cp_startofpacket; // nios2_dma_descriptor_write_agent:cp_startofpacket -> router_009:sink_startofpacket
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wire nios2_dma_descriptor_write_agent_cp_endofpacket; // nios2_dma_descriptor_write_agent:cp_endofpacket -> router_009:sink_endofpacket
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wire router_009_src_valid; // router_009:src_valid -> cmd_demux_009:sink_valid
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wire [107:0] router_009_src_data; // router_009:src_data -> cmd_demux_009:sink_data
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wire router_009_src_ready; // cmd_demux_009:sink_ready -> router_009:src_ready
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wire [13:0] router_009_src_channel; // router_009:src_channel -> cmd_demux_009:sink_channel
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wire router_009_src_startofpacket; // router_009:src_startofpacket -> cmd_demux_009:sink_startofpacket
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wire router_009_src_endofpacket; // router_009:src_endofpacket -> cmd_demux_009:sink_endofpacket
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wire eth0_tx_dma_m_read_agent_cp_valid; // eth0_tx_dma_m_read_agent:cp_valid -> router_010:sink_valid
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wire [107:0] eth0_tx_dma_m_read_agent_cp_data; // eth0_tx_dma_m_read_agent:cp_data -> router_010:sink_data
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wire eth0_tx_dma_m_read_agent_cp_ready; // router_010:sink_ready -> eth0_tx_dma_m_read_agent:cp_ready
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wire eth0_tx_dma_m_read_agent_cp_startofpacket; // eth0_tx_dma_m_read_agent:cp_startofpacket -> router_010:sink_startofpacket
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wire eth0_tx_dma_m_read_agent_cp_endofpacket; // eth0_tx_dma_m_read_agent:cp_endofpacket -> router_010:sink_endofpacket
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wire router_010_src_valid; // router_010:src_valid -> cmd_demux_010:sink_valid
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wire [107:0] router_010_src_data; // router_010:src_data -> cmd_demux_010:sink_data
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wire router_010_src_ready; // cmd_demux_010:sink_ready -> router_010:src_ready
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wire [13:0] router_010_src_channel; // router_010:src_channel -> cmd_demux_010:sink_channel
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wire router_010_src_startofpacket; // router_010:src_startofpacket -> cmd_demux_010:sink_startofpacket
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wire router_010_src_endofpacket; // router_010:src_endofpacket -> cmd_demux_010:sink_endofpacket
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wire eth1_tx_dma_m_read_agent_cp_valid; // eth1_tx_dma_m_read_agent:cp_valid -> router_011:sink_valid
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wire [107:0] eth1_tx_dma_m_read_agent_cp_data; // eth1_tx_dma_m_read_agent:cp_data -> router_011:sink_data
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wire eth1_tx_dma_m_read_agent_cp_ready; // router_011:sink_ready -> eth1_tx_dma_m_read_agent:cp_ready
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wire eth1_tx_dma_m_read_agent_cp_startofpacket; // eth1_tx_dma_m_read_agent:cp_startofpacket -> router_011:sink_startofpacket
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wire eth1_tx_dma_m_read_agent_cp_endofpacket; // eth1_tx_dma_m_read_agent:cp_endofpacket -> router_011:sink_endofpacket
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wire router_011_src_valid; // router_011:src_valid -> cmd_demux_011:sink_valid
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wire [107:0] router_011_src_data; // router_011:src_data -> cmd_demux_011:sink_data
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wire router_011_src_ready; // cmd_demux_011:sink_ready -> router_011:src_ready
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wire [13:0] router_011_src_channel; // router_011:src_channel -> cmd_demux_011:sink_channel
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wire router_011_src_startofpacket; // router_011:src_startofpacket -> cmd_demux_011:sink_startofpacket
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wire router_011_src_endofpacket; // router_011:src_endofpacket -> cmd_demux_011:sink_endofpacket
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wire eth0_rx_dma_m_write_agent_cp_valid; // eth0_rx_dma_m_write_agent:cp_valid -> router_012:sink_valid
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wire [80:0] eth0_rx_dma_m_write_agent_cp_data; // eth0_rx_dma_m_write_agent:cp_data -> router_012:sink_data
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wire eth0_rx_dma_m_write_agent_cp_ready; // router_012:sink_ready -> eth0_rx_dma_m_write_agent:cp_ready
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wire eth0_rx_dma_m_write_agent_cp_startofpacket; // eth0_rx_dma_m_write_agent:cp_startofpacket -> router_012:sink_startofpacket
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wire eth0_rx_dma_m_write_agent_cp_endofpacket; // eth0_rx_dma_m_write_agent:cp_endofpacket -> router_012:sink_endofpacket
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wire eth1_rx_dma_m_write_agent_cp_valid; // eth1_rx_dma_m_write_agent:cp_valid -> router_013:sink_valid
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wire [80:0] eth1_rx_dma_m_write_agent_cp_data; // eth1_rx_dma_m_write_agent:cp_data -> router_013:sink_data
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wire eth1_rx_dma_m_write_agent_cp_ready; // router_013:sink_ready -> eth1_rx_dma_m_write_agent:cp_ready
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wire eth1_rx_dma_m_write_agent_cp_startofpacket; // eth1_rx_dma_m_write_agent:cp_startofpacket -> router_013:sink_startofpacket
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wire eth1_rx_dma_m_write_agent_cp_endofpacket; // eth1_rx_dma_m_write_agent:cp_endofpacket -> router_013:sink_endofpacket
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wire nios2_onchip_mem_s2_agent_rp_valid; // nios2_onchip_mem_s2_agent:rp_valid -> router_014:sink_valid
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wire [107:0] nios2_onchip_mem_s2_agent_rp_data; // nios2_onchip_mem_s2_agent:rp_data -> router_014:sink_data
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wire nios2_onchip_mem_s2_agent_rp_ready; // router_014:sink_ready -> nios2_onchip_mem_s2_agent:rp_ready
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wire nios2_onchip_mem_s2_agent_rp_startofpacket; // nios2_onchip_mem_s2_agent:rp_startofpacket -> router_014:sink_startofpacket
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wire nios2_onchip_mem_s2_agent_rp_endofpacket; // nios2_onchip_mem_s2_agent:rp_endofpacket -> router_014:sink_endofpacket
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wire router_014_src_valid; // router_014:src_valid -> rsp_demux:sink_valid
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wire [107:0] router_014_src_data; // router_014:src_data -> rsp_demux:sink_data
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wire router_014_src_ready; // rsp_demux:sink_ready -> router_014:src_ready
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wire [13:0] router_014_src_channel; // router_014:src_channel -> rsp_demux:sink_channel
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wire router_014_src_startofpacket; // router_014:src_startofpacket -> rsp_demux:sink_startofpacket
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wire router_014_src_endofpacket; // router_014:src_endofpacket -> rsp_demux:sink_endofpacket
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wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
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wire [107:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
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wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
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wire [13:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
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wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
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wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
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wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
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wire [107:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
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wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
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wire [13:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
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wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
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wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
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wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
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wire [107:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux:sink2_data
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wire cmd_demux_002_src0_ready; // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
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wire [13:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
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wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
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wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
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wire cmd_demux_003_src0_valid; // cmd_demux_003:src0_valid -> cmd_mux:sink3_valid
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wire [107:0] cmd_demux_003_src0_data; // cmd_demux_003:src0_data -> cmd_mux:sink3_data
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wire cmd_demux_003_src0_ready; // cmd_mux:sink3_ready -> cmd_demux_003:src0_ready
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wire [13:0] cmd_demux_003_src0_channel; // cmd_demux_003:src0_channel -> cmd_mux:sink3_channel
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wire cmd_demux_003_src0_startofpacket; // cmd_demux_003:src0_startofpacket -> cmd_mux:sink3_startofpacket
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wire cmd_demux_003_src0_endofpacket; // cmd_demux_003:src0_endofpacket -> cmd_mux:sink3_endofpacket
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wire cmd_demux_004_src0_valid; // cmd_demux_004:src0_valid -> cmd_mux:sink4_valid
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wire [107:0] cmd_demux_004_src0_data; // cmd_demux_004:src0_data -> cmd_mux:sink4_data
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wire cmd_demux_004_src0_ready; // cmd_mux:sink4_ready -> cmd_demux_004:src0_ready
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wire [13:0] cmd_demux_004_src0_channel; // cmd_demux_004:src0_channel -> cmd_mux:sink4_channel
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wire cmd_demux_004_src0_startofpacket; // cmd_demux_004:src0_startofpacket -> cmd_mux:sink4_startofpacket
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wire cmd_demux_004_src0_endofpacket; // cmd_demux_004:src0_endofpacket -> cmd_mux:sink4_endofpacket
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wire cmd_demux_005_src0_valid; // cmd_demux_005:src0_valid -> cmd_mux:sink5_valid
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wire [107:0] cmd_demux_005_src0_data; // cmd_demux_005:src0_data -> cmd_mux:sink5_data
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wire cmd_demux_005_src0_ready; // cmd_mux:sink5_ready -> cmd_demux_005:src0_ready
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wire [13:0] cmd_demux_005_src0_channel; // cmd_demux_005:src0_channel -> cmd_mux:sink5_channel
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wire cmd_demux_005_src0_startofpacket; // cmd_demux_005:src0_startofpacket -> cmd_mux:sink5_startofpacket
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wire cmd_demux_005_src0_endofpacket; // cmd_demux_005:src0_endofpacket -> cmd_mux:sink5_endofpacket
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wire cmd_demux_006_src0_valid; // cmd_demux_006:src0_valid -> cmd_mux:sink6_valid
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wire [107:0] cmd_demux_006_src0_data; // cmd_demux_006:src0_data -> cmd_mux:sink6_data
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wire cmd_demux_006_src0_ready; // cmd_mux:sink6_ready -> cmd_demux_006:src0_ready
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wire [13:0] cmd_demux_006_src0_channel; // cmd_demux_006:src0_channel -> cmd_mux:sink6_channel
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wire cmd_demux_006_src0_startofpacket; // cmd_demux_006:src0_startofpacket -> cmd_mux:sink6_startofpacket
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wire cmd_demux_006_src0_endofpacket; // cmd_demux_006:src0_endofpacket -> cmd_mux:sink6_endofpacket
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wire cmd_demux_007_src0_valid; // cmd_demux_007:src0_valid -> cmd_mux:sink7_valid
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wire [107:0] cmd_demux_007_src0_data; // cmd_demux_007:src0_data -> cmd_mux:sink7_data
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wire cmd_demux_007_src0_ready; // cmd_mux:sink7_ready -> cmd_demux_007:src0_ready
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wire [13:0] cmd_demux_007_src0_channel; // cmd_demux_007:src0_channel -> cmd_mux:sink7_channel
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wire cmd_demux_007_src0_startofpacket; // cmd_demux_007:src0_startofpacket -> cmd_mux:sink7_startofpacket
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wire cmd_demux_007_src0_endofpacket; // cmd_demux_007:src0_endofpacket -> cmd_mux:sink7_endofpacket
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wire cmd_demux_008_src0_valid; // cmd_demux_008:src0_valid -> cmd_mux:sink8_valid
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wire [107:0] cmd_demux_008_src0_data; // cmd_demux_008:src0_data -> cmd_mux:sink8_data
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wire cmd_demux_008_src0_ready; // cmd_mux:sink8_ready -> cmd_demux_008:src0_ready
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wire [13:0] cmd_demux_008_src0_channel; // cmd_demux_008:src0_channel -> cmd_mux:sink8_channel
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wire cmd_demux_008_src0_startofpacket; // cmd_demux_008:src0_startofpacket -> cmd_mux:sink8_startofpacket
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wire cmd_demux_008_src0_endofpacket; // cmd_demux_008:src0_endofpacket -> cmd_mux:sink8_endofpacket
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wire cmd_demux_009_src0_valid; // cmd_demux_009:src0_valid -> cmd_mux:sink9_valid
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wire [107:0] cmd_demux_009_src0_data; // cmd_demux_009:src0_data -> cmd_mux:sink9_data
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wire cmd_demux_009_src0_ready; // cmd_mux:sink9_ready -> cmd_demux_009:src0_ready
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wire [13:0] cmd_demux_009_src0_channel; // cmd_demux_009:src0_channel -> cmd_mux:sink9_channel
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wire cmd_demux_009_src0_startofpacket; // cmd_demux_009:src0_startofpacket -> cmd_mux:sink9_startofpacket
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wire cmd_demux_009_src0_endofpacket; // cmd_demux_009:src0_endofpacket -> cmd_mux:sink9_endofpacket
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wire cmd_demux_010_src0_valid; // cmd_demux_010:src0_valid -> cmd_mux:sink10_valid
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wire [107:0] cmd_demux_010_src0_data; // cmd_demux_010:src0_data -> cmd_mux:sink10_data
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wire cmd_demux_010_src0_ready; // cmd_mux:sink10_ready -> cmd_demux_010:src0_ready
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wire [13:0] cmd_demux_010_src0_channel; // cmd_demux_010:src0_channel -> cmd_mux:sink10_channel
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wire cmd_demux_010_src0_startofpacket; // cmd_demux_010:src0_startofpacket -> cmd_mux:sink10_startofpacket
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wire cmd_demux_010_src0_endofpacket; // cmd_demux_010:src0_endofpacket -> cmd_mux:sink10_endofpacket
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wire cmd_demux_011_src0_valid; // cmd_demux_011:src0_valid -> cmd_mux:sink11_valid
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wire [107:0] cmd_demux_011_src0_data; // cmd_demux_011:src0_data -> cmd_mux:sink11_data
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wire cmd_demux_011_src0_ready; // cmd_mux:sink11_ready -> cmd_demux_011:src0_ready
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wire [13:0] cmd_demux_011_src0_channel; // cmd_demux_011:src0_channel -> cmd_mux:sink11_channel
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wire cmd_demux_011_src0_startofpacket; // cmd_demux_011:src0_startofpacket -> cmd_mux:sink11_startofpacket
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wire cmd_demux_011_src0_endofpacket; // cmd_demux_011:src0_endofpacket -> cmd_mux:sink11_endofpacket
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wire cmd_demux_012_src0_valid; // cmd_demux_012:src0_valid -> cmd_mux:sink12_valid
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wire [107:0] cmd_demux_012_src0_data; // cmd_demux_012:src0_data -> cmd_mux:sink12_data
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wire cmd_demux_012_src0_ready; // cmd_mux:sink12_ready -> cmd_demux_012:src0_ready
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wire [13:0] cmd_demux_012_src0_channel; // cmd_demux_012:src0_channel -> cmd_mux:sink12_channel
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wire cmd_demux_012_src0_startofpacket; // cmd_demux_012:src0_startofpacket -> cmd_mux:sink12_startofpacket
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wire cmd_demux_012_src0_endofpacket; // cmd_demux_012:src0_endofpacket -> cmd_mux:sink12_endofpacket
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wire cmd_demux_013_src0_valid; // cmd_demux_013:src0_valid -> cmd_mux:sink13_valid
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wire [107:0] cmd_demux_013_src0_data; // cmd_demux_013:src0_data -> cmd_mux:sink13_data
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wire cmd_demux_013_src0_ready; // cmd_mux:sink13_ready -> cmd_demux_013:src0_ready
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wire [13:0] cmd_demux_013_src0_channel; // cmd_demux_013:src0_channel -> cmd_mux:sink13_channel
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wire cmd_demux_013_src0_startofpacket; // cmd_demux_013:src0_startofpacket -> cmd_mux:sink13_startofpacket
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wire cmd_demux_013_src0_endofpacket; // cmd_demux_013:src0_endofpacket -> cmd_mux:sink13_endofpacket
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wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
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wire [107:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
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wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
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wire [13:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
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wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
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wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
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wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
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wire [107:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
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wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
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wire [13:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
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wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
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wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
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wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
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wire [107:0] rsp_demux_src2_data; // rsp_demux:src2_data -> rsp_mux_002:sink0_data
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wire rsp_demux_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
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wire [13:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
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wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
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wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
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wire rsp_demux_src3_valid; // rsp_demux:src3_valid -> rsp_mux_003:sink0_valid
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wire [107:0] rsp_demux_src3_data; // rsp_demux:src3_data -> rsp_mux_003:sink0_data
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wire rsp_demux_src3_ready; // rsp_mux_003:sink0_ready -> rsp_demux:src3_ready
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wire [13:0] rsp_demux_src3_channel; // rsp_demux:src3_channel -> rsp_mux_003:sink0_channel
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wire rsp_demux_src3_startofpacket; // rsp_demux:src3_startofpacket -> rsp_mux_003:sink0_startofpacket
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wire rsp_demux_src3_endofpacket; // rsp_demux:src3_endofpacket -> rsp_mux_003:sink0_endofpacket
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wire rsp_demux_src4_valid; // rsp_demux:src4_valid -> rsp_mux_004:sink0_valid
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wire [107:0] rsp_demux_src4_data; // rsp_demux:src4_data -> rsp_mux_004:sink0_data
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wire rsp_demux_src4_ready; // rsp_mux_004:sink0_ready -> rsp_demux:src4_ready
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wire [13:0] rsp_demux_src4_channel; // rsp_demux:src4_channel -> rsp_mux_004:sink0_channel
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wire rsp_demux_src4_startofpacket; // rsp_demux:src4_startofpacket -> rsp_mux_004:sink0_startofpacket
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wire rsp_demux_src4_endofpacket; // rsp_demux:src4_endofpacket -> rsp_mux_004:sink0_endofpacket
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wire rsp_demux_src5_valid; // rsp_demux:src5_valid -> rsp_mux_005:sink0_valid
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wire [107:0] rsp_demux_src5_data; // rsp_demux:src5_data -> rsp_mux_005:sink0_data
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wire rsp_demux_src5_ready; // rsp_mux_005:sink0_ready -> rsp_demux:src5_ready
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wire [13:0] rsp_demux_src5_channel; // rsp_demux:src5_channel -> rsp_mux_005:sink0_channel
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wire rsp_demux_src5_startofpacket; // rsp_demux:src5_startofpacket -> rsp_mux_005:sink0_startofpacket
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wire rsp_demux_src5_endofpacket; // rsp_demux:src5_endofpacket -> rsp_mux_005:sink0_endofpacket
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wire rsp_demux_src6_valid; // rsp_demux:src6_valid -> rsp_mux_006:sink0_valid
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wire [107:0] rsp_demux_src6_data; // rsp_demux:src6_data -> rsp_mux_006:sink0_data
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wire rsp_demux_src6_ready; // rsp_mux_006:sink0_ready -> rsp_demux:src6_ready
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wire [13:0] rsp_demux_src6_channel; // rsp_demux:src6_channel -> rsp_mux_006:sink0_channel
|
|
wire rsp_demux_src6_startofpacket; // rsp_demux:src6_startofpacket -> rsp_mux_006:sink0_startofpacket
|
|
wire rsp_demux_src6_endofpacket; // rsp_demux:src6_endofpacket -> rsp_mux_006:sink0_endofpacket
|
|
wire rsp_demux_src7_valid; // rsp_demux:src7_valid -> rsp_mux_007:sink0_valid
|
|
wire [107:0] rsp_demux_src7_data; // rsp_demux:src7_data -> rsp_mux_007:sink0_data
|
|
wire rsp_demux_src7_ready; // rsp_mux_007:sink0_ready -> rsp_demux:src7_ready
|
|
wire [13:0] rsp_demux_src7_channel; // rsp_demux:src7_channel -> rsp_mux_007:sink0_channel
|
|
wire rsp_demux_src7_startofpacket; // rsp_demux:src7_startofpacket -> rsp_mux_007:sink0_startofpacket
|
|
wire rsp_demux_src7_endofpacket; // rsp_demux:src7_endofpacket -> rsp_mux_007:sink0_endofpacket
|
|
wire rsp_demux_src8_valid; // rsp_demux:src8_valid -> rsp_mux_008:sink0_valid
|
|
wire [107:0] rsp_demux_src8_data; // rsp_demux:src8_data -> rsp_mux_008:sink0_data
|
|
wire rsp_demux_src8_ready; // rsp_mux_008:sink0_ready -> rsp_demux:src8_ready
|
|
wire [13:0] rsp_demux_src8_channel; // rsp_demux:src8_channel -> rsp_mux_008:sink0_channel
|
|
wire rsp_demux_src8_startofpacket; // rsp_demux:src8_startofpacket -> rsp_mux_008:sink0_startofpacket
|
|
wire rsp_demux_src8_endofpacket; // rsp_demux:src8_endofpacket -> rsp_mux_008:sink0_endofpacket
|
|
wire rsp_demux_src9_valid; // rsp_demux:src9_valid -> rsp_mux_009:sink0_valid
|
|
wire [107:0] rsp_demux_src9_data; // rsp_demux:src9_data -> rsp_mux_009:sink0_data
|
|
wire rsp_demux_src9_ready; // rsp_mux_009:sink0_ready -> rsp_demux:src9_ready
|
|
wire [13:0] rsp_demux_src9_channel; // rsp_demux:src9_channel -> rsp_mux_009:sink0_channel
|
|
wire rsp_demux_src9_startofpacket; // rsp_demux:src9_startofpacket -> rsp_mux_009:sink0_startofpacket
|
|
wire rsp_demux_src9_endofpacket; // rsp_demux:src9_endofpacket -> rsp_mux_009:sink0_endofpacket
|
|
wire rsp_demux_src10_valid; // rsp_demux:src10_valid -> rsp_mux_010:sink0_valid
|
|
wire [107:0] rsp_demux_src10_data; // rsp_demux:src10_data -> rsp_mux_010:sink0_data
|
|
wire rsp_demux_src10_ready; // rsp_mux_010:sink0_ready -> rsp_demux:src10_ready
|
|
wire [13:0] rsp_demux_src10_channel; // rsp_demux:src10_channel -> rsp_mux_010:sink0_channel
|
|
wire rsp_demux_src10_startofpacket; // rsp_demux:src10_startofpacket -> rsp_mux_010:sink0_startofpacket
|
|
wire rsp_demux_src10_endofpacket; // rsp_demux:src10_endofpacket -> rsp_mux_010:sink0_endofpacket
|
|
wire rsp_demux_src11_valid; // rsp_demux:src11_valid -> rsp_mux_011:sink0_valid
|
|
wire [107:0] rsp_demux_src11_data; // rsp_demux:src11_data -> rsp_mux_011:sink0_data
|
|
wire rsp_demux_src11_ready; // rsp_mux_011:sink0_ready -> rsp_demux:src11_ready
|
|
wire [13:0] rsp_demux_src11_channel; // rsp_demux:src11_channel -> rsp_mux_011:sink0_channel
|
|
wire rsp_demux_src11_startofpacket; // rsp_demux:src11_startofpacket -> rsp_mux_011:sink0_startofpacket
|
|
wire rsp_demux_src11_endofpacket; // rsp_demux:src11_endofpacket -> rsp_mux_011:sink0_endofpacket
|
|
wire rsp_demux_src12_valid; // rsp_demux:src12_valid -> rsp_mux_012:sink0_valid
|
|
wire [107:0] rsp_demux_src12_data; // rsp_demux:src12_data -> rsp_mux_012:sink0_data
|
|
wire rsp_demux_src12_ready; // rsp_mux_012:sink0_ready -> rsp_demux:src12_ready
|
|
wire [13:0] rsp_demux_src12_channel; // rsp_demux:src12_channel -> rsp_mux_012:sink0_channel
|
|
wire rsp_demux_src12_startofpacket; // rsp_demux:src12_startofpacket -> rsp_mux_012:sink0_startofpacket
|
|
wire rsp_demux_src12_endofpacket; // rsp_demux:src12_endofpacket -> rsp_mux_012:sink0_endofpacket
|
|
wire rsp_demux_src13_valid; // rsp_demux:src13_valid -> rsp_mux_013:sink0_valid
|
|
wire [107:0] rsp_demux_src13_data; // rsp_demux:src13_data -> rsp_mux_013:sink0_data
|
|
wire rsp_demux_src13_ready; // rsp_mux_013:sink0_ready -> rsp_demux:src13_ready
|
|
wire [13:0] rsp_demux_src13_channel; // rsp_demux:src13_channel -> rsp_mux_013:sink0_channel
|
|
wire rsp_demux_src13_startofpacket; // rsp_demux:src13_startofpacket -> rsp_mux_013:sink0_startofpacket
|
|
wire rsp_demux_src13_endofpacket; // rsp_demux:src13_endofpacket -> rsp_mux_013:sink0_endofpacket
|
|
wire rsp_mux_012_src_valid; // rsp_mux_012:src_valid -> eth0_rx_dma_m_write_rsp_width_adapter:in_valid
|
|
wire [107:0] rsp_mux_012_src_data; // rsp_mux_012:src_data -> eth0_rx_dma_m_write_rsp_width_adapter:in_data
|
|
wire rsp_mux_012_src_ready; // eth0_rx_dma_m_write_rsp_width_adapter:in_ready -> rsp_mux_012:src_ready
|
|
wire [13:0] rsp_mux_012_src_channel; // rsp_mux_012:src_channel -> eth0_rx_dma_m_write_rsp_width_adapter:in_channel
|
|
wire rsp_mux_012_src_startofpacket; // rsp_mux_012:src_startofpacket -> eth0_rx_dma_m_write_rsp_width_adapter:in_startofpacket
|
|
wire rsp_mux_012_src_endofpacket; // rsp_mux_012:src_endofpacket -> eth0_rx_dma_m_write_rsp_width_adapter:in_endofpacket
|
|
wire eth0_rx_dma_m_write_rsp_width_adapter_src_valid; // eth0_rx_dma_m_write_rsp_width_adapter:out_valid -> eth0_rx_dma_m_write_agent:rp_valid
|
|
wire [80:0] eth0_rx_dma_m_write_rsp_width_adapter_src_data; // eth0_rx_dma_m_write_rsp_width_adapter:out_data -> eth0_rx_dma_m_write_agent:rp_data
|
|
wire eth0_rx_dma_m_write_rsp_width_adapter_src_ready; // eth0_rx_dma_m_write_agent:rp_ready -> eth0_rx_dma_m_write_rsp_width_adapter:out_ready
|
|
wire [13:0] eth0_rx_dma_m_write_rsp_width_adapter_src_channel; // eth0_rx_dma_m_write_rsp_width_adapter:out_channel -> eth0_rx_dma_m_write_agent:rp_channel
|
|
wire eth0_rx_dma_m_write_rsp_width_adapter_src_startofpacket; // eth0_rx_dma_m_write_rsp_width_adapter:out_startofpacket -> eth0_rx_dma_m_write_agent:rp_startofpacket
|
|
wire eth0_rx_dma_m_write_rsp_width_adapter_src_endofpacket; // eth0_rx_dma_m_write_rsp_width_adapter:out_endofpacket -> eth0_rx_dma_m_write_agent:rp_endofpacket
|
|
wire rsp_mux_013_src_valid; // rsp_mux_013:src_valid -> eth1_rx_dma_m_write_rsp_width_adapter:in_valid
|
|
wire [107:0] rsp_mux_013_src_data; // rsp_mux_013:src_data -> eth1_rx_dma_m_write_rsp_width_adapter:in_data
|
|
wire rsp_mux_013_src_ready; // eth1_rx_dma_m_write_rsp_width_adapter:in_ready -> rsp_mux_013:src_ready
|
|
wire [13:0] rsp_mux_013_src_channel; // rsp_mux_013:src_channel -> eth1_rx_dma_m_write_rsp_width_adapter:in_channel
|
|
wire rsp_mux_013_src_startofpacket; // rsp_mux_013:src_startofpacket -> eth1_rx_dma_m_write_rsp_width_adapter:in_startofpacket
|
|
wire rsp_mux_013_src_endofpacket; // rsp_mux_013:src_endofpacket -> eth1_rx_dma_m_write_rsp_width_adapter:in_endofpacket
|
|
wire eth1_rx_dma_m_write_rsp_width_adapter_src_valid; // eth1_rx_dma_m_write_rsp_width_adapter:out_valid -> eth1_rx_dma_m_write_agent:rp_valid
|
|
wire [80:0] eth1_rx_dma_m_write_rsp_width_adapter_src_data; // eth1_rx_dma_m_write_rsp_width_adapter:out_data -> eth1_rx_dma_m_write_agent:rp_data
|
|
wire eth1_rx_dma_m_write_rsp_width_adapter_src_ready; // eth1_rx_dma_m_write_agent:rp_ready -> eth1_rx_dma_m_write_rsp_width_adapter:out_ready
|
|
wire [13:0] eth1_rx_dma_m_write_rsp_width_adapter_src_channel; // eth1_rx_dma_m_write_rsp_width_adapter:out_channel -> eth1_rx_dma_m_write_agent:rp_channel
|
|
wire eth1_rx_dma_m_write_rsp_width_adapter_src_startofpacket; // eth1_rx_dma_m_write_rsp_width_adapter:out_startofpacket -> eth1_rx_dma_m_write_agent:rp_startofpacket
|
|
wire eth1_rx_dma_m_write_rsp_width_adapter_src_endofpacket; // eth1_rx_dma_m_write_rsp_width_adapter:out_endofpacket -> eth1_rx_dma_m_write_agent:rp_endofpacket
|
|
wire router_012_src_valid; // router_012:src_valid -> eth0_rx_dma_m_write_cmd_width_adapter:in_valid
|
|
wire [80:0] router_012_src_data; // router_012:src_data -> eth0_rx_dma_m_write_cmd_width_adapter:in_data
|
|
wire router_012_src_ready; // eth0_rx_dma_m_write_cmd_width_adapter:in_ready -> router_012:src_ready
|
|
wire [13:0] router_012_src_channel; // router_012:src_channel -> eth0_rx_dma_m_write_cmd_width_adapter:in_channel
|
|
wire router_012_src_startofpacket; // router_012:src_startofpacket -> eth0_rx_dma_m_write_cmd_width_adapter:in_startofpacket
|
|
wire router_012_src_endofpacket; // router_012:src_endofpacket -> eth0_rx_dma_m_write_cmd_width_adapter:in_endofpacket
|
|
wire eth0_rx_dma_m_write_cmd_width_adapter_src_valid; // eth0_rx_dma_m_write_cmd_width_adapter:out_valid -> cmd_demux_012:sink_valid
|
|
wire [107:0] eth0_rx_dma_m_write_cmd_width_adapter_src_data; // eth0_rx_dma_m_write_cmd_width_adapter:out_data -> cmd_demux_012:sink_data
|
|
wire eth0_rx_dma_m_write_cmd_width_adapter_src_ready; // cmd_demux_012:sink_ready -> eth0_rx_dma_m_write_cmd_width_adapter:out_ready
|
|
wire [13:0] eth0_rx_dma_m_write_cmd_width_adapter_src_channel; // eth0_rx_dma_m_write_cmd_width_adapter:out_channel -> cmd_demux_012:sink_channel
|
|
wire eth0_rx_dma_m_write_cmd_width_adapter_src_startofpacket; // eth0_rx_dma_m_write_cmd_width_adapter:out_startofpacket -> cmd_demux_012:sink_startofpacket
|
|
wire eth0_rx_dma_m_write_cmd_width_adapter_src_endofpacket; // eth0_rx_dma_m_write_cmd_width_adapter:out_endofpacket -> cmd_demux_012:sink_endofpacket
|
|
wire router_013_src_valid; // router_013:src_valid -> eth1_rx_dma_m_write_cmd_width_adapter:in_valid
|
|
wire [80:0] router_013_src_data; // router_013:src_data -> eth1_rx_dma_m_write_cmd_width_adapter:in_data
|
|
wire router_013_src_ready; // eth1_rx_dma_m_write_cmd_width_adapter:in_ready -> router_013:src_ready
|
|
wire [13:0] router_013_src_channel; // router_013:src_channel -> eth1_rx_dma_m_write_cmd_width_adapter:in_channel
|
|
wire router_013_src_startofpacket; // router_013:src_startofpacket -> eth1_rx_dma_m_write_cmd_width_adapter:in_startofpacket
|
|
wire router_013_src_endofpacket; // router_013:src_endofpacket -> eth1_rx_dma_m_write_cmd_width_adapter:in_endofpacket
|
|
wire eth1_rx_dma_m_write_cmd_width_adapter_src_valid; // eth1_rx_dma_m_write_cmd_width_adapter:out_valid -> cmd_demux_013:sink_valid
|
|
wire [107:0] eth1_rx_dma_m_write_cmd_width_adapter_src_data; // eth1_rx_dma_m_write_cmd_width_adapter:out_data -> cmd_demux_013:sink_data
|
|
wire eth1_rx_dma_m_write_cmd_width_adapter_src_ready; // cmd_demux_013:sink_ready -> eth1_rx_dma_m_write_cmd_width_adapter:out_ready
|
|
wire [13:0] eth1_rx_dma_m_write_cmd_width_adapter_src_channel; // eth1_rx_dma_m_write_cmd_width_adapter:out_channel -> cmd_demux_013:sink_channel
|
|
wire eth1_rx_dma_m_write_cmd_width_adapter_src_startofpacket; // eth1_rx_dma_m_write_cmd_width_adapter:out_startofpacket -> cmd_demux_013:sink_startofpacket
|
|
wire eth1_rx_dma_m_write_cmd_width_adapter_src_endofpacket; // eth1_rx_dma_m_write_cmd_width_adapter:out_endofpacket -> cmd_demux_013:sink_endofpacket
|
|
wire nios2_onchip_mem_s2_agent_rdata_fifo_src_valid; // nios2_onchip_mem_s2_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
|
|
wire [33:0] nios2_onchip_mem_s2_agent_rdata_fifo_src_data; // nios2_onchip_mem_s2_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
|
|
wire nios2_onchip_mem_s2_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> nios2_onchip_mem_s2_agent:rdata_fifo_src_ready
|
|
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> nios2_onchip_mem_s2_agent:rdata_fifo_sink_valid
|
|
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> nios2_onchip_mem_s2_agent:rdata_fifo_sink_data
|
|
wire avalon_st_adapter_out_0_ready; // nios2_onchip_mem_s2_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
|
|
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> nios2_onchip_mem_s2_agent:rdata_fifo_sink_error
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth0_rx_dma_descriptor_read_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth0_rx_dma_descriptor_read_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth0_rx_dma_descriptor_read_waitrequest), // .waitrequest
|
|
.av_read (eth0_rx_dma_descriptor_read_read), // .read
|
|
.av_readdata (eth0_rx_dma_descriptor_read_readdata), // .readdata
|
|
.av_readdatavalid (eth0_rx_dma_descriptor_read_readdatavalid), // .readdatavalid
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth0_tx_dma_descriptor_read_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth0_tx_dma_descriptor_read_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth0_tx_dma_descriptor_read_waitrequest), // .waitrequest
|
|
.av_read (eth0_tx_dma_descriptor_read_read), // .read
|
|
.av_readdata (eth0_tx_dma_descriptor_read_readdata), // .readdata
|
|
.av_readdatavalid (eth0_tx_dma_descriptor_read_readdatavalid), // .readdatavalid
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth1_rx_dma_descriptor_read_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth1_rx_dma_descriptor_read_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth1_rx_dma_descriptor_read_waitrequest), // .waitrequest
|
|
.av_read (eth1_rx_dma_descriptor_read_read), // .read
|
|
.av_readdata (eth1_rx_dma_descriptor_read_readdata), // .readdata
|
|
.av_readdatavalid (eth1_rx_dma_descriptor_read_readdatavalid), // .readdatavalid
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth1_tx_dma_descriptor_read_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth1_tx_dma_descriptor_read_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth1_tx_dma_descriptor_read_waitrequest), // .waitrequest
|
|
.av_read (eth1_tx_dma_descriptor_read_read), // .read
|
|
.av_readdata (eth1_tx_dma_descriptor_read_readdata), // .readdata
|
|
.av_readdatavalid (eth1_tx_dma_descriptor_read_readdatavalid), // .readdatavalid
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) nios2_dma_descriptor_read_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_dma_descriptor_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (nios2_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (nios2_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (nios2_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (nios2_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (nios2_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (nios2_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (nios2_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (nios2_dma_descriptor_read_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (nios2_dma_descriptor_read_waitrequest), // .waitrequest
|
|
.av_read (nios2_dma_descriptor_read_read), // .read
|
|
.av_readdata (nios2_dma_descriptor_read_readdata), // .readdata
|
|
.av_readdatavalid (nios2_dma_descriptor_read_readdatavalid), // .readdatavalid
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (0),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth0_rx_dma_descriptor_write_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth0_rx_dma_descriptor_write_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth0_rx_dma_descriptor_write_waitrequest), // .waitrequest
|
|
.av_write (eth0_rx_dma_descriptor_write_write), // .write
|
|
.av_writedata (eth0_rx_dma_descriptor_write_writedata), // .writedata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_read (1'b0), // (terminated)
|
|
.av_readdata (), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (0),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth0_tx_dma_descriptor_write_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth0_tx_dma_descriptor_write_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth0_tx_dma_descriptor_write_waitrequest), // .waitrequest
|
|
.av_write (eth0_tx_dma_descriptor_write_write), // .write
|
|
.av_writedata (eth0_tx_dma_descriptor_write_writedata), // .writedata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_read (1'b0), // (terminated)
|
|
.av_readdata (), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (0),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth1_rx_dma_descriptor_write_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth1_rx_dma_descriptor_write_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth1_rx_dma_descriptor_write_waitrequest), // .waitrequest
|
|
.av_write (eth1_rx_dma_descriptor_write_write), // .write
|
|
.av_writedata (eth1_rx_dma_descriptor_write_writedata), // .writedata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_read (1'b0), // (terminated)
|
|
.av_readdata (), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (0),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth1_tx_dma_descriptor_write_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth1_tx_dma_descriptor_write_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth1_tx_dma_descriptor_write_waitrequest), // .waitrequest
|
|
.av_write (eth1_tx_dma_descriptor_write_write), // .write
|
|
.av_writedata (eth1_tx_dma_descriptor_write_writedata), // .writedata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_read (1'b0), // (terminated)
|
|
.av_readdata (), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (0),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) nios2_dma_descriptor_write_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_dma_descriptor_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (nios2_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (nios2_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (nios2_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (nios2_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (nios2_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (nios2_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (nios2_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (nios2_dma_descriptor_write_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (nios2_dma_descriptor_write_waitrequest), // .waitrequest
|
|
.av_write (nios2_dma_descriptor_write_write), // .write
|
|
.av_writedata (nios2_dma_descriptor_write_writedata), // .writedata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_read (1'b0), // (terminated)
|
|
.av_readdata (), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth0_tx_dma_m_read_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_tx_dma_m_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth0_tx_dma_m_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth0_tx_dma_m_read_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth0_tx_dma_m_read_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth0_tx_dma_m_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_tx_dma_m_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_tx_dma_m_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_tx_dma_m_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth0_tx_dma_m_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth0_tx_dma_m_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth0_tx_dma_m_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth0_tx_dma_m_read_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth0_tx_dma_m_read_waitrequest), // .waitrequest
|
|
.av_read (eth0_tx_dma_m_read_read), // .read
|
|
.av_readdata (eth0_tx_dma_m_read_readdata), // .readdata
|
|
.av_readdatavalid (eth0_tx_dma_m_read_readdatavalid), // .readdatavalid
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth1_tx_dma_m_read_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_tx_dma_m_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth1_tx_dma_m_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth1_tx_dma_m_read_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth1_tx_dma_m_read_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth1_tx_dma_m_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_tx_dma_m_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_tx_dma_m_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_tx_dma_m_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth1_tx_dma_m_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth1_tx_dma_m_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth1_tx_dma_m_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth1_tx_dma_m_read_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth1_tx_dma_m_read_waitrequest), // .waitrequest
|
|
.av_read (eth1_tx_dma_m_read_read), // .read
|
|
.av_readdata (eth1_tx_dma_m_read_readdata), // .readdata
|
|
.av_readdatavalid (eth1_tx_dma_m_read_readdatavalid), // .readdatavalid
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (8),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (1),
|
|
.USE_READ (0),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (1),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth0_rx_dma_m_write_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_rx_dma_m_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth0_rx_dma_m_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth0_rx_dma_m_write_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth0_rx_dma_m_write_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth0_rx_dma_m_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_rx_dma_m_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_rx_dma_m_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_rx_dma_m_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth0_rx_dma_m_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth0_rx_dma_m_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth0_rx_dma_m_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth0_rx_dma_m_write_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth0_rx_dma_m_write_waitrequest), // .waitrequest
|
|
.av_write (eth0_rx_dma_m_write_write), // .write
|
|
.av_writedata (eth0_rx_dma_m_write_writedata), // .writedata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (1'b1), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_read (1'b0), // (terminated)
|
|
.av_readdata (), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (8),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (1),
|
|
.USE_READ (0),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (1),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) eth1_rx_dma_m_write_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_rx_dma_m_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (eth1_rx_dma_m_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (eth1_rx_dma_m_write_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (eth1_rx_dma_m_write_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (eth1_rx_dma_m_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_rx_dma_m_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_rx_dma_m_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_rx_dma_m_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (eth1_rx_dma_m_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (eth1_rx_dma_m_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (eth1_rx_dma_m_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (eth1_rx_dma_m_write_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (eth1_rx_dma_m_write_waitrequest), // .waitrequest
|
|
.av_write (eth1_rx_dma_m_write_write), // .write
|
|
.av_writedata (eth1_rx_dma_m_write_writedata), // .writedata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (1'b1), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_read (1'b0), // (terminated)
|
|
.av_readdata (), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (16),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) nios2_onchip_mem_s2_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_onchip_mem_s2_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (nios2_onchip_mem_s2_agent_m0_burstcount), // .burstcount
|
|
.uav_read (nios2_onchip_mem_s2_agent_m0_read), // .read
|
|
.uav_write (nios2_onchip_mem_s2_agent_m0_write), // .write
|
|
.uav_waitrequest (nios2_onchip_mem_s2_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_onchip_mem_s2_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_onchip_mem_s2_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_onchip_mem_s2_agent_m0_readdata), // .readdata
|
|
.uav_writedata (nios2_onchip_mem_s2_agent_m0_writedata), // .writedata
|
|
.uav_lock (nios2_onchip_mem_s2_agent_m0_lock), // .lock
|
|
.uav_debugaccess (nios2_onchip_mem_s2_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (nios2_onchip_mem_s2_address), // avalon_anti_slave_0.address
|
|
.av_write (nios2_onchip_mem_s2_write), // .write
|
|
.av_readdata (nios2_onchip_mem_s2_readdata), // .readdata
|
|
.av_writedata (nios2_onchip_mem_s2_writedata), // .writedata
|
|
.av_byteenable (nios2_onchip_mem_s2_byteenable), // .byteenable
|
|
.av_chipselect (nios2_onchip_mem_s2_chipselect), // .chipselect
|
|
.av_clken (nios2_onchip_mem_s2_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (0),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth0_rx_dma_descriptor_read_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth0_rx_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth0_rx_dma_descriptor_read_agent_cp_valid), // cp.valid
|
|
.cp_data (eth0_rx_dma_descriptor_read_agent_cp_data), // .data
|
|
.cp_startofpacket (eth0_rx_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth0_rx_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth0_rx_dma_descriptor_read_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_src_data), // .data
|
|
.rp_channel (rsp_mux_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (3),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth0_tx_dma_descriptor_read_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth0_tx_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth0_tx_dma_descriptor_read_agent_cp_valid), // cp.valid
|
|
.cp_data (eth0_tx_dma_descriptor_read_agent_cp_data), // .data
|
|
.cp_startofpacket (eth0_tx_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth0_tx_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth0_tx_dma_descriptor_read_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_001_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_001_src_data), // .data
|
|
.rp_channel (rsp_mux_001_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_001_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (6),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth1_rx_dma_descriptor_read_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth1_rx_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth1_rx_dma_descriptor_read_agent_cp_valid), // cp.valid
|
|
.cp_data (eth1_rx_dma_descriptor_read_agent_cp_data), // .data
|
|
.cp_startofpacket (eth1_rx_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth1_rx_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth1_rx_dma_descriptor_read_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_002_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_002_src_data), // .data
|
|
.rp_channel (rsp_mux_002_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_002_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (9),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth1_tx_dma_descriptor_read_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth1_tx_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth1_tx_dma_descriptor_read_agent_cp_valid), // cp.valid
|
|
.cp_data (eth1_tx_dma_descriptor_read_agent_cp_data), // .data
|
|
.cp_startofpacket (eth1_tx_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth1_tx_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth1_tx_dma_descriptor_read_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_003_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_003_src_data), // .data
|
|
.rp_channel (rsp_mux_003_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_003_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (12),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) nios2_dma_descriptor_read_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (nios2_dma_descriptor_read_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (nios2_dma_descriptor_read_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (nios2_dma_descriptor_read_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (nios2_dma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (nios2_dma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (nios2_dma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (nios2_dma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (nios2_dma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (nios2_dma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (nios2_dma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (nios2_dma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (nios2_dma_descriptor_read_agent_cp_valid), // cp.valid
|
|
.cp_data (nios2_dma_descriptor_read_agent_cp_data), // .data
|
|
.cp_startofpacket (nios2_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (nios2_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (nios2_dma_descriptor_read_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_004_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_004_src_data), // .data
|
|
.rp_channel (rsp_mux_004_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_004_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_004_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_004_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (1),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth0_rx_dma_descriptor_write_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth0_rx_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth0_rx_dma_descriptor_write_agent_cp_valid), // cp.valid
|
|
.cp_data (eth0_rx_dma_descriptor_write_agent_cp_data), // .data
|
|
.cp_startofpacket (eth0_rx_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth0_rx_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth0_rx_dma_descriptor_write_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_005_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_005_src_data), // .data
|
|
.rp_channel (rsp_mux_005_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_005_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_005_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_005_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (4),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth0_tx_dma_descriptor_write_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth0_tx_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth0_tx_dma_descriptor_write_agent_cp_valid), // cp.valid
|
|
.cp_data (eth0_tx_dma_descriptor_write_agent_cp_data), // .data
|
|
.cp_startofpacket (eth0_tx_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth0_tx_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth0_tx_dma_descriptor_write_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_006_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_006_src_data), // .data
|
|
.rp_channel (rsp_mux_006_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_006_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_006_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_006_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (7),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth1_rx_dma_descriptor_write_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth1_rx_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth1_rx_dma_descriptor_write_agent_cp_valid), // cp.valid
|
|
.cp_data (eth1_rx_dma_descriptor_write_agent_cp_data), // .data
|
|
.cp_startofpacket (eth1_rx_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth1_rx_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth1_rx_dma_descriptor_write_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_007_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_007_src_data), // .data
|
|
.rp_channel (rsp_mux_007_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_007_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_007_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_007_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (10),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth1_tx_dma_descriptor_write_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth1_tx_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth1_tx_dma_descriptor_write_agent_cp_valid), // cp.valid
|
|
.cp_data (eth1_tx_dma_descriptor_write_agent_cp_data), // .data
|
|
.cp_startofpacket (eth1_tx_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth1_tx_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth1_tx_dma_descriptor_write_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_008_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_008_src_data), // .data
|
|
.rp_channel (rsp_mux_008_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_008_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_008_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_008_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (13),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) nios2_dma_descriptor_write_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (nios2_dma_descriptor_write_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (nios2_dma_descriptor_write_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (nios2_dma_descriptor_write_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (nios2_dma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (nios2_dma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (nios2_dma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (nios2_dma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (nios2_dma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (nios2_dma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (nios2_dma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (nios2_dma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (nios2_dma_descriptor_write_agent_cp_valid), // cp.valid
|
|
.cp_data (nios2_dma_descriptor_write_agent_cp_data), // .data
|
|
.cp_startofpacket (nios2_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (nios2_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (nios2_dma_descriptor_write_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_009_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_009_src_data), // .data
|
|
.rp_channel (rsp_mux_009_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_009_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_009_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_009_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (5),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth0_tx_dma_m_read_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth0_tx_dma_m_read_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth0_tx_dma_m_read_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth0_tx_dma_m_read_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth0_tx_dma_m_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth0_tx_dma_m_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth0_tx_dma_m_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth0_tx_dma_m_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth0_tx_dma_m_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth0_tx_dma_m_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth0_tx_dma_m_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth0_tx_dma_m_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth0_tx_dma_m_read_agent_cp_valid), // cp.valid
|
|
.cp_data (eth0_tx_dma_m_read_agent_cp_data), // .data
|
|
.cp_startofpacket (eth0_tx_dma_m_read_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth0_tx_dma_m_read_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth0_tx_dma_m_read_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_010_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_010_src_data), // .data
|
|
.rp_channel (rsp_mux_010_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_010_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_010_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_010_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_QOS_H (86),
|
|
.PKT_QOS_L (86),
|
|
.PKT_DATA_SIDEBAND_H (84),
|
|
.PKT_DATA_SIDEBAND_L (84),
|
|
.PKT_ADDR_SIDEBAND_H (83),
|
|
.PKT_ADDR_SIDEBAND_L (83),
|
|
.PKT_BURST_TYPE_H (82),
|
|
.PKT_BURST_TYPE_L (81),
|
|
.PKT_CACHE_H (102),
|
|
.PKT_CACHE_L (99),
|
|
.PKT_THREAD_ID_H (95),
|
|
.PKT_THREAD_ID_L (95),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (11),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth1_tx_dma_m_read_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth1_tx_dma_m_read_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth1_tx_dma_m_read_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth1_tx_dma_m_read_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth1_tx_dma_m_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth1_tx_dma_m_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth1_tx_dma_m_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth1_tx_dma_m_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth1_tx_dma_m_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth1_tx_dma_m_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth1_tx_dma_m_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth1_tx_dma_m_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth1_tx_dma_m_read_agent_cp_valid), // cp.valid
|
|
.cp_data (eth1_tx_dma_m_read_agent_cp_data), // .data
|
|
.cp_startofpacket (eth1_tx_dma_m_read_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth1_tx_dma_m_read_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth1_tx_dma_m_read_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_011_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_011_src_data), // .data
|
|
.rp_channel (rsp_mux_011_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_011_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_011_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_011_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (80),
|
|
.PKT_ORI_BURST_SIZE_L (78),
|
|
.PKT_RESPONSE_STATUS_H (77),
|
|
.PKT_RESPONSE_STATUS_L (76),
|
|
.PKT_QOS_H (59),
|
|
.PKT_QOS_L (59),
|
|
.PKT_DATA_SIDEBAND_H (57),
|
|
.PKT_DATA_SIDEBAND_L (57),
|
|
.PKT_ADDR_SIDEBAND_H (56),
|
|
.PKT_ADDR_SIDEBAND_L (56),
|
|
.PKT_BURST_TYPE_H (55),
|
|
.PKT_BURST_TYPE_L (54),
|
|
.PKT_CACHE_H (75),
|
|
.PKT_CACHE_L (72),
|
|
.PKT_THREAD_ID_H (68),
|
|
.PKT_THREAD_ID_L (68),
|
|
.PKT_BURST_SIZE_H (53),
|
|
.PKT_BURST_SIZE_L (51),
|
|
.PKT_TRANS_EXCLUSIVE (46),
|
|
.PKT_TRANS_LOCK (45),
|
|
.PKT_BEGIN_BURST (58),
|
|
.PKT_PROTECTION_H (71),
|
|
.PKT_PROTECTION_L (69),
|
|
.PKT_BURSTWRAP_H (50),
|
|
.PKT_BURSTWRAP_L (50),
|
|
.PKT_BYTE_CNT_H (49),
|
|
.PKT_BYTE_CNT_L (47),
|
|
.PKT_ADDR_H (40),
|
|
.PKT_ADDR_L (9),
|
|
.PKT_TRANS_COMPRESSED_READ (41),
|
|
.PKT_TRANS_POSTED (42),
|
|
.PKT_TRANS_WRITE (43),
|
|
.PKT_TRANS_READ (44),
|
|
.PKT_DATA_H (7),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (8),
|
|
.PKT_BYTEEN_L (8),
|
|
.PKT_SRC_ID_H (63),
|
|
.PKT_SRC_ID_L (60),
|
|
.PKT_DEST_ID_H (67),
|
|
.PKT_DEST_ID_L (64),
|
|
.ST_DATA_W (81),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.SUPPRESS_0_BYTEEN_RSP (1),
|
|
.ID (2),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth0_rx_dma_m_write_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth0_rx_dma_m_write_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth0_rx_dma_m_write_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth0_rx_dma_m_write_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth0_rx_dma_m_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth0_rx_dma_m_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth0_rx_dma_m_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth0_rx_dma_m_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth0_rx_dma_m_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth0_rx_dma_m_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth0_rx_dma_m_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth0_rx_dma_m_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth0_rx_dma_m_write_agent_cp_valid), // cp.valid
|
|
.cp_data (eth0_rx_dma_m_write_agent_cp_data), // .data
|
|
.cp_startofpacket (eth0_rx_dma_m_write_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth0_rx_dma_m_write_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth0_rx_dma_m_write_agent_cp_ready), // .ready
|
|
.rp_valid (eth0_rx_dma_m_write_rsp_width_adapter_src_valid), // rp.valid
|
|
.rp_data (eth0_rx_dma_m_write_rsp_width_adapter_src_data), // .data
|
|
.rp_channel (eth0_rx_dma_m_write_rsp_width_adapter_src_channel), // .channel
|
|
.rp_startofpacket (eth0_rx_dma_m_write_rsp_width_adapter_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (eth0_rx_dma_m_write_rsp_width_adapter_src_endofpacket), // .endofpacket
|
|
.rp_ready (eth0_rx_dma_m_write_rsp_width_adapter_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (80),
|
|
.PKT_ORI_BURST_SIZE_L (78),
|
|
.PKT_RESPONSE_STATUS_H (77),
|
|
.PKT_RESPONSE_STATUS_L (76),
|
|
.PKT_QOS_H (59),
|
|
.PKT_QOS_L (59),
|
|
.PKT_DATA_SIDEBAND_H (57),
|
|
.PKT_DATA_SIDEBAND_L (57),
|
|
.PKT_ADDR_SIDEBAND_H (56),
|
|
.PKT_ADDR_SIDEBAND_L (56),
|
|
.PKT_BURST_TYPE_H (55),
|
|
.PKT_BURST_TYPE_L (54),
|
|
.PKT_CACHE_H (75),
|
|
.PKT_CACHE_L (72),
|
|
.PKT_THREAD_ID_H (68),
|
|
.PKT_THREAD_ID_L (68),
|
|
.PKT_BURST_SIZE_H (53),
|
|
.PKT_BURST_SIZE_L (51),
|
|
.PKT_TRANS_EXCLUSIVE (46),
|
|
.PKT_TRANS_LOCK (45),
|
|
.PKT_BEGIN_BURST (58),
|
|
.PKT_PROTECTION_H (71),
|
|
.PKT_PROTECTION_L (69),
|
|
.PKT_BURSTWRAP_H (50),
|
|
.PKT_BURSTWRAP_L (50),
|
|
.PKT_BYTE_CNT_H (49),
|
|
.PKT_BYTE_CNT_L (47),
|
|
.PKT_ADDR_H (40),
|
|
.PKT_ADDR_L (9),
|
|
.PKT_TRANS_COMPRESSED_READ (41),
|
|
.PKT_TRANS_POSTED (42),
|
|
.PKT_TRANS_WRITE (43),
|
|
.PKT_TRANS_READ (44),
|
|
.PKT_DATA_H (7),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (8),
|
|
.PKT_BYTEEN_L (8),
|
|
.PKT_SRC_ID_H (63),
|
|
.PKT_SRC_ID_L (60),
|
|
.PKT_DEST_ID_H (67),
|
|
.PKT_DEST_ID_L (64),
|
|
.ST_DATA_W (81),
|
|
.ST_CHANNEL_W (14),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.SUPPRESS_0_BYTEEN_RSP (1),
|
|
.ID (8),
|
|
.BURSTWRAP_VALUE (1),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) eth1_rx_dma_m_write_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (eth1_rx_dma_m_write_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (eth1_rx_dma_m_write_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (eth1_rx_dma_m_write_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (eth1_rx_dma_m_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (eth1_rx_dma_m_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (eth1_rx_dma_m_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (eth1_rx_dma_m_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (eth1_rx_dma_m_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (eth1_rx_dma_m_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (eth1_rx_dma_m_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (eth1_rx_dma_m_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (eth1_rx_dma_m_write_agent_cp_valid), // cp.valid
|
|
.cp_data (eth1_rx_dma_m_write_agent_cp_data), // .data
|
|
.cp_startofpacket (eth1_rx_dma_m_write_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (eth1_rx_dma_m_write_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (eth1_rx_dma_m_write_agent_cp_ready), // .ready
|
|
.rp_valid (eth1_rx_dma_m_write_rsp_width_adapter_src_valid), // rp.valid
|
|
.rp_data (eth1_rx_dma_m_write_rsp_width_adapter_src_data), // .data
|
|
.rp_channel (eth1_rx_dma_m_write_rsp_width_adapter_src_channel), // .channel
|
|
.rp_startofpacket (eth1_rx_dma_m_write_rsp_width_adapter_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (eth1_rx_dma_m_write_rsp_width_adapter_src_endofpacket), // .endofpacket
|
|
.rp_ready (eth1_rx_dma_m_write_rsp_width_adapter_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (107),
|
|
.PKT_ORI_BURST_SIZE_L (105),
|
|
.PKT_RESPONSE_STATUS_H (104),
|
|
.PKT_RESPONSE_STATUS_L (103),
|
|
.PKT_BURST_SIZE_H (80),
|
|
.PKT_BURST_SIZE_L (78),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (85),
|
|
.PKT_PROTECTION_H (98),
|
|
.PKT_PROTECTION_L (96),
|
|
.PKT_BURSTWRAP_H (77),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (90),
|
|
.PKT_SRC_ID_L (87),
|
|
.PKT_DEST_ID_H (94),
|
|
.PKT_DEST_ID_L (91),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (14),
|
|
.ST_DATA_W (108),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) nios2_onchip_mem_s2_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (nios2_onchip_mem_s2_agent_m0_address), // m0.address
|
|
.m0_burstcount (nios2_onchip_mem_s2_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (nios2_onchip_mem_s2_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (nios2_onchip_mem_s2_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (nios2_onchip_mem_s2_agent_m0_lock), // .lock
|
|
.m0_readdata (nios2_onchip_mem_s2_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (nios2_onchip_mem_s2_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (nios2_onchip_mem_s2_agent_m0_read), // .read
|
|
.m0_waitrequest (nios2_onchip_mem_s2_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (nios2_onchip_mem_s2_agent_m0_writedata), // .writedata
|
|
.m0_write (nios2_onchip_mem_s2_agent_m0_write), // .write
|
|
.rp_endofpacket (nios2_onchip_mem_s2_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (nios2_onchip_mem_s2_agent_rp_ready), // .ready
|
|
.rp_valid (nios2_onchip_mem_s2_agent_rp_valid), // .valid
|
|
.rp_data (nios2_onchip_mem_s2_agent_rp_data), // .data
|
|
.rp_startofpacket (nios2_onchip_mem_s2_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_src_valid), // .valid
|
|
.cp_data (cmd_mux_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_src_channel), // .channel
|
|
.rf_sink_ready (nios2_onchip_mem_s2_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (nios2_onchip_mem_s2_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (nios2_onchip_mem_s2_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (nios2_onchip_mem_s2_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (nios2_onchip_mem_s2_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (nios2_onchip_mem_s2_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (nios2_onchip_mem_s2_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (nios2_onchip_mem_s2_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (nios2_onchip_mem_s2_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (nios2_onchip_mem_s2_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
|
|
.rdata_fifo_src_ready (nios2_onchip_mem_s2_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (nios2_onchip_mem_s2_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (nios2_onchip_mem_s2_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (109),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) nios2_onchip_mem_s2_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (nios2_onchip_mem_s2_agent_rf_source_data), // in.data
|
|
.in_valid (nios2_onchip_mem_s2_agent_rf_source_valid), // .valid
|
|
.in_ready (nios2_onchip_mem_s2_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (nios2_onchip_mem_s2_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (nios2_onchip_mem_s2_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (nios2_onchip_mem_s2_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (nios2_onchip_mem_s2_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (nios2_onchip_mem_s2_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (nios2_onchip_mem_s2_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (nios2_onchip_mem_s2_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router (
|
|
.sink_ready (eth0_rx_dma_descriptor_read_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth0_rx_dma_descriptor_read_agent_cp_valid), // .valid
|
|
.sink_data (eth0_rx_dma_descriptor_read_agent_cp_data), // .data
|
|
.sink_startofpacket (eth0_rx_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_rx_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_src_ready), // src.ready
|
|
.src_valid (router_src_valid), // .valid
|
|
.src_data (router_src_data), // .data
|
|
.src_channel (router_src_channel), // .channel
|
|
.src_startofpacket (router_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_001 (
|
|
.sink_ready (eth0_tx_dma_descriptor_read_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth0_tx_dma_descriptor_read_agent_cp_valid), // .valid
|
|
.sink_data (eth0_tx_dma_descriptor_read_agent_cp_data), // .data
|
|
.sink_startofpacket (eth0_tx_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_tx_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_001_src_ready), // src.ready
|
|
.src_valid (router_001_src_valid), // .valid
|
|
.src_data (router_001_src_data), // .data
|
|
.src_channel (router_001_src_channel), // .channel
|
|
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_002 (
|
|
.sink_ready (eth1_rx_dma_descriptor_read_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth1_rx_dma_descriptor_read_agent_cp_valid), // .valid
|
|
.sink_data (eth1_rx_dma_descriptor_read_agent_cp_data), // .data
|
|
.sink_startofpacket (eth1_rx_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_rx_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_002_src_ready), // src.ready
|
|
.src_valid (router_002_src_valid), // .valid
|
|
.src_data (router_002_src_data), // .data
|
|
.src_channel (router_002_src_channel), // .channel
|
|
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_003 (
|
|
.sink_ready (eth1_tx_dma_descriptor_read_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth1_tx_dma_descriptor_read_agent_cp_valid), // .valid
|
|
.sink_data (eth1_tx_dma_descriptor_read_agent_cp_data), // .data
|
|
.sink_startofpacket (eth1_tx_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_tx_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_003_src_ready), // src.ready
|
|
.src_valid (router_003_src_valid), // .valid
|
|
.src_data (router_003_src_data), // .data
|
|
.src_channel (router_003_src_channel), // .channel
|
|
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_004 (
|
|
.sink_ready (nios2_dma_descriptor_read_agent_cp_ready), // sink.ready
|
|
.sink_valid (nios2_dma_descriptor_read_agent_cp_valid), // .valid
|
|
.sink_data (nios2_dma_descriptor_read_agent_cp_data), // .data
|
|
.sink_startofpacket (nios2_dma_descriptor_read_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_dma_descriptor_read_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_004_src_ready), // src.ready
|
|
.src_valid (router_004_src_valid), // .valid
|
|
.src_data (router_004_src_data), // .data
|
|
.src_channel (router_004_src_channel), // .channel
|
|
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_005 (
|
|
.sink_ready (eth0_rx_dma_descriptor_write_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth0_rx_dma_descriptor_write_agent_cp_valid), // .valid
|
|
.sink_data (eth0_rx_dma_descriptor_write_agent_cp_data), // .data
|
|
.sink_startofpacket (eth0_rx_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_rx_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_005_src_ready), // src.ready
|
|
.src_valid (router_005_src_valid), // .valid
|
|
.src_data (router_005_src_data), // .data
|
|
.src_channel (router_005_src_channel), // .channel
|
|
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_006 (
|
|
.sink_ready (eth0_tx_dma_descriptor_write_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth0_tx_dma_descriptor_write_agent_cp_valid), // .valid
|
|
.sink_data (eth0_tx_dma_descriptor_write_agent_cp_data), // .data
|
|
.sink_startofpacket (eth0_tx_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_tx_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_006_src_ready), // src.ready
|
|
.src_valid (router_006_src_valid), // .valid
|
|
.src_data (router_006_src_data), // .data
|
|
.src_channel (router_006_src_channel), // .channel
|
|
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_007 (
|
|
.sink_ready (eth1_rx_dma_descriptor_write_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth1_rx_dma_descriptor_write_agent_cp_valid), // .valid
|
|
.sink_data (eth1_rx_dma_descriptor_write_agent_cp_data), // .data
|
|
.sink_startofpacket (eth1_rx_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_rx_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_007_src_ready), // src.ready
|
|
.src_valid (router_007_src_valid), // .valid
|
|
.src_data (router_007_src_data), // .data
|
|
.src_channel (router_007_src_channel), // .channel
|
|
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_008 (
|
|
.sink_ready (eth1_tx_dma_descriptor_write_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth1_tx_dma_descriptor_write_agent_cp_valid), // .valid
|
|
.sink_data (eth1_tx_dma_descriptor_write_agent_cp_data), // .data
|
|
.sink_startofpacket (eth1_tx_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_tx_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_008_src_ready), // src.ready
|
|
.src_valid (router_008_src_valid), // .valid
|
|
.src_data (router_008_src_data), // .data
|
|
.src_channel (router_008_src_channel), // .channel
|
|
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_009 (
|
|
.sink_ready (nios2_dma_descriptor_write_agent_cp_ready), // sink.ready
|
|
.sink_valid (nios2_dma_descriptor_write_agent_cp_valid), // .valid
|
|
.sink_data (nios2_dma_descriptor_write_agent_cp_data), // .data
|
|
.sink_startofpacket (nios2_dma_descriptor_write_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_dma_descriptor_write_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_009_src_ready), // src.ready
|
|
.src_valid (router_009_src_valid), // .valid
|
|
.src_data (router_009_src_data), // .data
|
|
.src_channel (router_009_src_channel), // .channel
|
|
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_010 (
|
|
.sink_ready (eth0_tx_dma_m_read_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth0_tx_dma_m_read_agent_cp_valid), // .valid
|
|
.sink_data (eth0_tx_dma_m_read_agent_cp_data), // .data
|
|
.sink_startofpacket (eth0_tx_dma_m_read_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_tx_dma_m_read_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_010_src_ready), // src.ready
|
|
.src_valid (router_010_src_valid), // .valid
|
|
.src_data (router_010_src_data), // .data
|
|
.src_channel (router_010_src_channel), // .channel
|
|
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router router_011 (
|
|
.sink_ready (eth1_tx_dma_m_read_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth1_tx_dma_m_read_agent_cp_valid), // .valid
|
|
.sink_data (eth1_tx_dma_m_read_agent_cp_data), // .data
|
|
.sink_startofpacket (eth1_tx_dma_m_read_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_tx_dma_m_read_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_011_src_ready), // src.ready
|
|
.src_valid (router_011_src_valid), // .valid
|
|
.src_data (router_011_src_data), // .data
|
|
.src_channel (router_011_src_channel), // .channel
|
|
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router_012 router_012 (
|
|
.sink_ready (eth0_rx_dma_m_write_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth0_rx_dma_m_write_agent_cp_valid), // .valid
|
|
.sink_data (eth0_rx_dma_m_write_agent_cp_data), // .data
|
|
.sink_startofpacket (eth0_rx_dma_m_write_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_rx_dma_m_write_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_012_src_ready), // src.ready
|
|
.src_valid (router_012_src_valid), // .valid
|
|
.src_data (router_012_src_data), // .data
|
|
.src_channel (router_012_src_channel), // .channel
|
|
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router_012 router_013 (
|
|
.sink_ready (eth1_rx_dma_m_write_agent_cp_ready), // sink.ready
|
|
.sink_valid (eth1_rx_dma_m_write_agent_cp_valid), // .valid
|
|
.sink_data (eth1_rx_dma_m_write_agent_cp_data), // .data
|
|
.sink_startofpacket (eth1_rx_dma_m_write_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_rx_dma_m_write_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_013_src_ready), // src.ready
|
|
.src_valid (router_013_src_valid), // .valid
|
|
.src_data (router_013_src_data), // .data
|
|
.src_channel (router_013_src_channel), // .channel
|
|
.src_startofpacket (router_013_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_013_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_router_014 router_014 (
|
|
.sink_ready (nios2_onchip_mem_s2_agent_rp_ready), // sink.ready
|
|
.sink_valid (nios2_onchip_mem_s2_agent_rp_valid), // .valid
|
|
.sink_data (nios2_onchip_mem_s2_agent_rp_data), // .data
|
|
.sink_startofpacket (nios2_onchip_mem_s2_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_onchip_mem_s2_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_014_src_ready), // src.ready
|
|
.src_valid (router_014_src_valid), // .valid
|
|
.src_data (router_014_src_data), // .data
|
|
.src_channel (router_014_src_channel), // .channel
|
|
.src_startofpacket (router_014_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_014_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_src_ready), // sink.ready
|
|
.sink_channel (router_src_channel), // .channel
|
|
.sink_data (router_src_data), // .data
|
|
.sink_startofpacket (router_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_src_valid), // .valid
|
|
.src0_ready (cmd_demux_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_src0_valid), // .valid
|
|
.src0_data (cmd_demux_src0_data), // .data
|
|
.src0_channel (cmd_demux_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_001 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_001_src_ready), // sink.ready
|
|
.sink_channel (router_001_src_channel), // .channel
|
|
.sink_data (router_001_src_data), // .data
|
|
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_001_src_valid), // .valid
|
|
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_001_src0_valid), // .valid
|
|
.src0_data (cmd_demux_001_src0_data), // .data
|
|
.src0_channel (cmd_demux_001_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_002 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_002_src_ready), // sink.ready
|
|
.sink_channel (router_002_src_channel), // .channel
|
|
.sink_data (router_002_src_data), // .data
|
|
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_002_src_valid), // .valid
|
|
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_002_src0_valid), // .valid
|
|
.src0_data (cmd_demux_002_src0_data), // .data
|
|
.src0_channel (cmd_demux_002_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_003 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_003_src_ready), // sink.ready
|
|
.sink_channel (router_003_src_channel), // .channel
|
|
.sink_data (router_003_src_data), // .data
|
|
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_003_src_valid), // .valid
|
|
.src0_ready (cmd_demux_003_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_003_src0_valid), // .valid
|
|
.src0_data (cmd_demux_003_src0_data), // .data
|
|
.src0_channel (cmd_demux_003_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_003_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_004 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_004_src_ready), // sink.ready
|
|
.sink_channel (router_004_src_channel), // .channel
|
|
.sink_data (router_004_src_data), // .data
|
|
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_004_src_valid), // .valid
|
|
.src0_ready (cmd_demux_004_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_004_src0_valid), // .valid
|
|
.src0_data (cmd_demux_004_src0_data), // .data
|
|
.src0_channel (cmd_demux_004_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_004_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_004_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_005 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_005_src_ready), // sink.ready
|
|
.sink_channel (router_005_src_channel), // .channel
|
|
.sink_data (router_005_src_data), // .data
|
|
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_005_src_valid), // .valid
|
|
.src0_ready (cmd_demux_005_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_005_src0_valid), // .valid
|
|
.src0_data (cmd_demux_005_src0_data), // .data
|
|
.src0_channel (cmd_demux_005_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_005_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_005_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_006 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_006_src_ready), // sink.ready
|
|
.sink_channel (router_006_src_channel), // .channel
|
|
.sink_data (router_006_src_data), // .data
|
|
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_006_src_valid), // .valid
|
|
.src0_ready (cmd_demux_006_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_006_src0_valid), // .valid
|
|
.src0_data (cmd_demux_006_src0_data), // .data
|
|
.src0_channel (cmd_demux_006_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_006_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_006_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_007 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_007_src_ready), // sink.ready
|
|
.sink_channel (router_007_src_channel), // .channel
|
|
.sink_data (router_007_src_data), // .data
|
|
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_007_src_valid), // .valid
|
|
.src0_ready (cmd_demux_007_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_007_src0_valid), // .valid
|
|
.src0_data (cmd_demux_007_src0_data), // .data
|
|
.src0_channel (cmd_demux_007_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_007_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_007_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_008 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_008_src_ready), // sink.ready
|
|
.sink_channel (router_008_src_channel), // .channel
|
|
.sink_data (router_008_src_data), // .data
|
|
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_008_src_valid), // .valid
|
|
.src0_ready (cmd_demux_008_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_008_src0_valid), // .valid
|
|
.src0_data (cmd_demux_008_src0_data), // .data
|
|
.src0_channel (cmd_demux_008_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_008_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_008_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_009 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_009_src_ready), // sink.ready
|
|
.sink_channel (router_009_src_channel), // .channel
|
|
.sink_data (router_009_src_data), // .data
|
|
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_009_src_valid), // .valid
|
|
.src0_ready (cmd_demux_009_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_009_src0_valid), // .valid
|
|
.src0_data (cmd_demux_009_src0_data), // .data
|
|
.src0_channel (cmd_demux_009_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_009_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_009_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_010 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_010_src_ready), // sink.ready
|
|
.sink_channel (router_010_src_channel), // .channel
|
|
.sink_data (router_010_src_data), // .data
|
|
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_010_src_valid), // .valid
|
|
.src0_ready (cmd_demux_010_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_010_src0_valid), // .valid
|
|
.src0_data (cmd_demux_010_src0_data), // .data
|
|
.src0_channel (cmd_demux_010_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_010_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_010_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_011 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_011_src_ready), // sink.ready
|
|
.sink_channel (router_011_src_channel), // .channel
|
|
.sink_data (router_011_src_data), // .data
|
|
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_011_src_valid), // .valid
|
|
.src0_ready (cmd_demux_011_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_011_src0_valid), // .valid
|
|
.src0_data (cmd_demux_011_src0_data), // .data
|
|
.src0_channel (cmd_demux_011_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_011_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_011_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_012 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (eth0_rx_dma_m_write_cmd_width_adapter_src_ready), // sink.ready
|
|
.sink_channel (eth0_rx_dma_m_write_cmd_width_adapter_src_channel), // .channel
|
|
.sink_data (eth0_rx_dma_m_write_cmd_width_adapter_src_data), // .data
|
|
.sink_startofpacket (eth0_rx_dma_m_write_cmd_width_adapter_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_rx_dma_m_write_cmd_width_adapter_src_endofpacket), // .endofpacket
|
|
.sink_valid (eth0_rx_dma_m_write_cmd_width_adapter_src_valid), // .valid
|
|
.src0_ready (cmd_demux_012_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_012_src0_valid), // .valid
|
|
.src0_data (cmd_demux_012_src0_data), // .data
|
|
.src0_channel (cmd_demux_012_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_012_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_012_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_demux cmd_demux_013 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (eth1_rx_dma_m_write_cmd_width_adapter_src_ready), // sink.ready
|
|
.sink_channel (eth1_rx_dma_m_write_cmd_width_adapter_src_channel), // .channel
|
|
.sink_data (eth1_rx_dma_m_write_cmd_width_adapter_src_data), // .data
|
|
.sink_startofpacket (eth1_rx_dma_m_write_cmd_width_adapter_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_rx_dma_m_write_cmd_width_adapter_src_endofpacket), // .endofpacket
|
|
.sink_valid (eth1_rx_dma_m_write_cmd_width_adapter_src_valid), // .valid
|
|
.src0_ready (cmd_demux_013_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_013_src0_valid), // .valid
|
|
.src0_data (cmd_demux_013_src0_data), // .data
|
|
.src0_channel (cmd_demux_013_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_013_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_013_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_cmd_mux cmd_mux (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_src_ready), // src.ready
|
|
.src_valid (cmd_mux_src_valid), // .valid
|
|
.src_data (cmd_mux_src_data), // .data
|
|
.src_channel (cmd_mux_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src0_valid), // .valid
|
|
.sink0_channel (cmd_demux_src0_channel), // .channel
|
|
.sink0_data (cmd_demux_src0_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src0_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src0_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src0_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src0_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src0_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src0_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
|
|
.sink3_ready (cmd_demux_003_src0_ready), // sink3.ready
|
|
.sink3_valid (cmd_demux_003_src0_valid), // .valid
|
|
.sink3_channel (cmd_demux_003_src0_channel), // .channel
|
|
.sink3_data (cmd_demux_003_src0_data), // .data
|
|
.sink3_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (cmd_demux_003_src0_endofpacket), // .endofpacket
|
|
.sink4_ready (cmd_demux_004_src0_ready), // sink4.ready
|
|
.sink4_valid (cmd_demux_004_src0_valid), // .valid
|
|
.sink4_channel (cmd_demux_004_src0_channel), // .channel
|
|
.sink4_data (cmd_demux_004_src0_data), // .data
|
|
.sink4_startofpacket (cmd_demux_004_src0_startofpacket), // .startofpacket
|
|
.sink4_endofpacket (cmd_demux_004_src0_endofpacket), // .endofpacket
|
|
.sink5_ready (cmd_demux_005_src0_ready), // sink5.ready
|
|
.sink5_valid (cmd_demux_005_src0_valid), // .valid
|
|
.sink5_channel (cmd_demux_005_src0_channel), // .channel
|
|
.sink5_data (cmd_demux_005_src0_data), // .data
|
|
.sink5_startofpacket (cmd_demux_005_src0_startofpacket), // .startofpacket
|
|
.sink5_endofpacket (cmd_demux_005_src0_endofpacket), // .endofpacket
|
|
.sink6_ready (cmd_demux_006_src0_ready), // sink6.ready
|
|
.sink6_valid (cmd_demux_006_src0_valid), // .valid
|
|
.sink6_channel (cmd_demux_006_src0_channel), // .channel
|
|
.sink6_data (cmd_demux_006_src0_data), // .data
|
|
.sink6_startofpacket (cmd_demux_006_src0_startofpacket), // .startofpacket
|
|
.sink6_endofpacket (cmd_demux_006_src0_endofpacket), // .endofpacket
|
|
.sink7_ready (cmd_demux_007_src0_ready), // sink7.ready
|
|
.sink7_valid (cmd_demux_007_src0_valid), // .valid
|
|
.sink7_channel (cmd_demux_007_src0_channel), // .channel
|
|
.sink7_data (cmd_demux_007_src0_data), // .data
|
|
.sink7_startofpacket (cmd_demux_007_src0_startofpacket), // .startofpacket
|
|
.sink7_endofpacket (cmd_demux_007_src0_endofpacket), // .endofpacket
|
|
.sink8_ready (cmd_demux_008_src0_ready), // sink8.ready
|
|
.sink8_valid (cmd_demux_008_src0_valid), // .valid
|
|
.sink8_channel (cmd_demux_008_src0_channel), // .channel
|
|
.sink8_data (cmd_demux_008_src0_data), // .data
|
|
.sink8_startofpacket (cmd_demux_008_src0_startofpacket), // .startofpacket
|
|
.sink8_endofpacket (cmd_demux_008_src0_endofpacket), // .endofpacket
|
|
.sink9_ready (cmd_demux_009_src0_ready), // sink9.ready
|
|
.sink9_valid (cmd_demux_009_src0_valid), // .valid
|
|
.sink9_channel (cmd_demux_009_src0_channel), // .channel
|
|
.sink9_data (cmd_demux_009_src0_data), // .data
|
|
.sink9_startofpacket (cmd_demux_009_src0_startofpacket), // .startofpacket
|
|
.sink9_endofpacket (cmd_demux_009_src0_endofpacket), // .endofpacket
|
|
.sink10_ready (cmd_demux_010_src0_ready), // sink10.ready
|
|
.sink10_valid (cmd_demux_010_src0_valid), // .valid
|
|
.sink10_channel (cmd_demux_010_src0_channel), // .channel
|
|
.sink10_data (cmd_demux_010_src0_data), // .data
|
|
.sink10_startofpacket (cmd_demux_010_src0_startofpacket), // .startofpacket
|
|
.sink10_endofpacket (cmd_demux_010_src0_endofpacket), // .endofpacket
|
|
.sink11_ready (cmd_demux_011_src0_ready), // sink11.ready
|
|
.sink11_valid (cmd_demux_011_src0_valid), // .valid
|
|
.sink11_channel (cmd_demux_011_src0_channel), // .channel
|
|
.sink11_data (cmd_demux_011_src0_data), // .data
|
|
.sink11_startofpacket (cmd_demux_011_src0_startofpacket), // .startofpacket
|
|
.sink11_endofpacket (cmd_demux_011_src0_endofpacket), // .endofpacket
|
|
.sink12_ready (cmd_demux_012_src0_ready), // sink12.ready
|
|
.sink12_valid (cmd_demux_012_src0_valid), // .valid
|
|
.sink12_channel (cmd_demux_012_src0_channel), // .channel
|
|
.sink12_data (cmd_demux_012_src0_data), // .data
|
|
.sink12_startofpacket (cmd_demux_012_src0_startofpacket), // .startofpacket
|
|
.sink12_endofpacket (cmd_demux_012_src0_endofpacket), // .endofpacket
|
|
.sink13_ready (cmd_demux_013_src0_ready), // sink13.ready
|
|
.sink13_valid (cmd_demux_013_src0_valid), // .valid
|
|
.sink13_channel (cmd_demux_013_src0_channel), // .channel
|
|
.sink13_data (cmd_demux_013_src0_data), // .data
|
|
.sink13_startofpacket (cmd_demux_013_src0_startofpacket), // .startofpacket
|
|
.sink13_endofpacket (cmd_demux_013_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_demux rsp_demux (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_014_src_ready), // sink.ready
|
|
.sink_channel (router_014_src_channel), // .channel
|
|
.sink_data (router_014_src_data), // .data
|
|
.sink_startofpacket (router_014_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_014_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_014_src_valid), // .valid
|
|
.src0_ready (rsp_demux_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_src0_valid), // .valid
|
|
.src0_data (rsp_demux_src0_data), // .data
|
|
.src0_channel (rsp_demux_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_src1_valid), // .valid
|
|
.src1_data (rsp_demux_src1_data), // .data
|
|
.src1_channel (rsp_demux_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_src2_valid), // .valid
|
|
.src2_data (rsp_demux_src2_data), // .data
|
|
.src2_channel (rsp_demux_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
|
|
.src3_ready (rsp_demux_src3_ready), // src3.ready
|
|
.src3_valid (rsp_demux_src3_valid), // .valid
|
|
.src3_data (rsp_demux_src3_data), // .data
|
|
.src3_channel (rsp_demux_src3_channel), // .channel
|
|
.src3_startofpacket (rsp_demux_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (rsp_demux_src3_endofpacket), // .endofpacket
|
|
.src4_ready (rsp_demux_src4_ready), // src4.ready
|
|
.src4_valid (rsp_demux_src4_valid), // .valid
|
|
.src4_data (rsp_demux_src4_data), // .data
|
|
.src4_channel (rsp_demux_src4_channel), // .channel
|
|
.src4_startofpacket (rsp_demux_src4_startofpacket), // .startofpacket
|
|
.src4_endofpacket (rsp_demux_src4_endofpacket), // .endofpacket
|
|
.src5_ready (rsp_demux_src5_ready), // src5.ready
|
|
.src5_valid (rsp_demux_src5_valid), // .valid
|
|
.src5_data (rsp_demux_src5_data), // .data
|
|
.src5_channel (rsp_demux_src5_channel), // .channel
|
|
.src5_startofpacket (rsp_demux_src5_startofpacket), // .startofpacket
|
|
.src5_endofpacket (rsp_demux_src5_endofpacket), // .endofpacket
|
|
.src6_ready (rsp_demux_src6_ready), // src6.ready
|
|
.src6_valid (rsp_demux_src6_valid), // .valid
|
|
.src6_data (rsp_demux_src6_data), // .data
|
|
.src6_channel (rsp_demux_src6_channel), // .channel
|
|
.src6_startofpacket (rsp_demux_src6_startofpacket), // .startofpacket
|
|
.src6_endofpacket (rsp_demux_src6_endofpacket), // .endofpacket
|
|
.src7_ready (rsp_demux_src7_ready), // src7.ready
|
|
.src7_valid (rsp_demux_src7_valid), // .valid
|
|
.src7_data (rsp_demux_src7_data), // .data
|
|
.src7_channel (rsp_demux_src7_channel), // .channel
|
|
.src7_startofpacket (rsp_demux_src7_startofpacket), // .startofpacket
|
|
.src7_endofpacket (rsp_demux_src7_endofpacket), // .endofpacket
|
|
.src8_ready (rsp_demux_src8_ready), // src8.ready
|
|
.src8_valid (rsp_demux_src8_valid), // .valid
|
|
.src8_data (rsp_demux_src8_data), // .data
|
|
.src8_channel (rsp_demux_src8_channel), // .channel
|
|
.src8_startofpacket (rsp_demux_src8_startofpacket), // .startofpacket
|
|
.src8_endofpacket (rsp_demux_src8_endofpacket), // .endofpacket
|
|
.src9_ready (rsp_demux_src9_ready), // src9.ready
|
|
.src9_valid (rsp_demux_src9_valid), // .valid
|
|
.src9_data (rsp_demux_src9_data), // .data
|
|
.src9_channel (rsp_demux_src9_channel), // .channel
|
|
.src9_startofpacket (rsp_demux_src9_startofpacket), // .startofpacket
|
|
.src9_endofpacket (rsp_demux_src9_endofpacket), // .endofpacket
|
|
.src10_ready (rsp_demux_src10_ready), // src10.ready
|
|
.src10_valid (rsp_demux_src10_valid), // .valid
|
|
.src10_data (rsp_demux_src10_data), // .data
|
|
.src10_channel (rsp_demux_src10_channel), // .channel
|
|
.src10_startofpacket (rsp_demux_src10_startofpacket), // .startofpacket
|
|
.src10_endofpacket (rsp_demux_src10_endofpacket), // .endofpacket
|
|
.src11_ready (rsp_demux_src11_ready), // src11.ready
|
|
.src11_valid (rsp_demux_src11_valid), // .valid
|
|
.src11_data (rsp_demux_src11_data), // .data
|
|
.src11_channel (rsp_demux_src11_channel), // .channel
|
|
.src11_startofpacket (rsp_demux_src11_startofpacket), // .startofpacket
|
|
.src11_endofpacket (rsp_demux_src11_endofpacket), // .endofpacket
|
|
.src12_ready (rsp_demux_src12_ready), // src12.ready
|
|
.src12_valid (rsp_demux_src12_valid), // .valid
|
|
.src12_data (rsp_demux_src12_data), // .data
|
|
.src12_channel (rsp_demux_src12_channel), // .channel
|
|
.src12_startofpacket (rsp_demux_src12_startofpacket), // .startofpacket
|
|
.src12_endofpacket (rsp_demux_src12_endofpacket), // .endofpacket
|
|
.src13_ready (rsp_demux_src13_ready), // src13.ready
|
|
.src13_valid (rsp_demux_src13_valid), // .valid
|
|
.src13_data (rsp_demux_src13_data), // .data
|
|
.src13_channel (rsp_demux_src13_channel), // .channel
|
|
.src13_startofpacket (rsp_demux_src13_startofpacket), // .startofpacket
|
|
.src13_endofpacket (rsp_demux_src13_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_src_ready), // src.ready
|
|
.src_valid (rsp_mux_src_valid), // .valid
|
|
.src_data (rsp_mux_src_data), // .data
|
|
.src_channel (rsp_mux_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src0_valid), // .valid
|
|
.sink0_channel (rsp_demux_src0_channel), // .channel
|
|
.sink0_data (rsp_demux_src0_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_001 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_001_src_ready), // src.ready
|
|
.src_valid (rsp_mux_001_src_valid), // .valid
|
|
.src_data (rsp_mux_001_src_data), // .data
|
|
.src_channel (rsp_mux_001_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src1_valid), // .valid
|
|
.sink0_channel (rsp_demux_src1_channel), // .channel
|
|
.sink0_data (rsp_demux_src1_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_002 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_002_src_ready), // src.ready
|
|
.src_valid (rsp_mux_002_src_valid), // .valid
|
|
.src_data (rsp_mux_002_src_data), // .data
|
|
.src_channel (rsp_mux_002_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src2_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src2_valid), // .valid
|
|
.sink0_channel (rsp_demux_src2_channel), // .channel
|
|
.sink0_data (rsp_demux_src2_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_003 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_003_src_ready), // src.ready
|
|
.src_valid (rsp_mux_003_src_valid), // .valid
|
|
.src_data (rsp_mux_003_src_data), // .data
|
|
.src_channel (rsp_mux_003_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src3_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src3_valid), // .valid
|
|
.sink0_channel (rsp_demux_src3_channel), // .channel
|
|
.sink0_data (rsp_demux_src3_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src3_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src3_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_004 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_004_src_ready), // src.ready
|
|
.src_valid (rsp_mux_004_src_valid), // .valid
|
|
.src_data (rsp_mux_004_src_data), // .data
|
|
.src_channel (rsp_mux_004_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_004_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_004_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src4_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src4_valid), // .valid
|
|
.sink0_channel (rsp_demux_src4_channel), // .channel
|
|
.sink0_data (rsp_demux_src4_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src4_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src4_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_005 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_005_src_ready), // src.ready
|
|
.src_valid (rsp_mux_005_src_valid), // .valid
|
|
.src_data (rsp_mux_005_src_data), // .data
|
|
.src_channel (rsp_mux_005_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_005_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_005_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src5_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src5_valid), // .valid
|
|
.sink0_channel (rsp_demux_src5_channel), // .channel
|
|
.sink0_data (rsp_demux_src5_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src5_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src5_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_006 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_006_src_ready), // src.ready
|
|
.src_valid (rsp_mux_006_src_valid), // .valid
|
|
.src_data (rsp_mux_006_src_data), // .data
|
|
.src_channel (rsp_mux_006_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_006_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_006_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src6_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src6_valid), // .valid
|
|
.sink0_channel (rsp_demux_src6_channel), // .channel
|
|
.sink0_data (rsp_demux_src6_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src6_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src6_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_007 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_007_src_ready), // src.ready
|
|
.src_valid (rsp_mux_007_src_valid), // .valid
|
|
.src_data (rsp_mux_007_src_data), // .data
|
|
.src_channel (rsp_mux_007_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_007_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_007_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src7_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src7_valid), // .valid
|
|
.sink0_channel (rsp_demux_src7_channel), // .channel
|
|
.sink0_data (rsp_demux_src7_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src7_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src7_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_008 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_008_src_ready), // src.ready
|
|
.src_valid (rsp_mux_008_src_valid), // .valid
|
|
.src_data (rsp_mux_008_src_data), // .data
|
|
.src_channel (rsp_mux_008_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_008_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_008_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src8_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src8_valid), // .valid
|
|
.sink0_channel (rsp_demux_src8_channel), // .channel
|
|
.sink0_data (rsp_demux_src8_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src8_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src8_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_009 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_009_src_ready), // src.ready
|
|
.src_valid (rsp_mux_009_src_valid), // .valid
|
|
.src_data (rsp_mux_009_src_data), // .data
|
|
.src_channel (rsp_mux_009_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_009_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_009_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src9_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src9_valid), // .valid
|
|
.sink0_channel (rsp_demux_src9_channel), // .channel
|
|
.sink0_data (rsp_demux_src9_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src9_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src9_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_010 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_010_src_ready), // src.ready
|
|
.src_valid (rsp_mux_010_src_valid), // .valid
|
|
.src_data (rsp_mux_010_src_data), // .data
|
|
.src_channel (rsp_mux_010_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_010_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_010_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src10_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src10_valid), // .valid
|
|
.sink0_channel (rsp_demux_src10_channel), // .channel
|
|
.sink0_data (rsp_demux_src10_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src10_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src10_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_011 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_011_src_ready), // src.ready
|
|
.src_valid (rsp_mux_011_src_valid), // .valid
|
|
.src_data (rsp_mux_011_src_data), // .data
|
|
.src_channel (rsp_mux_011_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_011_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_011_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src11_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src11_valid), // .valid
|
|
.sink0_channel (rsp_demux_src11_channel), // .channel
|
|
.sink0_data (rsp_demux_src11_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src11_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src11_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_012 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_012_src_ready), // src.ready
|
|
.src_valid (rsp_mux_012_src_valid), // .valid
|
|
.src_data (rsp_mux_012_src_data), // .data
|
|
.src_channel (rsp_mux_012_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_012_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_012_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src12_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src12_valid), // .valid
|
|
.sink0_channel (rsp_demux_src12_channel), // .channel
|
|
.sink0_data (rsp_demux_src12_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src12_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src12_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_2_rsp_mux rsp_mux_013 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_013_src_ready), // src.ready
|
|
.src_valid (rsp_mux_013_src_valid), // .valid
|
|
.src_data (rsp_mux_013_src_data), // .data
|
|
.src_channel (rsp_mux_013_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_013_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_013_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src13_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src13_valid), // .valid
|
|
.sink0_channel (rsp_demux_src13_channel), // .channel
|
|
.sink0_data (rsp_demux_src13_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src13_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src13_endofpacket) // .endofpacket
|
|
);
|
|
|
|
altera_merlin_width_adapter #(
|
|
.IN_PKT_ADDR_H (67),
|
|
.IN_PKT_ADDR_L (36),
|
|
.IN_PKT_DATA_H (31),
|
|
.IN_PKT_DATA_L (0),
|
|
.IN_PKT_BYTEEN_H (35),
|
|
.IN_PKT_BYTEEN_L (32),
|
|
.IN_PKT_BYTE_CNT_H (76),
|
|
.IN_PKT_BYTE_CNT_L (74),
|
|
.IN_PKT_TRANS_COMPRESSED_READ (68),
|
|
.IN_PKT_TRANS_WRITE (70),
|
|
.IN_PKT_BURSTWRAP_H (77),
|
|
.IN_PKT_BURSTWRAP_L (77),
|
|
.IN_PKT_BURST_SIZE_H (80),
|
|
.IN_PKT_BURST_SIZE_L (78),
|
|
.IN_PKT_RESPONSE_STATUS_H (104),
|
|
.IN_PKT_RESPONSE_STATUS_L (103),
|
|
.IN_PKT_TRANS_EXCLUSIVE (73),
|
|
.IN_PKT_BURST_TYPE_H (82),
|
|
.IN_PKT_BURST_TYPE_L (81),
|
|
.IN_PKT_ORI_BURST_SIZE_L (105),
|
|
.IN_PKT_ORI_BURST_SIZE_H (107),
|
|
.IN_ST_DATA_W (108),
|
|
.OUT_PKT_ADDR_H (40),
|
|
.OUT_PKT_ADDR_L (9),
|
|
.OUT_PKT_DATA_H (7),
|
|
.OUT_PKT_DATA_L (0),
|
|
.OUT_PKT_BYTEEN_H (8),
|
|
.OUT_PKT_BYTEEN_L (8),
|
|
.OUT_PKT_BYTE_CNT_H (49),
|
|
.OUT_PKT_BYTE_CNT_L (47),
|
|
.OUT_PKT_TRANS_COMPRESSED_READ (41),
|
|
.OUT_PKT_BURST_SIZE_H (53),
|
|
.OUT_PKT_BURST_SIZE_L (51),
|
|
.OUT_PKT_RESPONSE_STATUS_H (77),
|
|
.OUT_PKT_RESPONSE_STATUS_L (76),
|
|
.OUT_PKT_TRANS_EXCLUSIVE (46),
|
|
.OUT_PKT_BURST_TYPE_H (55),
|
|
.OUT_PKT_BURST_TYPE_L (54),
|
|
.OUT_PKT_ORI_BURST_SIZE_L (78),
|
|
.OUT_PKT_ORI_BURST_SIZE_H (80),
|
|
.OUT_ST_DATA_W (81),
|
|
.ST_CHANNEL_W (14),
|
|
.OPTIMIZE_FOR_RSP (1),
|
|
.RESPONSE_PATH (1),
|
|
.CONSTANT_BURST_SIZE (1),
|
|
.PACKING (1),
|
|
.ENABLE_ADDRESS_ALIGNMENT (0)
|
|
) eth0_rx_dma_m_write_rsp_width_adapter (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_valid (rsp_mux_012_src_valid), // sink.valid
|
|
.in_channel (rsp_mux_012_src_channel), // .channel
|
|
.in_startofpacket (rsp_mux_012_src_startofpacket), // .startofpacket
|
|
.in_endofpacket (rsp_mux_012_src_endofpacket), // .endofpacket
|
|
.in_ready (rsp_mux_012_src_ready), // .ready
|
|
.in_data (rsp_mux_012_src_data), // .data
|
|
.out_endofpacket (eth0_rx_dma_m_write_rsp_width_adapter_src_endofpacket), // src.endofpacket
|
|
.out_data (eth0_rx_dma_m_write_rsp_width_adapter_src_data), // .data
|
|
.out_channel (eth0_rx_dma_m_write_rsp_width_adapter_src_channel), // .channel
|
|
.out_valid (eth0_rx_dma_m_write_rsp_width_adapter_src_valid), // .valid
|
|
.out_ready (eth0_rx_dma_m_write_rsp_width_adapter_src_ready), // .ready
|
|
.out_startofpacket (eth0_rx_dma_m_write_rsp_width_adapter_src_startofpacket), // .startofpacket
|
|
.in_command_size_data (3'b000) // (terminated)
|
|
);
|
|
|
|
altera_merlin_width_adapter #(
|
|
.IN_PKT_ADDR_H (67),
|
|
.IN_PKT_ADDR_L (36),
|
|
.IN_PKT_DATA_H (31),
|
|
.IN_PKT_DATA_L (0),
|
|
.IN_PKT_BYTEEN_H (35),
|
|
.IN_PKT_BYTEEN_L (32),
|
|
.IN_PKT_BYTE_CNT_H (76),
|
|
.IN_PKT_BYTE_CNT_L (74),
|
|
.IN_PKT_TRANS_COMPRESSED_READ (68),
|
|
.IN_PKT_TRANS_WRITE (70),
|
|
.IN_PKT_BURSTWRAP_H (77),
|
|
.IN_PKT_BURSTWRAP_L (77),
|
|
.IN_PKT_BURST_SIZE_H (80),
|
|
.IN_PKT_BURST_SIZE_L (78),
|
|
.IN_PKT_RESPONSE_STATUS_H (104),
|
|
.IN_PKT_RESPONSE_STATUS_L (103),
|
|
.IN_PKT_TRANS_EXCLUSIVE (73),
|
|
.IN_PKT_BURST_TYPE_H (82),
|
|
.IN_PKT_BURST_TYPE_L (81),
|
|
.IN_PKT_ORI_BURST_SIZE_L (105),
|
|
.IN_PKT_ORI_BURST_SIZE_H (107),
|
|
.IN_ST_DATA_W (108),
|
|
.OUT_PKT_ADDR_H (40),
|
|
.OUT_PKT_ADDR_L (9),
|
|
.OUT_PKT_DATA_H (7),
|
|
.OUT_PKT_DATA_L (0),
|
|
.OUT_PKT_BYTEEN_H (8),
|
|
.OUT_PKT_BYTEEN_L (8),
|
|
.OUT_PKT_BYTE_CNT_H (49),
|
|
.OUT_PKT_BYTE_CNT_L (47),
|
|
.OUT_PKT_TRANS_COMPRESSED_READ (41),
|
|
.OUT_PKT_BURST_SIZE_H (53),
|
|
.OUT_PKT_BURST_SIZE_L (51),
|
|
.OUT_PKT_RESPONSE_STATUS_H (77),
|
|
.OUT_PKT_RESPONSE_STATUS_L (76),
|
|
.OUT_PKT_TRANS_EXCLUSIVE (46),
|
|
.OUT_PKT_BURST_TYPE_H (55),
|
|
.OUT_PKT_BURST_TYPE_L (54),
|
|
.OUT_PKT_ORI_BURST_SIZE_L (78),
|
|
.OUT_PKT_ORI_BURST_SIZE_H (80),
|
|
.OUT_ST_DATA_W (81),
|
|
.ST_CHANNEL_W (14),
|
|
.OPTIMIZE_FOR_RSP (1),
|
|
.RESPONSE_PATH (1),
|
|
.CONSTANT_BURST_SIZE (1),
|
|
.PACKING (1),
|
|
.ENABLE_ADDRESS_ALIGNMENT (0)
|
|
) eth1_rx_dma_m_write_rsp_width_adapter (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_valid (rsp_mux_013_src_valid), // sink.valid
|
|
.in_channel (rsp_mux_013_src_channel), // .channel
|
|
.in_startofpacket (rsp_mux_013_src_startofpacket), // .startofpacket
|
|
.in_endofpacket (rsp_mux_013_src_endofpacket), // .endofpacket
|
|
.in_ready (rsp_mux_013_src_ready), // .ready
|
|
.in_data (rsp_mux_013_src_data), // .data
|
|
.out_endofpacket (eth1_rx_dma_m_write_rsp_width_adapter_src_endofpacket), // src.endofpacket
|
|
.out_data (eth1_rx_dma_m_write_rsp_width_adapter_src_data), // .data
|
|
.out_channel (eth1_rx_dma_m_write_rsp_width_adapter_src_channel), // .channel
|
|
.out_valid (eth1_rx_dma_m_write_rsp_width_adapter_src_valid), // .valid
|
|
.out_ready (eth1_rx_dma_m_write_rsp_width_adapter_src_ready), // .ready
|
|
.out_startofpacket (eth1_rx_dma_m_write_rsp_width_adapter_src_startofpacket), // .startofpacket
|
|
.in_command_size_data (3'b000) // (terminated)
|
|
);
|
|
|
|
altera_merlin_width_adapter #(
|
|
.IN_PKT_ADDR_H (40),
|
|
.IN_PKT_ADDR_L (9),
|
|
.IN_PKT_DATA_H (7),
|
|
.IN_PKT_DATA_L (0),
|
|
.IN_PKT_BYTEEN_H (8),
|
|
.IN_PKT_BYTEEN_L (8),
|
|
.IN_PKT_BYTE_CNT_H (49),
|
|
.IN_PKT_BYTE_CNT_L (47),
|
|
.IN_PKT_TRANS_COMPRESSED_READ (41),
|
|
.IN_PKT_TRANS_WRITE (43),
|
|
.IN_PKT_BURSTWRAP_H (50),
|
|
.IN_PKT_BURSTWRAP_L (50),
|
|
.IN_PKT_BURST_SIZE_H (53),
|
|
.IN_PKT_BURST_SIZE_L (51),
|
|
.IN_PKT_RESPONSE_STATUS_H (77),
|
|
.IN_PKT_RESPONSE_STATUS_L (76),
|
|
.IN_PKT_TRANS_EXCLUSIVE (46),
|
|
.IN_PKT_BURST_TYPE_H (55),
|
|
.IN_PKT_BURST_TYPE_L (54),
|
|
.IN_PKT_ORI_BURST_SIZE_L (78),
|
|
.IN_PKT_ORI_BURST_SIZE_H (80),
|
|
.IN_ST_DATA_W (81),
|
|
.OUT_PKT_ADDR_H (67),
|
|
.OUT_PKT_ADDR_L (36),
|
|
.OUT_PKT_DATA_H (31),
|
|
.OUT_PKT_DATA_L (0),
|
|
.OUT_PKT_BYTEEN_H (35),
|
|
.OUT_PKT_BYTEEN_L (32),
|
|
.OUT_PKT_BYTE_CNT_H (76),
|
|
.OUT_PKT_BYTE_CNT_L (74),
|
|
.OUT_PKT_TRANS_COMPRESSED_READ (68),
|
|
.OUT_PKT_BURST_SIZE_H (80),
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|
.OUT_PKT_BURST_SIZE_L (78),
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|
.OUT_PKT_RESPONSE_STATUS_H (104),
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|
.OUT_PKT_RESPONSE_STATUS_L (103),
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|
.OUT_PKT_TRANS_EXCLUSIVE (73),
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|
.OUT_PKT_BURST_TYPE_H (82),
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|
.OUT_PKT_BURST_TYPE_L (81),
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|
.OUT_PKT_ORI_BURST_SIZE_L (105),
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|
.OUT_PKT_ORI_BURST_SIZE_H (107),
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|
.OUT_ST_DATA_W (108),
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|
.ST_CHANNEL_W (14),
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|
.OPTIMIZE_FOR_RSP (0),
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|
.RESPONSE_PATH (0),
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.CONSTANT_BURST_SIZE (1),
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.PACKING (1),
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.ENABLE_ADDRESS_ALIGNMENT (0)
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) eth0_rx_dma_m_write_cmd_width_adapter (
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.clk (clk_0_clk_clk), // clk.clk
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.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
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|
.in_valid (router_012_src_valid), // sink.valid
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.in_channel (router_012_src_channel), // .channel
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|
.in_startofpacket (router_012_src_startofpacket), // .startofpacket
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|
.in_endofpacket (router_012_src_endofpacket), // .endofpacket
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|
.in_ready (router_012_src_ready), // .ready
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|
.in_data (router_012_src_data), // .data
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|
.out_endofpacket (eth0_rx_dma_m_write_cmd_width_adapter_src_endofpacket), // src.endofpacket
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|
.out_data (eth0_rx_dma_m_write_cmd_width_adapter_src_data), // .data
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|
.out_channel (eth0_rx_dma_m_write_cmd_width_adapter_src_channel), // .channel
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|
.out_valid (eth0_rx_dma_m_write_cmd_width_adapter_src_valid), // .valid
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|
.out_ready (eth0_rx_dma_m_write_cmd_width_adapter_src_ready), // .ready
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|
.out_startofpacket (eth0_rx_dma_m_write_cmd_width_adapter_src_startofpacket), // .startofpacket
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|
.in_command_size_data (3'b000) // (terminated)
|
|
);
|
|
|
|
altera_merlin_width_adapter #(
|
|
.IN_PKT_ADDR_H (40),
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|
.IN_PKT_ADDR_L (9),
|
|
.IN_PKT_DATA_H (7),
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|
.IN_PKT_DATA_L (0),
|
|
.IN_PKT_BYTEEN_H (8),
|
|
.IN_PKT_BYTEEN_L (8),
|
|
.IN_PKT_BYTE_CNT_H (49),
|
|
.IN_PKT_BYTE_CNT_L (47),
|
|
.IN_PKT_TRANS_COMPRESSED_READ (41),
|
|
.IN_PKT_TRANS_WRITE (43),
|
|
.IN_PKT_BURSTWRAP_H (50),
|
|
.IN_PKT_BURSTWRAP_L (50),
|
|
.IN_PKT_BURST_SIZE_H (53),
|
|
.IN_PKT_BURST_SIZE_L (51),
|
|
.IN_PKT_RESPONSE_STATUS_H (77),
|
|
.IN_PKT_RESPONSE_STATUS_L (76),
|
|
.IN_PKT_TRANS_EXCLUSIVE (46),
|
|
.IN_PKT_BURST_TYPE_H (55),
|
|
.IN_PKT_BURST_TYPE_L (54),
|
|
.IN_PKT_ORI_BURST_SIZE_L (78),
|
|
.IN_PKT_ORI_BURST_SIZE_H (80),
|
|
.IN_ST_DATA_W (81),
|
|
.OUT_PKT_ADDR_H (67),
|
|
.OUT_PKT_ADDR_L (36),
|
|
.OUT_PKT_DATA_H (31),
|
|
.OUT_PKT_DATA_L (0),
|
|
.OUT_PKT_BYTEEN_H (35),
|
|
.OUT_PKT_BYTEEN_L (32),
|
|
.OUT_PKT_BYTE_CNT_H (76),
|
|
.OUT_PKT_BYTE_CNT_L (74),
|
|
.OUT_PKT_TRANS_COMPRESSED_READ (68),
|
|
.OUT_PKT_BURST_SIZE_H (80),
|
|
.OUT_PKT_BURST_SIZE_L (78),
|
|
.OUT_PKT_RESPONSE_STATUS_H (104),
|
|
.OUT_PKT_RESPONSE_STATUS_L (103),
|
|
.OUT_PKT_TRANS_EXCLUSIVE (73),
|
|
.OUT_PKT_BURST_TYPE_H (82),
|
|
.OUT_PKT_BURST_TYPE_L (81),
|
|
.OUT_PKT_ORI_BURST_SIZE_L (105),
|
|
.OUT_PKT_ORI_BURST_SIZE_H (107),
|
|
.OUT_ST_DATA_W (108),
|
|
.ST_CHANNEL_W (14),
|
|
.OPTIMIZE_FOR_RSP (0),
|
|
.RESPONSE_PATH (0),
|
|
.CONSTANT_BURST_SIZE (1),
|
|
.PACKING (1),
|
|
.ENABLE_ADDRESS_ALIGNMENT (0)
|
|
) eth1_rx_dma_m_write_cmd_width_adapter (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_valid (router_013_src_valid), // sink.valid
|
|
.in_channel (router_013_src_channel), // .channel
|
|
.in_startofpacket (router_013_src_startofpacket), // .startofpacket
|
|
.in_endofpacket (router_013_src_endofpacket), // .endofpacket
|
|
.in_ready (router_013_src_ready), // .ready
|
|
.in_data (router_013_src_data), // .data
|
|
.out_endofpacket (eth1_rx_dma_m_write_cmd_width_adapter_src_endofpacket), // src.endofpacket
|
|
.out_data (eth1_rx_dma_m_write_cmd_width_adapter_src_data), // .data
|
|
.out_channel (eth1_rx_dma_m_write_cmd_width_adapter_src_channel), // .channel
|
|
.out_valid (eth1_rx_dma_m_write_cmd_width_adapter_src_valid), // .valid
|
|
.out_ready (eth1_rx_dma_m_write_cmd_width_adapter_src_ready), // .ready
|
|
.out_startofpacket (eth1_rx_dma_m_write_cmd_width_adapter_src_startofpacket), // .startofpacket
|
|
.in_command_size_data (3'b000) // (terminated)
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (eth0_rx_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (nios2_onchip_mem_s2_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (nios2_onchip_mem_s2_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (nios2_onchip_mem_s2_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_out_0_error) // .error
|
|
);
|
|
|
|
endmodule
|