116 lines
4.0 KiB
Systemverilog
Executable File
116 lines
4.0 KiB
Systemverilog
Executable File
// (C) 2001-2018 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
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// $Revision: #1 $
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// $Date: 2018/07/18 $
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// $Author: psgswbuild $
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// -------------------------------------
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// Merlin Demultiplexer
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//
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// Asserts valid on the appropriate output
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// given a one-hot channel signal.
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// -------------------------------------
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`timescale 1 ns / 1 ns
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// ------------------------------------------
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// Generation parameters:
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// output_name: ECE385_mm_interconnect_1_rsp_demux
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// ST_DATA_W: 95
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// ST_CHANNEL_W: 11
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// NUM_OUTPUTS: 2
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// VALID_WIDTH: 1
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// ------------------------------------------
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//------------------------------------------
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// Message Supression Used
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// QIS Warnings
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// 15610 - Warning: Design contains x input pin(s) that do not drive logic
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//------------------------------------------
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module ECE385_mm_interconnect_1_rsp_demux
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(
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// -------------------
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// Sink
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// -------------------
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input [1-1 : 0] sink_valid,
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input [95-1 : 0] sink_data, // ST_DATA_W=95
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input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11
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input sink_startofpacket,
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input sink_endofpacket,
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output sink_ready,
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// -------------------
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// Sources
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// -------------------
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output reg src0_valid,
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output reg [95-1 : 0] src0_data, // ST_DATA_W=95
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output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11
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output reg src0_startofpacket,
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output reg src0_endofpacket,
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input src0_ready,
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output reg src1_valid,
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output reg [95-1 : 0] src1_data, // ST_DATA_W=95
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output reg [11-1 : 0] src1_channel, // ST_CHANNEL_W=11
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output reg src1_startofpacket,
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output reg src1_endofpacket,
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input src1_ready,
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// -------------------
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// Clock & Reset
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// -------------------
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(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
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input clk,
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(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
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input reset
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);
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localparam NUM_OUTPUTS = 2;
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wire [NUM_OUTPUTS - 1 : 0] ready_vector;
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// -------------------
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// Demux
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// -------------------
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always @* begin
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src0_data = sink_data;
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src0_startofpacket = sink_startofpacket;
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src0_endofpacket = sink_endofpacket;
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src0_channel = sink_channel >> NUM_OUTPUTS;
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src0_valid = sink_channel[0] && sink_valid;
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src1_data = sink_data;
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src1_startofpacket = sink_startofpacket;
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src1_endofpacket = sink_endofpacket;
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src1_channel = sink_channel >> NUM_OUTPUTS;
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src1_valid = sink_channel[1] && sink_valid;
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end
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// -------------------
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// Backpressure
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// -------------------
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assign ready_vector[0] = src0_ready;
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assign ready_vector[1] = src1_ready;
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assign sink_ready = |(sink_channel & {{9{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
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endmodule
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