296 lines
10 KiB
Systemverilog
Executable File
296 lines
10 KiB
Systemverilog
Executable File
// (C) 2001-2018 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
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// $Revision: #1 $
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// $Date: 2018/07/18 $
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// $Author: psgswbuild $
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// -------------------------------------------------------
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// Merlin Router
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//
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// Asserts the appropriate one-hot encoded channel based on
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// either (a) the address or (b) the dest id. The DECODER_TYPE
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// parameter controls this behaviour. 0 means address decoder,
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// 1 means dest id decoder.
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//
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// In the case of (a), it also sets the destination id.
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// -------------------------------------------------------
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`timescale 1 ns / 1 ns
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module ECE385_mm_interconnect_1_router_default_decode
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#(
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parameter DEFAULT_CHANNEL = 3,
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DEFAULT_WR_CHANNEL = -1,
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DEFAULT_RD_CHANNEL = -1,
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DEFAULT_DESTID = 9
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)
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(output [81 - 78 : 0] default_destination_id,
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output [11-1 : 0] default_wr_channel,
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output [11-1 : 0] default_rd_channel,
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output [11-1 : 0] default_src_channel
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);
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assign default_destination_id =
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DEFAULT_DESTID[81 - 78 : 0];
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generate
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if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
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assign default_src_channel = '0;
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end
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else begin : default_channel_assignment
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assign default_src_channel = 11'b1 << DEFAULT_CHANNEL;
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end
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endgenerate
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generate
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if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
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assign default_wr_channel = '0;
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assign default_rd_channel = '0;
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end
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else begin : default_rw_channel_assignment
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assign default_wr_channel = 11'b1 << DEFAULT_WR_CHANNEL;
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assign default_rd_channel = 11'b1 << DEFAULT_RD_CHANNEL;
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end
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endgenerate
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endmodule
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module ECE385_mm_interconnect_1_router
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(
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// -------------------
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// Clock & Reset
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// -------------------
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input clk,
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input reset,
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// -------------------
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// Command Sink (Input)
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// -------------------
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input sink_valid,
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input [95-1 : 0] sink_data,
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input sink_startofpacket,
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input sink_endofpacket,
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output sink_ready,
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// -------------------
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// Command Source (Output)
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// -------------------
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output src_valid,
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output reg [95-1 : 0] src_data,
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output reg [11-1 : 0] src_channel,
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output src_startofpacket,
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output src_endofpacket,
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input src_ready
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);
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// -------------------------------------------------------
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// Local parameters and variables
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// -------------------------------------------------------
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localparam PKT_ADDR_H = 52;
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localparam PKT_ADDR_L = 36;
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localparam PKT_DEST_ID_H = 81;
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localparam PKT_DEST_ID_L = 78;
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localparam PKT_PROTECTION_H = 85;
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localparam PKT_PROTECTION_L = 83;
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localparam ST_DATA_W = 95;
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localparam ST_CHANNEL_W = 11;
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localparam DECODER_TYPE = 0;
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localparam PKT_TRANS_WRITE = 55;
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localparam PKT_TRANS_READ = 56;
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localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
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localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
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// -------------------------------------------------------
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// Figure out the number of bits to mask off for each slave span
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// during address decoding
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// -------------------------------------------------------
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localparam PAD0 = log2ceil(64'h800 - 64'h0);
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localparam PAD1 = log2ceil(64'h808 - 64'h800);
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localparam PAD2 = log2ceil(64'h810 - 64'h808);
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localparam PAD3 = log2ceil(64'h820 - 64'h810);
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localparam PAD4 = log2ceil(64'h830 - 64'h820);
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localparam PAD5 = log2ceil(64'h840 - 64'h830);
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localparam PAD6 = log2ceil(64'h850 - 64'h840);
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localparam PAD7 = log2ceil(64'h860 - 64'h850);
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localparam PAD8 = log2ceil(64'h870 - 64'h860);
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localparam PAD9 = log2ceil(64'h1000 - 64'hc00);
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localparam PAD10 = log2ceil(64'h14000 - 64'h10000);
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// -------------------------------------------------------
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// Work out which address bits are significant based on the
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// address range of the slaves. If the required width is too
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// large or too small, we use the address field width instead.
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// -------------------------------------------------------
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localparam ADDR_RANGE = 64'h14000;
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localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
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localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
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(RANGE_ADDR_WIDTH == 0) ?
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PKT_ADDR_H :
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PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
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localparam RG = RANGE_ADDR_WIDTH-1;
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localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
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reg [PKT_ADDR_W-1 : 0] address;
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always @* begin
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address = {PKT_ADDR_W{1'b0}};
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address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
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end
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// -------------------------------------------------------
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// Pass almost everything through, untouched
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// -------------------------------------------------------
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assign sink_ready = src_ready;
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assign src_valid = sink_valid;
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assign src_startofpacket = sink_startofpacket;
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assign src_endofpacket = sink_endofpacket;
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wire [PKT_DEST_ID_W-1:0] default_destid;
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wire [11-1 : 0] default_src_channel;
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// -------------------------------------------------------
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// Write and read transaction signals
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// -------------------------------------------------------
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wire read_transaction;
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assign read_transaction = sink_data[PKT_TRANS_READ];
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ECE385_mm_interconnect_1_router_default_decode the_default_decode(
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.default_destination_id (default_destid),
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.default_wr_channel (),
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.default_rd_channel (),
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.default_src_channel (default_src_channel)
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);
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always @* begin
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src_data = sink_data;
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src_channel = default_src_channel;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
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// --------------------------------------------------
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// Address Decoder
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// Sets the channel and destination ID based on the address
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// --------------------------------------------------
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// ( 0x0 .. 0x800 )
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if ( {address[RG:PAD0],{PAD0{1'b0}}} == 17'h0 ) begin
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src_channel = 11'b00000000100;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
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end
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// ( 0x800 .. 0x808 )
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if ( {address[RG:PAD1],{PAD1{1'b0}}} == 17'h800 && read_transaction ) begin
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src_channel = 11'b00000000010;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
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end
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// ( 0x808 .. 0x810 )
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if ( {address[RG:PAD2],{PAD2{1'b0}}} == 17'h808 ) begin
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src_channel = 11'b00000000001;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
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end
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// ( 0x810 .. 0x820 )
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if ( {address[RG:PAD3],{PAD3{1'b0}}} == 17'h810 ) begin
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src_channel = 11'b01000000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
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end
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// ( 0x820 .. 0x830 )
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if ( {address[RG:PAD4],{PAD4{1'b0}}} == 17'h820 ) begin
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src_channel = 11'b00100000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
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end
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// ( 0x830 .. 0x840 )
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if ( {address[RG:PAD5],{PAD5{1'b0}}} == 17'h830 ) begin
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src_channel = 11'b00010000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
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end
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// ( 0x840 .. 0x850 )
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if ( {address[RG:PAD6],{PAD6{1'b0}}} == 17'h840 ) begin
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src_channel = 11'b00001000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
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end
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// ( 0x850 .. 0x860 )
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if ( {address[RG:PAD7],{PAD7{1'b0}}} == 17'h850 ) begin
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src_channel = 11'b00000100000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
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end
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// ( 0x860 .. 0x870 )
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if ( {address[RG:PAD8],{PAD8{1'b0}}} == 17'h860 ) begin
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src_channel = 11'b00000010000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
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end
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// ( 0xc00 .. 0x1000 )
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if ( {address[RG:PAD9],{PAD9{1'b0}}} == 17'hc00 ) begin
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src_channel = 11'b10000000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
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end
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// ( 0x10000 .. 0x14000 )
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if ( {address[RG:PAD10],{PAD10{1'b0}}} == 17'h10000 ) begin
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src_channel = 11'b00000001000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
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end
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end
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// --------------------------------------------------
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// Ceil(log2()) function
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// --------------------------------------------------
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function integer log2ceil;
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input reg[65:0] val;
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reg [65:0] i;
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begin
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i = 1;
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log2ceil = 0;
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while (i < val) begin
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log2ceil = log2ceil + 1;
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i = i << 1;
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end
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end
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endfunction
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endmodule
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