15049 lines
1.3 MiB
Executable File
15049 lines
1.3 MiB
Executable File
// ECE385_mm_interconnect_0.v
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// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
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// will probably be lost.
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//
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// Generated using ACDS version 18.1 625
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`timescale 1 ps / 1 ps
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module ECE385_mm_interconnect_0 (
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input wire clk_0_clk_clk, // clk_0_clk.clk
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input wire nios2_cpu_reset_reset_bridge_in_reset_reset, // nios2_cpu_reset_reset_bridge_in_reset.reset
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input wire nios2_dma_reset_reset_bridge_in_reset_reset, // nios2_dma_reset_reset_bridge_in_reset.reset
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input wire [27:0] nios2_cpu_data_master_address, // nios2_cpu_data_master.address
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output wire nios2_cpu_data_master_waitrequest, // .waitrequest
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input wire [3:0] nios2_cpu_data_master_byteenable, // .byteenable
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input wire nios2_cpu_data_master_read, // .read
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output wire [31:0] nios2_cpu_data_master_readdata, // .readdata
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input wire nios2_cpu_data_master_write, // .write
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input wire [31:0] nios2_cpu_data_master_writedata, // .writedata
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input wire nios2_cpu_data_master_debugaccess, // .debugaccess
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input wire [27:0] nios2_cpu_instruction_master_address, // nios2_cpu_instruction_master.address
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output wire nios2_cpu_instruction_master_waitrequest, // .waitrequest
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input wire nios2_cpu_instruction_master_read, // .read
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output wire [31:0] nios2_cpu_instruction_master_readdata, // .readdata
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input wire [31:0] nios2_dma_m_read_address, // nios2_dma_m_read.address
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output wire nios2_dma_m_read_waitrequest, // .waitrequest
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input wire nios2_dma_m_read_read, // .read
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output wire [31:0] nios2_dma_m_read_readdata, // .readdata
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output wire nios2_dma_m_read_readdatavalid, // .readdatavalid
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input wire [31:0] nios2_dma_m_write_address, // nios2_dma_m_write.address
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output wire nios2_dma_m_write_waitrequest, // .waitrequest
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input wire [3:0] nios2_dma_m_write_byteenable, // .byteenable
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input wire nios2_dma_m_write_write, // .write
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input wire [31:0] nios2_dma_m_write_writedata, // .writedata
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output wire [1:0] audio_pio_s1_address, // audio_pio_s1.address
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output wire audio_pio_s1_write, // .write
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input wire [31:0] audio_pio_s1_readdata, // .readdata
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output wire [31:0] audio_pio_s1_writedata, // .writedata
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output wire audio_pio_s1_chipselect, // .chipselect
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output wire [2:0] audio_timer_s1_address, // audio_timer_s1.address
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output wire audio_timer_s1_write, // .write
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input wire [15:0] audio_timer_s1_readdata, // .readdata
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output wire [15:0] audio_timer_s1_writedata, // .writedata
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output wire audio_timer_s1_chipselect, // .chipselect
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output wire [4:0] eth0_mdio_avalon_slave_address, // eth0_mdio_avalon_slave.address
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output wire eth0_mdio_avalon_slave_write, // .write
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output wire eth0_mdio_avalon_slave_read, // .read
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input wire [31:0] eth0_mdio_avalon_slave_readdata, // .readdata
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output wire [31:0] eth0_mdio_avalon_slave_writedata, // .writedata
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input wire eth0_mdio_avalon_slave_waitrequest, // .waitrequest
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output wire [3:0] eth0_rx_dma_csr_address, // eth0_rx_dma_csr.address
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output wire eth0_rx_dma_csr_write, // .write
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output wire eth0_rx_dma_csr_read, // .read
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input wire [31:0] eth0_rx_dma_csr_readdata, // .readdata
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output wire [31:0] eth0_rx_dma_csr_writedata, // .writedata
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output wire eth0_rx_dma_csr_chipselect, // .chipselect
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output wire [3:0] eth0_tx_dma_csr_address, // eth0_tx_dma_csr.address
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output wire eth0_tx_dma_csr_write, // .write
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output wire eth0_tx_dma_csr_read, // .read
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input wire [31:0] eth0_tx_dma_csr_readdata, // .readdata
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output wire [31:0] eth0_tx_dma_csr_writedata, // .writedata
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output wire eth0_tx_dma_csr_chipselect, // .chipselect
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output wire [4:0] eth1_mdio_avalon_slave_address, // eth1_mdio_avalon_slave.address
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output wire eth1_mdio_avalon_slave_write, // .write
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output wire eth1_mdio_avalon_slave_read, // .read
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input wire [31:0] eth1_mdio_avalon_slave_readdata, // .readdata
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output wire [31:0] eth1_mdio_avalon_slave_writedata, // .writedata
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input wire eth1_mdio_avalon_slave_waitrequest, // .waitrequest
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output wire [3:0] eth1_rx_dma_csr_address, // eth1_rx_dma_csr.address
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output wire eth1_rx_dma_csr_write, // .write
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output wire eth1_rx_dma_csr_read, // .read
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input wire [31:0] eth1_rx_dma_csr_readdata, // .readdata
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output wire [31:0] eth1_rx_dma_csr_writedata, // .writedata
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output wire eth1_rx_dma_csr_chipselect, // .chipselect
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output wire [3:0] eth1_tx_dma_csr_address, // eth1_tx_dma_csr.address
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output wire eth1_tx_dma_csr_write, // .write
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output wire eth1_tx_dma_csr_read, // .read
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input wire [31:0] eth1_tx_dma_csr_readdata, // .readdata
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output wire [31:0] eth1_tx_dma_csr_writedata, // .writedata
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output wire eth1_tx_dma_csr_chipselect, // .chipselect
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output wire [2:0] io_hex_s1_address, // io_hex_s1.address
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output wire io_hex_s1_write, // .write
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input wire [31:0] io_hex_s1_readdata, // .readdata
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output wire [31:0] io_hex_s1_writedata, // .writedata
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output wire io_hex_s1_chipselect, // .chipselect
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output wire [1:0] io_keys_s1_address, // io_keys_s1.address
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input wire [31:0] io_keys_s1_readdata, // .readdata
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output wire [2:0] io_led_green_s1_address, // io_led_green_s1.address
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output wire io_led_green_s1_write, // .write
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input wire [31:0] io_led_green_s1_readdata, // .readdata
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output wire [31:0] io_led_green_s1_writedata, // .writedata
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output wire io_led_green_s1_chipselect, // .chipselect
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output wire [2:0] io_led_red_s1_address, // io_led_red_s1.address
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output wire io_led_red_s1_write, // .write
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input wire [31:0] io_led_red_s1_readdata, // .readdata
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output wire [31:0] io_led_red_s1_writedata, // .writedata
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output wire io_led_red_s1_chipselect, // .chipselect
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output wire [1:0] io_switches_s1_address, // io_switches_s1.address
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input wire [31:0] io_switches_s1_readdata, // .readdata
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output wire [1:0] io_vga_sync_s1_address, // io_vga_sync_s1.address
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input wire [31:0] io_vga_sync_s1_readdata, // .readdata
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output wire [8:0] nios2_cpu_debug_mem_slave_address, // nios2_cpu_debug_mem_slave.address
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output wire nios2_cpu_debug_mem_slave_write, // .write
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output wire nios2_cpu_debug_mem_slave_read, // .read
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input wire [31:0] nios2_cpu_debug_mem_slave_readdata, // .readdata
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output wire [31:0] nios2_cpu_debug_mem_slave_writedata, // .writedata
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output wire [3:0] nios2_cpu_debug_mem_slave_byteenable, // .byteenable
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input wire nios2_cpu_debug_mem_slave_waitrequest, // .waitrequest
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output wire nios2_cpu_debug_mem_slave_debugaccess, // .debugaccess
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output wire [3:0] nios2_dma_csr_address, // nios2_dma_csr.address
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output wire nios2_dma_csr_write, // .write
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output wire nios2_dma_csr_read, // .read
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input wire [31:0] nios2_dma_csr_readdata, // .readdata
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output wire [31:0] nios2_dma_csr_writedata, // .writedata
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output wire nios2_dma_csr_chipselect, // .chipselect
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output wire [0:0] nios2_jtag_uart_avalon_jtag_slave_address, // nios2_jtag_uart_avalon_jtag_slave.address
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output wire nios2_jtag_uart_avalon_jtag_slave_write, // .write
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output wire nios2_jtag_uart_avalon_jtag_slave_read, // .read
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input wire [31:0] nios2_jtag_uart_avalon_jtag_slave_readdata, // .readdata
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output wire [31:0] nios2_jtag_uart_avalon_jtag_slave_writedata, // .writedata
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input wire nios2_jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
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output wire nios2_jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
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output wire [15:0] nios2_onchip_mem_s1_address, // nios2_onchip_mem_s1.address
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output wire nios2_onchip_mem_s1_write, // .write
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input wire [31:0] nios2_onchip_mem_s1_readdata, // .readdata
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output wire [31:0] nios2_onchip_mem_s1_writedata, // .writedata
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output wire [3:0] nios2_onchip_mem_s1_byteenable, // .byteenable
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output wire nios2_onchip_mem_s1_chipselect, // .chipselect
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output wire nios2_onchip_mem_s1_clken, // .clken
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output wire [1:0] nios2_pll_pll_slave_address, // nios2_pll_pll_slave.address
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output wire nios2_pll_pll_slave_write, // .write
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output wire nios2_pll_pll_slave_read, // .read
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input wire [31:0] nios2_pll_pll_slave_readdata, // .readdata
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output wire [31:0] nios2_pll_pll_slave_writedata, // .writedata
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output wire [0:0] nios2_sysid_control_slave_address, // nios2_sysid_control_slave.address
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input wire [31:0] nios2_sysid_control_slave_readdata, // .readdata
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output wire [2:0] nios2_timer_s1_address, // nios2_timer_s1.address
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output wire nios2_timer_s1_write, // .write
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input wire [15:0] nios2_timer_s1_readdata, // .readdata
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output wire [15:0] nios2_timer_s1_writedata, // .writedata
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output wire nios2_timer_s1_chipselect, // .chipselect
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output wire [24:0] sdram_s1_address, // sdram_s1.address
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output wire sdram_s1_write, // .write
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output wire sdram_s1_read, // .read
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input wire [31:0] sdram_s1_readdata, // .readdata
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output wire [31:0] sdram_s1_writedata, // .writedata
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output wire [3:0] sdram_s1_byteenable, // .byteenable
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input wire sdram_s1_readdatavalid, // .readdatavalid
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input wire sdram_s1_waitrequest, // .waitrequest
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output wire sdram_s1_chipselect, // .chipselect
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output wire [19:0] sram_multiplexer_avl_address, // sram_multiplexer_avl.address
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output wire sram_multiplexer_avl_write, // .write
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output wire sram_multiplexer_avl_read, // .read
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input wire [15:0] sram_multiplexer_avl_readdata, // .readdata
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output wire [15:0] sram_multiplexer_avl_writedata, // .writedata
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output wire [7:0] usb_keycode_s2_address, // usb_keycode_s2.address
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output wire usb_keycode_s2_write, // .write
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input wire [31:0] usb_keycode_s2_readdata, // .readdata
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output wire [31:0] usb_keycode_s2_writedata, // .writedata
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output wire [3:0] usb_keycode_s2_byteenable, // .byteenable
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output wire usb_keycode_s2_chipselect, // .chipselect
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output wire usb_keycode_s2_clken, // .clken
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output wire [1:0] vga_background_offset_s1_address, // vga_background_offset_s1.address
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output wire vga_background_offset_s1_write, // .write
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input wire [31:0] vga_background_offset_s1_readdata, // .readdata
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output wire [31:0] vga_background_offset_s1_writedata, // .writedata
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output wire vga_background_offset_s1_chipselect, // .chipselect
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output wire [9:0] vga_sprite_0_s1_address, // vga_sprite_0_s1.address
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output wire vga_sprite_0_s1_write, // .write
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input wire [31:0] vga_sprite_0_s1_readdata, // .readdata
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output wire [31:0] vga_sprite_0_s1_writedata, // .writedata
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output wire [3:0] vga_sprite_0_s1_byteenable, // .byteenable
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output wire vga_sprite_0_s1_chipselect, // .chipselect
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output wire vga_sprite_0_s1_clken, // .clken
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output wire [9:0] vga_sprite_1_s1_address, // vga_sprite_1_s1.address
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output wire vga_sprite_1_s1_write, // .write
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input wire [31:0] vga_sprite_1_s1_readdata, // .readdata
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output wire [31:0] vga_sprite_1_s1_writedata, // .writedata
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output wire [3:0] vga_sprite_1_s1_byteenable, // .byteenable
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output wire vga_sprite_1_s1_chipselect, // .chipselect
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output wire vga_sprite_1_s1_clken, // .clken
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output wire [9:0] vga_sprite_2_s1_address, // vga_sprite_2_s1.address
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output wire vga_sprite_2_s1_write, // .write
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input wire [31:0] vga_sprite_2_s1_readdata, // .readdata
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output wire [31:0] vga_sprite_2_s1_writedata, // .writedata
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output wire [3:0] vga_sprite_2_s1_byteenable, // .byteenable
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output wire vga_sprite_2_s1_chipselect, // .chipselect
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output wire vga_sprite_2_s1_clken, // .clken
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output wire [9:0] vga_sprite_3_s1_address, // vga_sprite_3_s1.address
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output wire vga_sprite_3_s1_write, // .write
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input wire [31:0] vga_sprite_3_s1_readdata, // .readdata
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output wire [31:0] vga_sprite_3_s1_writedata, // .writedata
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output wire [3:0] vga_sprite_3_s1_byteenable, // .byteenable
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output wire vga_sprite_3_s1_chipselect, // .chipselect
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output wire vga_sprite_3_s1_clken, // .clken
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output wire [9:0] vga_sprite_4_s1_address, // vga_sprite_4_s1.address
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output wire vga_sprite_4_s1_write, // .write
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input wire [31:0] vga_sprite_4_s1_readdata, // .readdata
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output wire [31:0] vga_sprite_4_s1_writedata, // .writedata
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output wire [3:0] vga_sprite_4_s1_byteenable, // .byteenable
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output wire vga_sprite_4_s1_chipselect, // .chipselect
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output wire vga_sprite_4_s1_clken, // .clken
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output wire [9:0] vga_sprite_5_s1_address, // vga_sprite_5_s1.address
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output wire vga_sprite_5_s1_write, // .write
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input wire [31:0] vga_sprite_5_s1_readdata, // .readdata
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output wire [31:0] vga_sprite_5_s1_writedata, // .writedata
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output wire [3:0] vga_sprite_5_s1_byteenable, // .byteenable
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output wire vga_sprite_5_s1_chipselect, // .chipselect
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output wire vga_sprite_5_s1_clken, // .clken
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output wire [9:0] vga_sprite_6_s1_address, // vga_sprite_6_s1.address
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output wire vga_sprite_6_s1_write, // .write
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input wire [31:0] vga_sprite_6_s1_readdata, // .readdata
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output wire [31:0] vga_sprite_6_s1_writedata, // .writedata
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output wire [3:0] vga_sprite_6_s1_byteenable, // .byteenable
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output wire vga_sprite_6_s1_chipselect, // .chipselect
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output wire vga_sprite_6_s1_clken, // .clken
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output wire [9:0] vga_sprite_7_s1_address, // vga_sprite_7_s1.address
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output wire vga_sprite_7_s1_write, // .write
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input wire [31:0] vga_sprite_7_s1_readdata, // .readdata
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output wire [31:0] vga_sprite_7_s1_writedata, // .writedata
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output wire [3:0] vga_sprite_7_s1_byteenable, // .byteenable
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output wire vga_sprite_7_s1_chipselect, // .chipselect
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output wire vga_sprite_7_s1_clken, // .clken
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output wire [7:0] vga_sprite_params_avl_address, // vga_sprite_params_avl.address
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output wire vga_sprite_params_avl_write, // .write
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output wire vga_sprite_params_avl_read, // .read
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input wire [31:0] vga_sprite_params_avl_readdata, // .readdata
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output wire [31:0] vga_sprite_params_avl_writedata // .writedata
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wire nios2_cpu_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_cpu_data_master_agent:av_waitrequest -> nios2_cpu_data_master_translator:uav_waitrequest
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wire [31:0] nios2_cpu_data_master_translator_avalon_universal_master_0_readdata; // nios2_cpu_data_master_agent:av_readdata -> nios2_cpu_data_master_translator:uav_readdata
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wire nios2_cpu_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_cpu_data_master_translator:uav_debugaccess -> nios2_cpu_data_master_agent:av_debugaccess
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wire [31:0] nios2_cpu_data_master_translator_avalon_universal_master_0_address; // nios2_cpu_data_master_translator:uav_address -> nios2_cpu_data_master_agent:av_address
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wire nios2_cpu_data_master_translator_avalon_universal_master_0_read; // nios2_cpu_data_master_translator:uav_read -> nios2_cpu_data_master_agent:av_read
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wire [3:0] nios2_cpu_data_master_translator_avalon_universal_master_0_byteenable; // nios2_cpu_data_master_translator:uav_byteenable -> nios2_cpu_data_master_agent:av_byteenable
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wire nios2_cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_cpu_data_master_agent:av_readdatavalid -> nios2_cpu_data_master_translator:uav_readdatavalid
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wire nios2_cpu_data_master_translator_avalon_universal_master_0_lock; // nios2_cpu_data_master_translator:uav_lock -> nios2_cpu_data_master_agent:av_lock
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wire nios2_cpu_data_master_translator_avalon_universal_master_0_write; // nios2_cpu_data_master_translator:uav_write -> nios2_cpu_data_master_agent:av_write
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wire [31:0] nios2_cpu_data_master_translator_avalon_universal_master_0_writedata; // nios2_cpu_data_master_translator:uav_writedata -> nios2_cpu_data_master_agent:av_writedata
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wire [2:0] nios2_cpu_data_master_translator_avalon_universal_master_0_burstcount; // nios2_cpu_data_master_translator:uav_burstcount -> nios2_cpu_data_master_agent:av_burstcount
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wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_cpu_data_master_agent:rp_valid
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wire [113:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_cpu_data_master_agent:rp_data
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wire rsp_mux_src_ready; // nios2_cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
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wire [33:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_cpu_data_master_agent:rp_channel
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wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_cpu_data_master_agent:rp_startofpacket
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wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_cpu_data_master_agent:rp_endofpacket
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wire nios2_dma_m_read_translator_avalon_universal_master_0_waitrequest; // nios2_dma_m_read_agent:av_waitrequest -> nios2_dma_m_read_translator:uav_waitrequest
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wire [31:0] nios2_dma_m_read_translator_avalon_universal_master_0_readdata; // nios2_dma_m_read_agent:av_readdata -> nios2_dma_m_read_translator:uav_readdata
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wire nios2_dma_m_read_translator_avalon_universal_master_0_debugaccess; // nios2_dma_m_read_translator:uav_debugaccess -> nios2_dma_m_read_agent:av_debugaccess
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wire [31:0] nios2_dma_m_read_translator_avalon_universal_master_0_address; // nios2_dma_m_read_translator:uav_address -> nios2_dma_m_read_agent:av_address
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wire nios2_dma_m_read_translator_avalon_universal_master_0_read; // nios2_dma_m_read_translator:uav_read -> nios2_dma_m_read_agent:av_read
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wire [3:0] nios2_dma_m_read_translator_avalon_universal_master_0_byteenable; // nios2_dma_m_read_translator:uav_byteenable -> nios2_dma_m_read_agent:av_byteenable
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wire nios2_dma_m_read_translator_avalon_universal_master_0_readdatavalid; // nios2_dma_m_read_agent:av_readdatavalid -> nios2_dma_m_read_translator:uav_readdatavalid
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wire nios2_dma_m_read_translator_avalon_universal_master_0_lock; // nios2_dma_m_read_translator:uav_lock -> nios2_dma_m_read_agent:av_lock
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wire nios2_dma_m_read_translator_avalon_universal_master_0_write; // nios2_dma_m_read_translator:uav_write -> nios2_dma_m_read_agent:av_write
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wire [31:0] nios2_dma_m_read_translator_avalon_universal_master_0_writedata; // nios2_dma_m_read_translator:uav_writedata -> nios2_dma_m_read_agent:av_writedata
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wire [2:0] nios2_dma_m_read_translator_avalon_universal_master_0_burstcount; // nios2_dma_m_read_translator:uav_burstcount -> nios2_dma_m_read_agent:av_burstcount
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wire nios2_dma_m_write_translator_avalon_universal_master_0_waitrequest; // nios2_dma_m_write_agent:av_waitrequest -> nios2_dma_m_write_translator:uav_waitrequest
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wire [31:0] nios2_dma_m_write_translator_avalon_universal_master_0_readdata; // nios2_dma_m_write_agent:av_readdata -> nios2_dma_m_write_translator:uav_readdata
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wire nios2_dma_m_write_translator_avalon_universal_master_0_debugaccess; // nios2_dma_m_write_translator:uav_debugaccess -> nios2_dma_m_write_agent:av_debugaccess
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wire [31:0] nios2_dma_m_write_translator_avalon_universal_master_0_address; // nios2_dma_m_write_translator:uav_address -> nios2_dma_m_write_agent:av_address
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wire nios2_dma_m_write_translator_avalon_universal_master_0_read; // nios2_dma_m_write_translator:uav_read -> nios2_dma_m_write_agent:av_read
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wire [3:0] nios2_dma_m_write_translator_avalon_universal_master_0_byteenable; // nios2_dma_m_write_translator:uav_byteenable -> nios2_dma_m_write_agent:av_byteenable
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wire nios2_dma_m_write_translator_avalon_universal_master_0_readdatavalid; // nios2_dma_m_write_agent:av_readdatavalid -> nios2_dma_m_write_translator:uav_readdatavalid
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wire nios2_dma_m_write_translator_avalon_universal_master_0_lock; // nios2_dma_m_write_translator:uav_lock -> nios2_dma_m_write_agent:av_lock
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wire nios2_dma_m_write_translator_avalon_universal_master_0_write; // nios2_dma_m_write_translator:uav_write -> nios2_dma_m_write_agent:av_write
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wire [31:0] nios2_dma_m_write_translator_avalon_universal_master_0_writedata; // nios2_dma_m_write_translator:uav_writedata -> nios2_dma_m_write_agent:av_writedata
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wire [2:0] nios2_dma_m_write_translator_avalon_universal_master_0_burstcount; // nios2_dma_m_write_translator:uav_burstcount -> nios2_dma_m_write_agent:av_burstcount
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wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> nios2_dma_m_write_agent:rp_valid
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wire [113:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> nios2_dma_m_write_agent:rp_data
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wire rsp_mux_002_src_ready; // nios2_dma_m_write_agent:rp_ready -> rsp_mux_002:src_ready
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wire [33:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> nios2_dma_m_write_agent:rp_channel
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wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> nios2_dma_m_write_agent:rp_startofpacket
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wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> nios2_dma_m_write_agent:rp_endofpacket
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wire nios2_cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_cpu_instruction_master_agent:av_waitrequest -> nios2_cpu_instruction_master_translator:uav_waitrequest
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wire [31:0] nios2_cpu_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_cpu_instruction_master_agent:av_readdata -> nios2_cpu_instruction_master_translator:uav_readdata
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wire nios2_cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_cpu_instruction_master_translator:uav_debugaccess -> nios2_cpu_instruction_master_agent:av_debugaccess
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wire [31:0] nios2_cpu_instruction_master_translator_avalon_universal_master_0_address; // nios2_cpu_instruction_master_translator:uav_address -> nios2_cpu_instruction_master_agent:av_address
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wire nios2_cpu_instruction_master_translator_avalon_universal_master_0_read; // nios2_cpu_instruction_master_translator:uav_read -> nios2_cpu_instruction_master_agent:av_read
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wire [3:0] nios2_cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_cpu_instruction_master_translator:uav_byteenable -> nios2_cpu_instruction_master_agent:av_byteenable
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wire nios2_cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_cpu_instruction_master_agent:av_readdatavalid -> nios2_cpu_instruction_master_translator:uav_readdatavalid
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wire nios2_cpu_instruction_master_translator_avalon_universal_master_0_lock; // nios2_cpu_instruction_master_translator:uav_lock -> nios2_cpu_instruction_master_agent:av_lock
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wire nios2_cpu_instruction_master_translator_avalon_universal_master_0_write; // nios2_cpu_instruction_master_translator:uav_write -> nios2_cpu_instruction_master_agent:av_write
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wire [31:0] nios2_cpu_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_cpu_instruction_master_translator:uav_writedata -> nios2_cpu_instruction_master_agent:av_writedata
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wire [2:0] nios2_cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_cpu_instruction_master_translator:uav_burstcount -> nios2_cpu_instruction_master_agent:av_burstcount
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wire rsp_mux_003_src_valid; // rsp_mux_003:src_valid -> nios2_cpu_instruction_master_agent:rp_valid
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wire [113:0] rsp_mux_003_src_data; // rsp_mux_003:src_data -> nios2_cpu_instruction_master_agent:rp_data
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wire rsp_mux_003_src_ready; // nios2_cpu_instruction_master_agent:rp_ready -> rsp_mux_003:src_ready
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wire [33:0] rsp_mux_003_src_channel; // rsp_mux_003:src_channel -> nios2_cpu_instruction_master_agent:rp_channel
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wire rsp_mux_003_src_startofpacket; // rsp_mux_003:src_startofpacket -> nios2_cpu_instruction_master_agent:rp_startofpacket
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wire rsp_mux_003_src_endofpacket; // rsp_mux_003:src_endofpacket -> nios2_cpu_instruction_master_agent:rp_endofpacket
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wire [31:0] nios2_jtag_uart_avalon_jtag_slave_agent_m0_readdata; // nios2_jtag_uart_avalon_jtag_slave_translator:uav_readdata -> nios2_jtag_uart_avalon_jtag_slave_agent:m0_readdata
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wire nios2_jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // nios2_jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> nios2_jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
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wire nios2_jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // nios2_jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> nios2_jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
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wire [31:0] nios2_jtag_uart_avalon_jtag_slave_agent_m0_address; // nios2_jtag_uart_avalon_jtag_slave_agent:m0_address -> nios2_jtag_uart_avalon_jtag_slave_translator:uav_address
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wire [3:0] nios2_jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // nios2_jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> nios2_jtag_uart_avalon_jtag_slave_translator:uav_byteenable
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wire nios2_jtag_uart_avalon_jtag_slave_agent_m0_read; // nios2_jtag_uart_avalon_jtag_slave_agent:m0_read -> nios2_jtag_uart_avalon_jtag_slave_translator:uav_read
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wire nios2_jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // nios2_jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> nios2_jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
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wire nios2_jtag_uart_avalon_jtag_slave_agent_m0_lock; // nios2_jtag_uart_avalon_jtag_slave_agent:m0_lock -> nios2_jtag_uart_avalon_jtag_slave_translator:uav_lock
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wire [31:0] nios2_jtag_uart_avalon_jtag_slave_agent_m0_writedata; // nios2_jtag_uart_avalon_jtag_slave_agent:m0_writedata -> nios2_jtag_uart_avalon_jtag_slave_translator:uav_writedata
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wire nios2_jtag_uart_avalon_jtag_slave_agent_m0_write; // nios2_jtag_uart_avalon_jtag_slave_agent:m0_write -> nios2_jtag_uart_avalon_jtag_slave_translator:uav_write
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wire [2:0] nios2_jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // nios2_jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> nios2_jtag_uart_avalon_jtag_slave_translator:uav_burstcount
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // nios2_jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
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wire [114:0] nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_data; // nios2_jtag_uart_avalon_jtag_slave_agent:rf_source_data -> nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> nios2_jtag_uart_avalon_jtag_slave_agent:rf_source_ready
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // nios2_jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // nios2_jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> nios2_jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
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wire [114:0] nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> nios2_jtag_uart_avalon_jtag_slave_agent:rf_sink_data
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // nios2_jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> nios2_jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> nios2_jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
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wire cmd_mux_src_valid; // cmd_mux:src_valid -> nios2_jtag_uart_avalon_jtag_slave_agent:cp_valid
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wire [113:0] cmd_mux_src_data; // cmd_mux:src_data -> nios2_jtag_uart_avalon_jtag_slave_agent:cp_data
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wire cmd_mux_src_ready; // nios2_jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
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wire [33:0] cmd_mux_src_channel; // cmd_mux:src_channel -> nios2_jtag_uart_avalon_jtag_slave_agent:cp_channel
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wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> nios2_jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
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wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> nios2_jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
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wire [31:0] eth1_mdio_avalon_slave_agent_m0_readdata; // eth1_mdio_avalon_slave_translator:uav_readdata -> eth1_mdio_avalon_slave_agent:m0_readdata
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wire eth1_mdio_avalon_slave_agent_m0_waitrequest; // eth1_mdio_avalon_slave_translator:uav_waitrequest -> eth1_mdio_avalon_slave_agent:m0_waitrequest
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wire eth1_mdio_avalon_slave_agent_m0_debugaccess; // eth1_mdio_avalon_slave_agent:m0_debugaccess -> eth1_mdio_avalon_slave_translator:uav_debugaccess
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wire [31:0] eth1_mdio_avalon_slave_agent_m0_address; // eth1_mdio_avalon_slave_agent:m0_address -> eth1_mdio_avalon_slave_translator:uav_address
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wire [3:0] eth1_mdio_avalon_slave_agent_m0_byteenable; // eth1_mdio_avalon_slave_agent:m0_byteenable -> eth1_mdio_avalon_slave_translator:uav_byteenable
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wire eth1_mdio_avalon_slave_agent_m0_read; // eth1_mdio_avalon_slave_agent:m0_read -> eth1_mdio_avalon_slave_translator:uav_read
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wire eth1_mdio_avalon_slave_agent_m0_readdatavalid; // eth1_mdio_avalon_slave_translator:uav_readdatavalid -> eth1_mdio_avalon_slave_agent:m0_readdatavalid
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wire eth1_mdio_avalon_slave_agent_m0_lock; // eth1_mdio_avalon_slave_agent:m0_lock -> eth1_mdio_avalon_slave_translator:uav_lock
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wire [31:0] eth1_mdio_avalon_slave_agent_m0_writedata; // eth1_mdio_avalon_slave_agent:m0_writedata -> eth1_mdio_avalon_slave_translator:uav_writedata
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wire eth1_mdio_avalon_slave_agent_m0_write; // eth1_mdio_avalon_slave_agent:m0_write -> eth1_mdio_avalon_slave_translator:uav_write
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wire [2:0] eth1_mdio_avalon_slave_agent_m0_burstcount; // eth1_mdio_avalon_slave_agent:m0_burstcount -> eth1_mdio_avalon_slave_translator:uav_burstcount
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wire eth1_mdio_avalon_slave_agent_rf_source_valid; // eth1_mdio_avalon_slave_agent:rf_source_valid -> eth1_mdio_avalon_slave_agent_rsp_fifo:in_valid
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wire [114:0] eth1_mdio_avalon_slave_agent_rf_source_data; // eth1_mdio_avalon_slave_agent:rf_source_data -> eth1_mdio_avalon_slave_agent_rsp_fifo:in_data
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wire eth1_mdio_avalon_slave_agent_rf_source_ready; // eth1_mdio_avalon_slave_agent_rsp_fifo:in_ready -> eth1_mdio_avalon_slave_agent:rf_source_ready
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wire eth1_mdio_avalon_slave_agent_rf_source_startofpacket; // eth1_mdio_avalon_slave_agent:rf_source_startofpacket -> eth1_mdio_avalon_slave_agent_rsp_fifo:in_startofpacket
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wire eth1_mdio_avalon_slave_agent_rf_source_endofpacket; // eth1_mdio_avalon_slave_agent:rf_source_endofpacket -> eth1_mdio_avalon_slave_agent_rsp_fifo:in_endofpacket
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wire eth1_mdio_avalon_slave_agent_rsp_fifo_out_valid; // eth1_mdio_avalon_slave_agent_rsp_fifo:out_valid -> eth1_mdio_avalon_slave_agent:rf_sink_valid
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wire [114:0] eth1_mdio_avalon_slave_agent_rsp_fifo_out_data; // eth1_mdio_avalon_slave_agent_rsp_fifo:out_data -> eth1_mdio_avalon_slave_agent:rf_sink_data
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wire eth1_mdio_avalon_slave_agent_rsp_fifo_out_ready; // eth1_mdio_avalon_slave_agent:rf_sink_ready -> eth1_mdio_avalon_slave_agent_rsp_fifo:out_ready
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wire eth1_mdio_avalon_slave_agent_rsp_fifo_out_startofpacket; // eth1_mdio_avalon_slave_agent_rsp_fifo:out_startofpacket -> eth1_mdio_avalon_slave_agent:rf_sink_startofpacket
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wire eth1_mdio_avalon_slave_agent_rsp_fifo_out_endofpacket; // eth1_mdio_avalon_slave_agent_rsp_fifo:out_endofpacket -> eth1_mdio_avalon_slave_agent:rf_sink_endofpacket
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wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> eth1_mdio_avalon_slave_agent:cp_valid
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wire [113:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> eth1_mdio_avalon_slave_agent:cp_data
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wire cmd_mux_001_src_ready; // eth1_mdio_avalon_slave_agent:cp_ready -> cmd_mux_001:src_ready
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wire [33:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> eth1_mdio_avalon_slave_agent:cp_channel
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wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> eth1_mdio_avalon_slave_agent:cp_startofpacket
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wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> eth1_mdio_avalon_slave_agent:cp_endofpacket
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wire [31:0] eth0_mdio_avalon_slave_agent_m0_readdata; // eth0_mdio_avalon_slave_translator:uav_readdata -> eth0_mdio_avalon_slave_agent:m0_readdata
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wire eth0_mdio_avalon_slave_agent_m0_waitrequest; // eth0_mdio_avalon_slave_translator:uav_waitrequest -> eth0_mdio_avalon_slave_agent:m0_waitrequest
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wire eth0_mdio_avalon_slave_agent_m0_debugaccess; // eth0_mdio_avalon_slave_agent:m0_debugaccess -> eth0_mdio_avalon_slave_translator:uav_debugaccess
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wire [31:0] eth0_mdio_avalon_slave_agent_m0_address; // eth0_mdio_avalon_slave_agent:m0_address -> eth0_mdio_avalon_slave_translator:uav_address
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wire [3:0] eth0_mdio_avalon_slave_agent_m0_byteenable; // eth0_mdio_avalon_slave_agent:m0_byteenable -> eth0_mdio_avalon_slave_translator:uav_byteenable
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wire eth0_mdio_avalon_slave_agent_m0_read; // eth0_mdio_avalon_slave_agent:m0_read -> eth0_mdio_avalon_slave_translator:uav_read
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wire eth0_mdio_avalon_slave_agent_m0_readdatavalid; // eth0_mdio_avalon_slave_translator:uav_readdatavalid -> eth0_mdio_avalon_slave_agent:m0_readdatavalid
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wire eth0_mdio_avalon_slave_agent_m0_lock; // eth0_mdio_avalon_slave_agent:m0_lock -> eth0_mdio_avalon_slave_translator:uav_lock
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wire [31:0] eth0_mdio_avalon_slave_agent_m0_writedata; // eth0_mdio_avalon_slave_agent:m0_writedata -> eth0_mdio_avalon_slave_translator:uav_writedata
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wire eth0_mdio_avalon_slave_agent_m0_write; // eth0_mdio_avalon_slave_agent:m0_write -> eth0_mdio_avalon_slave_translator:uav_write
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wire [2:0] eth0_mdio_avalon_slave_agent_m0_burstcount; // eth0_mdio_avalon_slave_agent:m0_burstcount -> eth0_mdio_avalon_slave_translator:uav_burstcount
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wire eth0_mdio_avalon_slave_agent_rf_source_valid; // eth0_mdio_avalon_slave_agent:rf_source_valid -> eth0_mdio_avalon_slave_agent_rsp_fifo:in_valid
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wire [114:0] eth0_mdio_avalon_slave_agent_rf_source_data; // eth0_mdio_avalon_slave_agent:rf_source_data -> eth0_mdio_avalon_slave_agent_rsp_fifo:in_data
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wire eth0_mdio_avalon_slave_agent_rf_source_ready; // eth0_mdio_avalon_slave_agent_rsp_fifo:in_ready -> eth0_mdio_avalon_slave_agent:rf_source_ready
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wire eth0_mdio_avalon_slave_agent_rf_source_startofpacket; // eth0_mdio_avalon_slave_agent:rf_source_startofpacket -> eth0_mdio_avalon_slave_agent_rsp_fifo:in_startofpacket
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wire eth0_mdio_avalon_slave_agent_rf_source_endofpacket; // eth0_mdio_avalon_slave_agent:rf_source_endofpacket -> eth0_mdio_avalon_slave_agent_rsp_fifo:in_endofpacket
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wire eth0_mdio_avalon_slave_agent_rsp_fifo_out_valid; // eth0_mdio_avalon_slave_agent_rsp_fifo:out_valid -> eth0_mdio_avalon_slave_agent:rf_sink_valid
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wire [114:0] eth0_mdio_avalon_slave_agent_rsp_fifo_out_data; // eth0_mdio_avalon_slave_agent_rsp_fifo:out_data -> eth0_mdio_avalon_slave_agent:rf_sink_data
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wire eth0_mdio_avalon_slave_agent_rsp_fifo_out_ready; // eth0_mdio_avalon_slave_agent:rf_sink_ready -> eth0_mdio_avalon_slave_agent_rsp_fifo:out_ready
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wire eth0_mdio_avalon_slave_agent_rsp_fifo_out_startofpacket; // eth0_mdio_avalon_slave_agent_rsp_fifo:out_startofpacket -> eth0_mdio_avalon_slave_agent:rf_sink_startofpacket
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wire eth0_mdio_avalon_slave_agent_rsp_fifo_out_endofpacket; // eth0_mdio_avalon_slave_agent_rsp_fifo:out_endofpacket -> eth0_mdio_avalon_slave_agent:rf_sink_endofpacket
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wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> eth0_mdio_avalon_slave_agent:cp_valid
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wire [113:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> eth0_mdio_avalon_slave_agent:cp_data
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wire cmd_mux_002_src_ready; // eth0_mdio_avalon_slave_agent:cp_ready -> cmd_mux_002:src_ready
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wire [33:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> eth0_mdio_avalon_slave_agent:cp_channel
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wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> eth0_mdio_avalon_slave_agent:cp_startofpacket
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wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> eth0_mdio_avalon_slave_agent:cp_endofpacket
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wire [15:0] sram_multiplexer_avl_agent_m0_readdata; // sram_multiplexer_avl_translator:uav_readdata -> sram_multiplexer_avl_agent:m0_readdata
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wire sram_multiplexer_avl_agent_m0_waitrequest; // sram_multiplexer_avl_translator:uav_waitrequest -> sram_multiplexer_avl_agent:m0_waitrequest
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wire sram_multiplexer_avl_agent_m0_debugaccess; // sram_multiplexer_avl_agent:m0_debugaccess -> sram_multiplexer_avl_translator:uav_debugaccess
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wire [31:0] sram_multiplexer_avl_agent_m0_address; // sram_multiplexer_avl_agent:m0_address -> sram_multiplexer_avl_translator:uav_address
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wire [1:0] sram_multiplexer_avl_agent_m0_byteenable; // sram_multiplexer_avl_agent:m0_byteenable -> sram_multiplexer_avl_translator:uav_byteenable
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wire sram_multiplexer_avl_agent_m0_read; // sram_multiplexer_avl_agent:m0_read -> sram_multiplexer_avl_translator:uav_read
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wire sram_multiplexer_avl_agent_m0_readdatavalid; // sram_multiplexer_avl_translator:uav_readdatavalid -> sram_multiplexer_avl_agent:m0_readdatavalid
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wire sram_multiplexer_avl_agent_m0_lock; // sram_multiplexer_avl_agent:m0_lock -> sram_multiplexer_avl_translator:uav_lock
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wire [15:0] sram_multiplexer_avl_agent_m0_writedata; // sram_multiplexer_avl_agent:m0_writedata -> sram_multiplexer_avl_translator:uav_writedata
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wire sram_multiplexer_avl_agent_m0_write; // sram_multiplexer_avl_agent:m0_write -> sram_multiplexer_avl_translator:uav_write
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wire [1:0] sram_multiplexer_avl_agent_m0_burstcount; // sram_multiplexer_avl_agent:m0_burstcount -> sram_multiplexer_avl_translator:uav_burstcount
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wire sram_multiplexer_avl_agent_rf_source_valid; // sram_multiplexer_avl_agent:rf_source_valid -> sram_multiplexer_avl_agent_rsp_fifo:in_valid
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wire [96:0] sram_multiplexer_avl_agent_rf_source_data; // sram_multiplexer_avl_agent:rf_source_data -> sram_multiplexer_avl_agent_rsp_fifo:in_data
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wire sram_multiplexer_avl_agent_rf_source_ready; // sram_multiplexer_avl_agent_rsp_fifo:in_ready -> sram_multiplexer_avl_agent:rf_source_ready
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wire sram_multiplexer_avl_agent_rf_source_startofpacket; // sram_multiplexer_avl_agent:rf_source_startofpacket -> sram_multiplexer_avl_agent_rsp_fifo:in_startofpacket
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wire sram_multiplexer_avl_agent_rf_source_endofpacket; // sram_multiplexer_avl_agent:rf_source_endofpacket -> sram_multiplexer_avl_agent_rsp_fifo:in_endofpacket
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wire sram_multiplexer_avl_agent_rsp_fifo_out_valid; // sram_multiplexer_avl_agent_rsp_fifo:out_valid -> sram_multiplexer_avl_agent:rf_sink_valid
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wire [96:0] sram_multiplexer_avl_agent_rsp_fifo_out_data; // sram_multiplexer_avl_agent_rsp_fifo:out_data -> sram_multiplexer_avl_agent:rf_sink_data
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wire sram_multiplexer_avl_agent_rsp_fifo_out_ready; // sram_multiplexer_avl_agent:rf_sink_ready -> sram_multiplexer_avl_agent_rsp_fifo:out_ready
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wire sram_multiplexer_avl_agent_rsp_fifo_out_startofpacket; // sram_multiplexer_avl_agent_rsp_fifo:out_startofpacket -> sram_multiplexer_avl_agent:rf_sink_startofpacket
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wire sram_multiplexer_avl_agent_rsp_fifo_out_endofpacket; // sram_multiplexer_avl_agent_rsp_fifo:out_endofpacket -> sram_multiplexer_avl_agent:rf_sink_endofpacket
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wire [31:0] vga_sprite_params_avl_agent_m0_readdata; // vga_sprite_params_avl_translator:uav_readdata -> vga_sprite_params_avl_agent:m0_readdata
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wire vga_sprite_params_avl_agent_m0_waitrequest; // vga_sprite_params_avl_translator:uav_waitrequest -> vga_sprite_params_avl_agent:m0_waitrequest
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wire vga_sprite_params_avl_agent_m0_debugaccess; // vga_sprite_params_avl_agent:m0_debugaccess -> vga_sprite_params_avl_translator:uav_debugaccess
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wire [31:0] vga_sprite_params_avl_agent_m0_address; // vga_sprite_params_avl_agent:m0_address -> vga_sprite_params_avl_translator:uav_address
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wire [3:0] vga_sprite_params_avl_agent_m0_byteenable; // vga_sprite_params_avl_agent:m0_byteenable -> vga_sprite_params_avl_translator:uav_byteenable
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wire vga_sprite_params_avl_agent_m0_read; // vga_sprite_params_avl_agent:m0_read -> vga_sprite_params_avl_translator:uav_read
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wire vga_sprite_params_avl_agent_m0_readdatavalid; // vga_sprite_params_avl_translator:uav_readdatavalid -> vga_sprite_params_avl_agent:m0_readdatavalid
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wire vga_sprite_params_avl_agent_m0_lock; // vga_sprite_params_avl_agent:m0_lock -> vga_sprite_params_avl_translator:uav_lock
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wire [31:0] vga_sprite_params_avl_agent_m0_writedata; // vga_sprite_params_avl_agent:m0_writedata -> vga_sprite_params_avl_translator:uav_writedata
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wire vga_sprite_params_avl_agent_m0_write; // vga_sprite_params_avl_agent:m0_write -> vga_sprite_params_avl_translator:uav_write
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wire [2:0] vga_sprite_params_avl_agent_m0_burstcount; // vga_sprite_params_avl_agent:m0_burstcount -> vga_sprite_params_avl_translator:uav_burstcount
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wire vga_sprite_params_avl_agent_rf_source_valid; // vga_sprite_params_avl_agent:rf_source_valid -> vga_sprite_params_avl_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_params_avl_agent_rf_source_data; // vga_sprite_params_avl_agent:rf_source_data -> vga_sprite_params_avl_agent_rsp_fifo:in_data
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wire vga_sprite_params_avl_agent_rf_source_ready; // vga_sprite_params_avl_agent_rsp_fifo:in_ready -> vga_sprite_params_avl_agent:rf_source_ready
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wire vga_sprite_params_avl_agent_rf_source_startofpacket; // vga_sprite_params_avl_agent:rf_source_startofpacket -> vga_sprite_params_avl_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_params_avl_agent_rf_source_endofpacket; // vga_sprite_params_avl_agent:rf_source_endofpacket -> vga_sprite_params_avl_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_params_avl_agent_rsp_fifo_out_valid; // vga_sprite_params_avl_agent_rsp_fifo:out_valid -> vga_sprite_params_avl_agent:rf_sink_valid
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wire [114:0] vga_sprite_params_avl_agent_rsp_fifo_out_data; // vga_sprite_params_avl_agent_rsp_fifo:out_data -> vga_sprite_params_avl_agent:rf_sink_data
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wire vga_sprite_params_avl_agent_rsp_fifo_out_ready; // vga_sprite_params_avl_agent:rf_sink_ready -> vga_sprite_params_avl_agent_rsp_fifo:out_ready
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wire vga_sprite_params_avl_agent_rsp_fifo_out_startofpacket; // vga_sprite_params_avl_agent_rsp_fifo:out_startofpacket -> vga_sprite_params_avl_agent:rf_sink_startofpacket
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wire vga_sprite_params_avl_agent_rsp_fifo_out_endofpacket; // vga_sprite_params_avl_agent_rsp_fifo:out_endofpacket -> vga_sprite_params_avl_agent:rf_sink_endofpacket
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wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> vga_sprite_params_avl_agent:cp_valid
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wire [113:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> vga_sprite_params_avl_agent:cp_data
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wire cmd_mux_004_src_ready; // vga_sprite_params_avl_agent:cp_ready -> cmd_mux_004:src_ready
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wire [33:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> vga_sprite_params_avl_agent:cp_channel
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wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> vga_sprite_params_avl_agent:cp_startofpacket
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wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> vga_sprite_params_avl_agent:cp_endofpacket
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wire [31:0] nios2_sysid_control_slave_agent_m0_readdata; // nios2_sysid_control_slave_translator:uav_readdata -> nios2_sysid_control_slave_agent:m0_readdata
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wire nios2_sysid_control_slave_agent_m0_waitrequest; // nios2_sysid_control_slave_translator:uav_waitrequest -> nios2_sysid_control_slave_agent:m0_waitrequest
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wire nios2_sysid_control_slave_agent_m0_debugaccess; // nios2_sysid_control_slave_agent:m0_debugaccess -> nios2_sysid_control_slave_translator:uav_debugaccess
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wire [31:0] nios2_sysid_control_slave_agent_m0_address; // nios2_sysid_control_slave_agent:m0_address -> nios2_sysid_control_slave_translator:uav_address
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wire [3:0] nios2_sysid_control_slave_agent_m0_byteenable; // nios2_sysid_control_slave_agent:m0_byteenable -> nios2_sysid_control_slave_translator:uav_byteenable
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wire nios2_sysid_control_slave_agent_m0_read; // nios2_sysid_control_slave_agent:m0_read -> nios2_sysid_control_slave_translator:uav_read
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wire nios2_sysid_control_slave_agent_m0_readdatavalid; // nios2_sysid_control_slave_translator:uav_readdatavalid -> nios2_sysid_control_slave_agent:m0_readdatavalid
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wire nios2_sysid_control_slave_agent_m0_lock; // nios2_sysid_control_slave_agent:m0_lock -> nios2_sysid_control_slave_translator:uav_lock
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wire [31:0] nios2_sysid_control_slave_agent_m0_writedata; // nios2_sysid_control_slave_agent:m0_writedata -> nios2_sysid_control_slave_translator:uav_writedata
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wire nios2_sysid_control_slave_agent_m0_write; // nios2_sysid_control_slave_agent:m0_write -> nios2_sysid_control_slave_translator:uav_write
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wire [2:0] nios2_sysid_control_slave_agent_m0_burstcount; // nios2_sysid_control_slave_agent:m0_burstcount -> nios2_sysid_control_slave_translator:uav_burstcount
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wire nios2_sysid_control_slave_agent_rf_source_valid; // nios2_sysid_control_slave_agent:rf_source_valid -> nios2_sysid_control_slave_agent_rsp_fifo:in_valid
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wire [114:0] nios2_sysid_control_slave_agent_rf_source_data; // nios2_sysid_control_slave_agent:rf_source_data -> nios2_sysid_control_slave_agent_rsp_fifo:in_data
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wire nios2_sysid_control_slave_agent_rf_source_ready; // nios2_sysid_control_slave_agent_rsp_fifo:in_ready -> nios2_sysid_control_slave_agent:rf_source_ready
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wire nios2_sysid_control_slave_agent_rf_source_startofpacket; // nios2_sysid_control_slave_agent:rf_source_startofpacket -> nios2_sysid_control_slave_agent_rsp_fifo:in_startofpacket
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wire nios2_sysid_control_slave_agent_rf_source_endofpacket; // nios2_sysid_control_slave_agent:rf_source_endofpacket -> nios2_sysid_control_slave_agent_rsp_fifo:in_endofpacket
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wire nios2_sysid_control_slave_agent_rsp_fifo_out_valid; // nios2_sysid_control_slave_agent_rsp_fifo:out_valid -> nios2_sysid_control_slave_agent:rf_sink_valid
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wire [114:0] nios2_sysid_control_slave_agent_rsp_fifo_out_data; // nios2_sysid_control_slave_agent_rsp_fifo:out_data -> nios2_sysid_control_slave_agent:rf_sink_data
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wire nios2_sysid_control_slave_agent_rsp_fifo_out_ready; // nios2_sysid_control_slave_agent:rf_sink_ready -> nios2_sysid_control_slave_agent_rsp_fifo:out_ready
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wire nios2_sysid_control_slave_agent_rsp_fifo_out_startofpacket; // nios2_sysid_control_slave_agent_rsp_fifo:out_startofpacket -> nios2_sysid_control_slave_agent:rf_sink_startofpacket
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wire nios2_sysid_control_slave_agent_rsp_fifo_out_endofpacket; // nios2_sysid_control_slave_agent_rsp_fifo:out_endofpacket -> nios2_sysid_control_slave_agent:rf_sink_endofpacket
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wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> nios2_sysid_control_slave_agent:cp_valid
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wire [113:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> nios2_sysid_control_slave_agent:cp_data
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wire cmd_mux_005_src_ready; // nios2_sysid_control_slave_agent:cp_ready -> cmd_mux_005:src_ready
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wire [33:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> nios2_sysid_control_slave_agent:cp_channel
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wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> nios2_sysid_control_slave_agent:cp_startofpacket
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wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> nios2_sysid_control_slave_agent:cp_endofpacket
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wire [31:0] eth0_rx_dma_csr_agent_m0_readdata; // eth0_rx_dma_csr_translator:uav_readdata -> eth0_rx_dma_csr_agent:m0_readdata
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wire eth0_rx_dma_csr_agent_m0_waitrequest; // eth0_rx_dma_csr_translator:uav_waitrequest -> eth0_rx_dma_csr_agent:m0_waitrequest
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wire eth0_rx_dma_csr_agent_m0_debugaccess; // eth0_rx_dma_csr_agent:m0_debugaccess -> eth0_rx_dma_csr_translator:uav_debugaccess
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wire [31:0] eth0_rx_dma_csr_agent_m0_address; // eth0_rx_dma_csr_agent:m0_address -> eth0_rx_dma_csr_translator:uav_address
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wire [3:0] eth0_rx_dma_csr_agent_m0_byteenable; // eth0_rx_dma_csr_agent:m0_byteenable -> eth0_rx_dma_csr_translator:uav_byteenable
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wire eth0_rx_dma_csr_agent_m0_read; // eth0_rx_dma_csr_agent:m0_read -> eth0_rx_dma_csr_translator:uav_read
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wire eth0_rx_dma_csr_agent_m0_readdatavalid; // eth0_rx_dma_csr_translator:uav_readdatavalid -> eth0_rx_dma_csr_agent:m0_readdatavalid
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wire eth0_rx_dma_csr_agent_m0_lock; // eth0_rx_dma_csr_agent:m0_lock -> eth0_rx_dma_csr_translator:uav_lock
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wire [31:0] eth0_rx_dma_csr_agent_m0_writedata; // eth0_rx_dma_csr_agent:m0_writedata -> eth0_rx_dma_csr_translator:uav_writedata
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wire eth0_rx_dma_csr_agent_m0_write; // eth0_rx_dma_csr_agent:m0_write -> eth0_rx_dma_csr_translator:uav_write
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wire [2:0] eth0_rx_dma_csr_agent_m0_burstcount; // eth0_rx_dma_csr_agent:m0_burstcount -> eth0_rx_dma_csr_translator:uav_burstcount
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wire eth0_rx_dma_csr_agent_rf_source_valid; // eth0_rx_dma_csr_agent:rf_source_valid -> eth0_rx_dma_csr_agent_rsp_fifo:in_valid
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wire [114:0] eth0_rx_dma_csr_agent_rf_source_data; // eth0_rx_dma_csr_agent:rf_source_data -> eth0_rx_dma_csr_agent_rsp_fifo:in_data
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wire eth0_rx_dma_csr_agent_rf_source_ready; // eth0_rx_dma_csr_agent_rsp_fifo:in_ready -> eth0_rx_dma_csr_agent:rf_source_ready
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wire eth0_rx_dma_csr_agent_rf_source_startofpacket; // eth0_rx_dma_csr_agent:rf_source_startofpacket -> eth0_rx_dma_csr_agent_rsp_fifo:in_startofpacket
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wire eth0_rx_dma_csr_agent_rf_source_endofpacket; // eth0_rx_dma_csr_agent:rf_source_endofpacket -> eth0_rx_dma_csr_agent_rsp_fifo:in_endofpacket
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wire eth0_rx_dma_csr_agent_rsp_fifo_out_valid; // eth0_rx_dma_csr_agent_rsp_fifo:out_valid -> eth0_rx_dma_csr_agent:rf_sink_valid
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wire [114:0] eth0_rx_dma_csr_agent_rsp_fifo_out_data; // eth0_rx_dma_csr_agent_rsp_fifo:out_data -> eth0_rx_dma_csr_agent:rf_sink_data
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wire eth0_rx_dma_csr_agent_rsp_fifo_out_ready; // eth0_rx_dma_csr_agent:rf_sink_ready -> eth0_rx_dma_csr_agent_rsp_fifo:out_ready
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wire eth0_rx_dma_csr_agent_rsp_fifo_out_startofpacket; // eth0_rx_dma_csr_agent_rsp_fifo:out_startofpacket -> eth0_rx_dma_csr_agent:rf_sink_startofpacket
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wire eth0_rx_dma_csr_agent_rsp_fifo_out_endofpacket; // eth0_rx_dma_csr_agent_rsp_fifo:out_endofpacket -> eth0_rx_dma_csr_agent:rf_sink_endofpacket
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wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> eth0_rx_dma_csr_agent:cp_valid
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wire [113:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> eth0_rx_dma_csr_agent:cp_data
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wire cmd_mux_006_src_ready; // eth0_rx_dma_csr_agent:cp_ready -> cmd_mux_006:src_ready
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wire [33:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> eth0_rx_dma_csr_agent:cp_channel
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wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> eth0_rx_dma_csr_agent:cp_startofpacket
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wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> eth0_rx_dma_csr_agent:cp_endofpacket
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wire [31:0] eth0_tx_dma_csr_agent_m0_readdata; // eth0_tx_dma_csr_translator:uav_readdata -> eth0_tx_dma_csr_agent:m0_readdata
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wire eth0_tx_dma_csr_agent_m0_waitrequest; // eth0_tx_dma_csr_translator:uav_waitrequest -> eth0_tx_dma_csr_agent:m0_waitrequest
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wire eth0_tx_dma_csr_agent_m0_debugaccess; // eth0_tx_dma_csr_agent:m0_debugaccess -> eth0_tx_dma_csr_translator:uav_debugaccess
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wire [31:0] eth0_tx_dma_csr_agent_m0_address; // eth0_tx_dma_csr_agent:m0_address -> eth0_tx_dma_csr_translator:uav_address
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wire [3:0] eth0_tx_dma_csr_agent_m0_byteenable; // eth0_tx_dma_csr_agent:m0_byteenable -> eth0_tx_dma_csr_translator:uav_byteenable
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wire eth0_tx_dma_csr_agent_m0_read; // eth0_tx_dma_csr_agent:m0_read -> eth0_tx_dma_csr_translator:uav_read
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wire eth0_tx_dma_csr_agent_m0_readdatavalid; // eth0_tx_dma_csr_translator:uav_readdatavalid -> eth0_tx_dma_csr_agent:m0_readdatavalid
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wire eth0_tx_dma_csr_agent_m0_lock; // eth0_tx_dma_csr_agent:m0_lock -> eth0_tx_dma_csr_translator:uav_lock
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wire [31:0] eth0_tx_dma_csr_agent_m0_writedata; // eth0_tx_dma_csr_agent:m0_writedata -> eth0_tx_dma_csr_translator:uav_writedata
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wire eth0_tx_dma_csr_agent_m0_write; // eth0_tx_dma_csr_agent:m0_write -> eth0_tx_dma_csr_translator:uav_write
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wire [2:0] eth0_tx_dma_csr_agent_m0_burstcount; // eth0_tx_dma_csr_agent:m0_burstcount -> eth0_tx_dma_csr_translator:uav_burstcount
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wire eth0_tx_dma_csr_agent_rf_source_valid; // eth0_tx_dma_csr_agent:rf_source_valid -> eth0_tx_dma_csr_agent_rsp_fifo:in_valid
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wire [114:0] eth0_tx_dma_csr_agent_rf_source_data; // eth0_tx_dma_csr_agent:rf_source_data -> eth0_tx_dma_csr_agent_rsp_fifo:in_data
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wire eth0_tx_dma_csr_agent_rf_source_ready; // eth0_tx_dma_csr_agent_rsp_fifo:in_ready -> eth0_tx_dma_csr_agent:rf_source_ready
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wire eth0_tx_dma_csr_agent_rf_source_startofpacket; // eth0_tx_dma_csr_agent:rf_source_startofpacket -> eth0_tx_dma_csr_agent_rsp_fifo:in_startofpacket
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wire eth0_tx_dma_csr_agent_rf_source_endofpacket; // eth0_tx_dma_csr_agent:rf_source_endofpacket -> eth0_tx_dma_csr_agent_rsp_fifo:in_endofpacket
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wire eth0_tx_dma_csr_agent_rsp_fifo_out_valid; // eth0_tx_dma_csr_agent_rsp_fifo:out_valid -> eth0_tx_dma_csr_agent:rf_sink_valid
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wire [114:0] eth0_tx_dma_csr_agent_rsp_fifo_out_data; // eth0_tx_dma_csr_agent_rsp_fifo:out_data -> eth0_tx_dma_csr_agent:rf_sink_data
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wire eth0_tx_dma_csr_agent_rsp_fifo_out_ready; // eth0_tx_dma_csr_agent:rf_sink_ready -> eth0_tx_dma_csr_agent_rsp_fifo:out_ready
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wire eth0_tx_dma_csr_agent_rsp_fifo_out_startofpacket; // eth0_tx_dma_csr_agent_rsp_fifo:out_startofpacket -> eth0_tx_dma_csr_agent:rf_sink_startofpacket
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wire eth0_tx_dma_csr_agent_rsp_fifo_out_endofpacket; // eth0_tx_dma_csr_agent_rsp_fifo:out_endofpacket -> eth0_tx_dma_csr_agent:rf_sink_endofpacket
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wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> eth0_tx_dma_csr_agent:cp_valid
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wire [113:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> eth0_tx_dma_csr_agent:cp_data
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wire cmd_mux_007_src_ready; // eth0_tx_dma_csr_agent:cp_ready -> cmd_mux_007:src_ready
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wire [33:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> eth0_tx_dma_csr_agent:cp_channel
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wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> eth0_tx_dma_csr_agent:cp_startofpacket
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wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> eth0_tx_dma_csr_agent:cp_endofpacket
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wire [31:0] eth1_rx_dma_csr_agent_m0_readdata; // eth1_rx_dma_csr_translator:uav_readdata -> eth1_rx_dma_csr_agent:m0_readdata
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wire eth1_rx_dma_csr_agent_m0_waitrequest; // eth1_rx_dma_csr_translator:uav_waitrequest -> eth1_rx_dma_csr_agent:m0_waitrequest
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wire eth1_rx_dma_csr_agent_m0_debugaccess; // eth1_rx_dma_csr_agent:m0_debugaccess -> eth1_rx_dma_csr_translator:uav_debugaccess
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wire [31:0] eth1_rx_dma_csr_agent_m0_address; // eth1_rx_dma_csr_agent:m0_address -> eth1_rx_dma_csr_translator:uav_address
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wire [3:0] eth1_rx_dma_csr_agent_m0_byteenable; // eth1_rx_dma_csr_agent:m0_byteenable -> eth1_rx_dma_csr_translator:uav_byteenable
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wire eth1_rx_dma_csr_agent_m0_read; // eth1_rx_dma_csr_agent:m0_read -> eth1_rx_dma_csr_translator:uav_read
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wire eth1_rx_dma_csr_agent_m0_readdatavalid; // eth1_rx_dma_csr_translator:uav_readdatavalid -> eth1_rx_dma_csr_agent:m0_readdatavalid
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wire eth1_rx_dma_csr_agent_m0_lock; // eth1_rx_dma_csr_agent:m0_lock -> eth1_rx_dma_csr_translator:uav_lock
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wire [31:0] eth1_rx_dma_csr_agent_m0_writedata; // eth1_rx_dma_csr_agent:m0_writedata -> eth1_rx_dma_csr_translator:uav_writedata
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wire eth1_rx_dma_csr_agent_m0_write; // eth1_rx_dma_csr_agent:m0_write -> eth1_rx_dma_csr_translator:uav_write
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wire [2:0] eth1_rx_dma_csr_agent_m0_burstcount; // eth1_rx_dma_csr_agent:m0_burstcount -> eth1_rx_dma_csr_translator:uav_burstcount
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wire eth1_rx_dma_csr_agent_rf_source_valid; // eth1_rx_dma_csr_agent:rf_source_valid -> eth1_rx_dma_csr_agent_rsp_fifo:in_valid
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wire [114:0] eth1_rx_dma_csr_agent_rf_source_data; // eth1_rx_dma_csr_agent:rf_source_data -> eth1_rx_dma_csr_agent_rsp_fifo:in_data
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wire eth1_rx_dma_csr_agent_rf_source_ready; // eth1_rx_dma_csr_agent_rsp_fifo:in_ready -> eth1_rx_dma_csr_agent:rf_source_ready
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wire eth1_rx_dma_csr_agent_rf_source_startofpacket; // eth1_rx_dma_csr_agent:rf_source_startofpacket -> eth1_rx_dma_csr_agent_rsp_fifo:in_startofpacket
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wire eth1_rx_dma_csr_agent_rf_source_endofpacket; // eth1_rx_dma_csr_agent:rf_source_endofpacket -> eth1_rx_dma_csr_agent_rsp_fifo:in_endofpacket
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wire eth1_rx_dma_csr_agent_rsp_fifo_out_valid; // eth1_rx_dma_csr_agent_rsp_fifo:out_valid -> eth1_rx_dma_csr_agent:rf_sink_valid
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wire [114:0] eth1_rx_dma_csr_agent_rsp_fifo_out_data; // eth1_rx_dma_csr_agent_rsp_fifo:out_data -> eth1_rx_dma_csr_agent:rf_sink_data
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wire eth1_rx_dma_csr_agent_rsp_fifo_out_ready; // eth1_rx_dma_csr_agent:rf_sink_ready -> eth1_rx_dma_csr_agent_rsp_fifo:out_ready
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wire eth1_rx_dma_csr_agent_rsp_fifo_out_startofpacket; // eth1_rx_dma_csr_agent_rsp_fifo:out_startofpacket -> eth1_rx_dma_csr_agent:rf_sink_startofpacket
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wire eth1_rx_dma_csr_agent_rsp_fifo_out_endofpacket; // eth1_rx_dma_csr_agent_rsp_fifo:out_endofpacket -> eth1_rx_dma_csr_agent:rf_sink_endofpacket
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wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> eth1_rx_dma_csr_agent:cp_valid
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wire [113:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> eth1_rx_dma_csr_agent:cp_data
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wire cmd_mux_008_src_ready; // eth1_rx_dma_csr_agent:cp_ready -> cmd_mux_008:src_ready
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wire [33:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> eth1_rx_dma_csr_agent:cp_channel
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wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> eth1_rx_dma_csr_agent:cp_startofpacket
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wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> eth1_rx_dma_csr_agent:cp_endofpacket
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wire [31:0] eth1_tx_dma_csr_agent_m0_readdata; // eth1_tx_dma_csr_translator:uav_readdata -> eth1_tx_dma_csr_agent:m0_readdata
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wire eth1_tx_dma_csr_agent_m0_waitrequest; // eth1_tx_dma_csr_translator:uav_waitrequest -> eth1_tx_dma_csr_agent:m0_waitrequest
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wire eth1_tx_dma_csr_agent_m0_debugaccess; // eth1_tx_dma_csr_agent:m0_debugaccess -> eth1_tx_dma_csr_translator:uav_debugaccess
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wire [31:0] eth1_tx_dma_csr_agent_m0_address; // eth1_tx_dma_csr_agent:m0_address -> eth1_tx_dma_csr_translator:uav_address
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wire [3:0] eth1_tx_dma_csr_agent_m0_byteenable; // eth1_tx_dma_csr_agent:m0_byteenable -> eth1_tx_dma_csr_translator:uav_byteenable
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wire eth1_tx_dma_csr_agent_m0_read; // eth1_tx_dma_csr_agent:m0_read -> eth1_tx_dma_csr_translator:uav_read
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wire eth1_tx_dma_csr_agent_m0_readdatavalid; // eth1_tx_dma_csr_translator:uav_readdatavalid -> eth1_tx_dma_csr_agent:m0_readdatavalid
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wire eth1_tx_dma_csr_agent_m0_lock; // eth1_tx_dma_csr_agent:m0_lock -> eth1_tx_dma_csr_translator:uav_lock
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wire [31:0] eth1_tx_dma_csr_agent_m0_writedata; // eth1_tx_dma_csr_agent:m0_writedata -> eth1_tx_dma_csr_translator:uav_writedata
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wire eth1_tx_dma_csr_agent_m0_write; // eth1_tx_dma_csr_agent:m0_write -> eth1_tx_dma_csr_translator:uav_write
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wire [2:0] eth1_tx_dma_csr_agent_m0_burstcount; // eth1_tx_dma_csr_agent:m0_burstcount -> eth1_tx_dma_csr_translator:uav_burstcount
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wire eth1_tx_dma_csr_agent_rf_source_valid; // eth1_tx_dma_csr_agent:rf_source_valid -> eth1_tx_dma_csr_agent_rsp_fifo:in_valid
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wire [114:0] eth1_tx_dma_csr_agent_rf_source_data; // eth1_tx_dma_csr_agent:rf_source_data -> eth1_tx_dma_csr_agent_rsp_fifo:in_data
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wire eth1_tx_dma_csr_agent_rf_source_ready; // eth1_tx_dma_csr_agent_rsp_fifo:in_ready -> eth1_tx_dma_csr_agent:rf_source_ready
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wire eth1_tx_dma_csr_agent_rf_source_startofpacket; // eth1_tx_dma_csr_agent:rf_source_startofpacket -> eth1_tx_dma_csr_agent_rsp_fifo:in_startofpacket
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wire eth1_tx_dma_csr_agent_rf_source_endofpacket; // eth1_tx_dma_csr_agent:rf_source_endofpacket -> eth1_tx_dma_csr_agent_rsp_fifo:in_endofpacket
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wire eth1_tx_dma_csr_agent_rsp_fifo_out_valid; // eth1_tx_dma_csr_agent_rsp_fifo:out_valid -> eth1_tx_dma_csr_agent:rf_sink_valid
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wire [114:0] eth1_tx_dma_csr_agent_rsp_fifo_out_data; // eth1_tx_dma_csr_agent_rsp_fifo:out_data -> eth1_tx_dma_csr_agent:rf_sink_data
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wire eth1_tx_dma_csr_agent_rsp_fifo_out_ready; // eth1_tx_dma_csr_agent:rf_sink_ready -> eth1_tx_dma_csr_agent_rsp_fifo:out_ready
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wire eth1_tx_dma_csr_agent_rsp_fifo_out_startofpacket; // eth1_tx_dma_csr_agent_rsp_fifo:out_startofpacket -> eth1_tx_dma_csr_agent:rf_sink_startofpacket
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wire eth1_tx_dma_csr_agent_rsp_fifo_out_endofpacket; // eth1_tx_dma_csr_agent_rsp_fifo:out_endofpacket -> eth1_tx_dma_csr_agent:rf_sink_endofpacket
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wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> eth1_tx_dma_csr_agent:cp_valid
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wire [113:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> eth1_tx_dma_csr_agent:cp_data
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wire cmd_mux_009_src_ready; // eth1_tx_dma_csr_agent:cp_ready -> cmd_mux_009:src_ready
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wire [33:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> eth1_tx_dma_csr_agent:cp_channel
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wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> eth1_tx_dma_csr_agent:cp_startofpacket
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wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> eth1_tx_dma_csr_agent:cp_endofpacket
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wire [31:0] nios2_dma_csr_agent_m0_readdata; // nios2_dma_csr_translator:uav_readdata -> nios2_dma_csr_agent:m0_readdata
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wire nios2_dma_csr_agent_m0_waitrequest; // nios2_dma_csr_translator:uav_waitrequest -> nios2_dma_csr_agent:m0_waitrequest
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wire nios2_dma_csr_agent_m0_debugaccess; // nios2_dma_csr_agent:m0_debugaccess -> nios2_dma_csr_translator:uav_debugaccess
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wire [31:0] nios2_dma_csr_agent_m0_address; // nios2_dma_csr_agent:m0_address -> nios2_dma_csr_translator:uav_address
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wire [3:0] nios2_dma_csr_agent_m0_byteenable; // nios2_dma_csr_agent:m0_byteenable -> nios2_dma_csr_translator:uav_byteenable
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wire nios2_dma_csr_agent_m0_read; // nios2_dma_csr_agent:m0_read -> nios2_dma_csr_translator:uav_read
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wire nios2_dma_csr_agent_m0_readdatavalid; // nios2_dma_csr_translator:uav_readdatavalid -> nios2_dma_csr_agent:m0_readdatavalid
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wire nios2_dma_csr_agent_m0_lock; // nios2_dma_csr_agent:m0_lock -> nios2_dma_csr_translator:uav_lock
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wire [31:0] nios2_dma_csr_agent_m0_writedata; // nios2_dma_csr_agent:m0_writedata -> nios2_dma_csr_translator:uav_writedata
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wire nios2_dma_csr_agent_m0_write; // nios2_dma_csr_agent:m0_write -> nios2_dma_csr_translator:uav_write
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wire [2:0] nios2_dma_csr_agent_m0_burstcount; // nios2_dma_csr_agent:m0_burstcount -> nios2_dma_csr_translator:uav_burstcount
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wire nios2_dma_csr_agent_rf_source_valid; // nios2_dma_csr_agent:rf_source_valid -> nios2_dma_csr_agent_rsp_fifo:in_valid
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wire [114:0] nios2_dma_csr_agent_rf_source_data; // nios2_dma_csr_agent:rf_source_data -> nios2_dma_csr_agent_rsp_fifo:in_data
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wire nios2_dma_csr_agent_rf_source_ready; // nios2_dma_csr_agent_rsp_fifo:in_ready -> nios2_dma_csr_agent:rf_source_ready
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wire nios2_dma_csr_agent_rf_source_startofpacket; // nios2_dma_csr_agent:rf_source_startofpacket -> nios2_dma_csr_agent_rsp_fifo:in_startofpacket
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wire nios2_dma_csr_agent_rf_source_endofpacket; // nios2_dma_csr_agent:rf_source_endofpacket -> nios2_dma_csr_agent_rsp_fifo:in_endofpacket
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wire nios2_dma_csr_agent_rsp_fifo_out_valid; // nios2_dma_csr_agent_rsp_fifo:out_valid -> nios2_dma_csr_agent:rf_sink_valid
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wire [114:0] nios2_dma_csr_agent_rsp_fifo_out_data; // nios2_dma_csr_agent_rsp_fifo:out_data -> nios2_dma_csr_agent:rf_sink_data
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wire nios2_dma_csr_agent_rsp_fifo_out_ready; // nios2_dma_csr_agent:rf_sink_ready -> nios2_dma_csr_agent_rsp_fifo:out_ready
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wire nios2_dma_csr_agent_rsp_fifo_out_startofpacket; // nios2_dma_csr_agent_rsp_fifo:out_startofpacket -> nios2_dma_csr_agent:rf_sink_startofpacket
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wire nios2_dma_csr_agent_rsp_fifo_out_endofpacket; // nios2_dma_csr_agent_rsp_fifo:out_endofpacket -> nios2_dma_csr_agent:rf_sink_endofpacket
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wire cmd_mux_010_src_valid; // cmd_mux_010:src_valid -> nios2_dma_csr_agent:cp_valid
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wire [113:0] cmd_mux_010_src_data; // cmd_mux_010:src_data -> nios2_dma_csr_agent:cp_data
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wire cmd_mux_010_src_ready; // nios2_dma_csr_agent:cp_ready -> cmd_mux_010:src_ready
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wire [33:0] cmd_mux_010_src_channel; // cmd_mux_010:src_channel -> nios2_dma_csr_agent:cp_channel
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wire cmd_mux_010_src_startofpacket; // cmd_mux_010:src_startofpacket -> nios2_dma_csr_agent:cp_startofpacket
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wire cmd_mux_010_src_endofpacket; // cmd_mux_010:src_endofpacket -> nios2_dma_csr_agent:cp_endofpacket
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wire [31:0] nios2_cpu_debug_mem_slave_agent_m0_readdata; // nios2_cpu_debug_mem_slave_translator:uav_readdata -> nios2_cpu_debug_mem_slave_agent:m0_readdata
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wire nios2_cpu_debug_mem_slave_agent_m0_waitrequest; // nios2_cpu_debug_mem_slave_translator:uav_waitrequest -> nios2_cpu_debug_mem_slave_agent:m0_waitrequest
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wire nios2_cpu_debug_mem_slave_agent_m0_debugaccess; // nios2_cpu_debug_mem_slave_agent:m0_debugaccess -> nios2_cpu_debug_mem_slave_translator:uav_debugaccess
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wire [31:0] nios2_cpu_debug_mem_slave_agent_m0_address; // nios2_cpu_debug_mem_slave_agent:m0_address -> nios2_cpu_debug_mem_slave_translator:uav_address
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wire [3:0] nios2_cpu_debug_mem_slave_agent_m0_byteenable; // nios2_cpu_debug_mem_slave_agent:m0_byteenable -> nios2_cpu_debug_mem_slave_translator:uav_byteenable
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wire nios2_cpu_debug_mem_slave_agent_m0_read; // nios2_cpu_debug_mem_slave_agent:m0_read -> nios2_cpu_debug_mem_slave_translator:uav_read
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wire nios2_cpu_debug_mem_slave_agent_m0_readdatavalid; // nios2_cpu_debug_mem_slave_translator:uav_readdatavalid -> nios2_cpu_debug_mem_slave_agent:m0_readdatavalid
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wire nios2_cpu_debug_mem_slave_agent_m0_lock; // nios2_cpu_debug_mem_slave_agent:m0_lock -> nios2_cpu_debug_mem_slave_translator:uav_lock
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wire [31:0] nios2_cpu_debug_mem_slave_agent_m0_writedata; // nios2_cpu_debug_mem_slave_agent:m0_writedata -> nios2_cpu_debug_mem_slave_translator:uav_writedata
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wire nios2_cpu_debug_mem_slave_agent_m0_write; // nios2_cpu_debug_mem_slave_agent:m0_write -> nios2_cpu_debug_mem_slave_translator:uav_write
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wire [2:0] nios2_cpu_debug_mem_slave_agent_m0_burstcount; // nios2_cpu_debug_mem_slave_agent:m0_burstcount -> nios2_cpu_debug_mem_slave_translator:uav_burstcount
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wire nios2_cpu_debug_mem_slave_agent_rf_source_valid; // nios2_cpu_debug_mem_slave_agent:rf_source_valid -> nios2_cpu_debug_mem_slave_agent_rsp_fifo:in_valid
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wire [114:0] nios2_cpu_debug_mem_slave_agent_rf_source_data; // nios2_cpu_debug_mem_slave_agent:rf_source_data -> nios2_cpu_debug_mem_slave_agent_rsp_fifo:in_data
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wire nios2_cpu_debug_mem_slave_agent_rf_source_ready; // nios2_cpu_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_cpu_debug_mem_slave_agent:rf_source_ready
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wire nios2_cpu_debug_mem_slave_agent_rf_source_startofpacket; // nios2_cpu_debug_mem_slave_agent:rf_source_startofpacket -> nios2_cpu_debug_mem_slave_agent_rsp_fifo:in_startofpacket
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wire nios2_cpu_debug_mem_slave_agent_rf_source_endofpacket; // nios2_cpu_debug_mem_slave_agent:rf_source_endofpacket -> nios2_cpu_debug_mem_slave_agent_rsp_fifo:in_endofpacket
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wire nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_cpu_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_cpu_debug_mem_slave_agent:rf_sink_valid
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wire [114:0] nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_cpu_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_cpu_debug_mem_slave_agent:rf_sink_data
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wire nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_cpu_debug_mem_slave_agent:rf_sink_ready -> nios2_cpu_debug_mem_slave_agent_rsp_fifo:out_ready
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wire nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_cpu_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_cpu_debug_mem_slave_agent:rf_sink_startofpacket
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wire nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_cpu_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_cpu_debug_mem_slave_agent:rf_sink_endofpacket
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wire cmd_mux_011_src_valid; // cmd_mux_011:src_valid -> nios2_cpu_debug_mem_slave_agent:cp_valid
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wire [113:0] cmd_mux_011_src_data; // cmd_mux_011:src_data -> nios2_cpu_debug_mem_slave_agent:cp_data
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wire cmd_mux_011_src_ready; // nios2_cpu_debug_mem_slave_agent:cp_ready -> cmd_mux_011:src_ready
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wire [33:0] cmd_mux_011_src_channel; // cmd_mux_011:src_channel -> nios2_cpu_debug_mem_slave_agent:cp_channel
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wire cmd_mux_011_src_startofpacket; // cmd_mux_011:src_startofpacket -> nios2_cpu_debug_mem_slave_agent:cp_startofpacket
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wire cmd_mux_011_src_endofpacket; // cmd_mux_011:src_endofpacket -> nios2_cpu_debug_mem_slave_agent:cp_endofpacket
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wire [31:0] nios2_pll_pll_slave_agent_m0_readdata; // nios2_pll_pll_slave_translator:uav_readdata -> nios2_pll_pll_slave_agent:m0_readdata
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wire nios2_pll_pll_slave_agent_m0_waitrequest; // nios2_pll_pll_slave_translator:uav_waitrequest -> nios2_pll_pll_slave_agent:m0_waitrequest
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wire nios2_pll_pll_slave_agent_m0_debugaccess; // nios2_pll_pll_slave_agent:m0_debugaccess -> nios2_pll_pll_slave_translator:uav_debugaccess
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wire [31:0] nios2_pll_pll_slave_agent_m0_address; // nios2_pll_pll_slave_agent:m0_address -> nios2_pll_pll_slave_translator:uav_address
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wire [3:0] nios2_pll_pll_slave_agent_m0_byteenable; // nios2_pll_pll_slave_agent:m0_byteenable -> nios2_pll_pll_slave_translator:uav_byteenable
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wire nios2_pll_pll_slave_agent_m0_read; // nios2_pll_pll_slave_agent:m0_read -> nios2_pll_pll_slave_translator:uav_read
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wire nios2_pll_pll_slave_agent_m0_readdatavalid; // nios2_pll_pll_slave_translator:uav_readdatavalid -> nios2_pll_pll_slave_agent:m0_readdatavalid
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wire nios2_pll_pll_slave_agent_m0_lock; // nios2_pll_pll_slave_agent:m0_lock -> nios2_pll_pll_slave_translator:uav_lock
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wire [31:0] nios2_pll_pll_slave_agent_m0_writedata; // nios2_pll_pll_slave_agent:m0_writedata -> nios2_pll_pll_slave_translator:uav_writedata
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wire nios2_pll_pll_slave_agent_m0_write; // nios2_pll_pll_slave_agent:m0_write -> nios2_pll_pll_slave_translator:uav_write
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wire [2:0] nios2_pll_pll_slave_agent_m0_burstcount; // nios2_pll_pll_slave_agent:m0_burstcount -> nios2_pll_pll_slave_translator:uav_burstcount
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wire nios2_pll_pll_slave_agent_rf_source_valid; // nios2_pll_pll_slave_agent:rf_source_valid -> nios2_pll_pll_slave_agent_rsp_fifo:in_valid
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wire [114:0] nios2_pll_pll_slave_agent_rf_source_data; // nios2_pll_pll_slave_agent:rf_source_data -> nios2_pll_pll_slave_agent_rsp_fifo:in_data
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wire nios2_pll_pll_slave_agent_rf_source_ready; // nios2_pll_pll_slave_agent_rsp_fifo:in_ready -> nios2_pll_pll_slave_agent:rf_source_ready
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wire nios2_pll_pll_slave_agent_rf_source_startofpacket; // nios2_pll_pll_slave_agent:rf_source_startofpacket -> nios2_pll_pll_slave_agent_rsp_fifo:in_startofpacket
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wire nios2_pll_pll_slave_agent_rf_source_endofpacket; // nios2_pll_pll_slave_agent:rf_source_endofpacket -> nios2_pll_pll_slave_agent_rsp_fifo:in_endofpacket
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wire nios2_pll_pll_slave_agent_rsp_fifo_out_valid; // nios2_pll_pll_slave_agent_rsp_fifo:out_valid -> nios2_pll_pll_slave_agent:rf_sink_valid
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wire [114:0] nios2_pll_pll_slave_agent_rsp_fifo_out_data; // nios2_pll_pll_slave_agent_rsp_fifo:out_data -> nios2_pll_pll_slave_agent:rf_sink_data
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wire nios2_pll_pll_slave_agent_rsp_fifo_out_ready; // nios2_pll_pll_slave_agent:rf_sink_ready -> nios2_pll_pll_slave_agent_rsp_fifo:out_ready
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wire nios2_pll_pll_slave_agent_rsp_fifo_out_startofpacket; // nios2_pll_pll_slave_agent_rsp_fifo:out_startofpacket -> nios2_pll_pll_slave_agent:rf_sink_startofpacket
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wire nios2_pll_pll_slave_agent_rsp_fifo_out_endofpacket; // nios2_pll_pll_slave_agent_rsp_fifo:out_endofpacket -> nios2_pll_pll_slave_agent:rf_sink_endofpacket
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wire cmd_mux_012_src_valid; // cmd_mux_012:src_valid -> nios2_pll_pll_slave_agent:cp_valid
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wire [113:0] cmd_mux_012_src_data; // cmd_mux_012:src_data -> nios2_pll_pll_slave_agent:cp_data
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wire cmd_mux_012_src_ready; // nios2_pll_pll_slave_agent:cp_ready -> cmd_mux_012:src_ready
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wire [33:0] cmd_mux_012_src_channel; // cmd_mux_012:src_channel -> nios2_pll_pll_slave_agent:cp_channel
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wire cmd_mux_012_src_startofpacket; // cmd_mux_012:src_startofpacket -> nios2_pll_pll_slave_agent:cp_startofpacket
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wire cmd_mux_012_src_endofpacket; // cmd_mux_012:src_endofpacket -> nios2_pll_pll_slave_agent:cp_endofpacket
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wire [31:0] nios2_onchip_mem_s1_agent_m0_readdata; // nios2_onchip_mem_s1_translator:uav_readdata -> nios2_onchip_mem_s1_agent:m0_readdata
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wire nios2_onchip_mem_s1_agent_m0_waitrequest; // nios2_onchip_mem_s1_translator:uav_waitrequest -> nios2_onchip_mem_s1_agent:m0_waitrequest
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wire nios2_onchip_mem_s1_agent_m0_debugaccess; // nios2_onchip_mem_s1_agent:m0_debugaccess -> nios2_onchip_mem_s1_translator:uav_debugaccess
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wire [31:0] nios2_onchip_mem_s1_agent_m0_address; // nios2_onchip_mem_s1_agent:m0_address -> nios2_onchip_mem_s1_translator:uav_address
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wire [3:0] nios2_onchip_mem_s1_agent_m0_byteenable; // nios2_onchip_mem_s1_agent:m0_byteenable -> nios2_onchip_mem_s1_translator:uav_byteenable
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wire nios2_onchip_mem_s1_agent_m0_read; // nios2_onchip_mem_s1_agent:m0_read -> nios2_onchip_mem_s1_translator:uav_read
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wire nios2_onchip_mem_s1_agent_m0_readdatavalid; // nios2_onchip_mem_s1_translator:uav_readdatavalid -> nios2_onchip_mem_s1_agent:m0_readdatavalid
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wire nios2_onchip_mem_s1_agent_m0_lock; // nios2_onchip_mem_s1_agent:m0_lock -> nios2_onchip_mem_s1_translator:uav_lock
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wire [31:0] nios2_onchip_mem_s1_agent_m0_writedata; // nios2_onchip_mem_s1_agent:m0_writedata -> nios2_onchip_mem_s1_translator:uav_writedata
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wire nios2_onchip_mem_s1_agent_m0_write; // nios2_onchip_mem_s1_agent:m0_write -> nios2_onchip_mem_s1_translator:uav_write
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wire [2:0] nios2_onchip_mem_s1_agent_m0_burstcount; // nios2_onchip_mem_s1_agent:m0_burstcount -> nios2_onchip_mem_s1_translator:uav_burstcount
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wire nios2_onchip_mem_s1_agent_rf_source_valid; // nios2_onchip_mem_s1_agent:rf_source_valid -> nios2_onchip_mem_s1_agent_rsp_fifo:in_valid
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wire [114:0] nios2_onchip_mem_s1_agent_rf_source_data; // nios2_onchip_mem_s1_agent:rf_source_data -> nios2_onchip_mem_s1_agent_rsp_fifo:in_data
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wire nios2_onchip_mem_s1_agent_rf_source_ready; // nios2_onchip_mem_s1_agent_rsp_fifo:in_ready -> nios2_onchip_mem_s1_agent:rf_source_ready
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wire nios2_onchip_mem_s1_agent_rf_source_startofpacket; // nios2_onchip_mem_s1_agent:rf_source_startofpacket -> nios2_onchip_mem_s1_agent_rsp_fifo:in_startofpacket
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wire nios2_onchip_mem_s1_agent_rf_source_endofpacket; // nios2_onchip_mem_s1_agent:rf_source_endofpacket -> nios2_onchip_mem_s1_agent_rsp_fifo:in_endofpacket
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wire nios2_onchip_mem_s1_agent_rsp_fifo_out_valid; // nios2_onchip_mem_s1_agent_rsp_fifo:out_valid -> nios2_onchip_mem_s1_agent:rf_sink_valid
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wire [114:0] nios2_onchip_mem_s1_agent_rsp_fifo_out_data; // nios2_onchip_mem_s1_agent_rsp_fifo:out_data -> nios2_onchip_mem_s1_agent:rf_sink_data
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wire nios2_onchip_mem_s1_agent_rsp_fifo_out_ready; // nios2_onchip_mem_s1_agent:rf_sink_ready -> nios2_onchip_mem_s1_agent_rsp_fifo:out_ready
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wire nios2_onchip_mem_s1_agent_rsp_fifo_out_startofpacket; // nios2_onchip_mem_s1_agent_rsp_fifo:out_startofpacket -> nios2_onchip_mem_s1_agent:rf_sink_startofpacket
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wire nios2_onchip_mem_s1_agent_rsp_fifo_out_endofpacket; // nios2_onchip_mem_s1_agent_rsp_fifo:out_endofpacket -> nios2_onchip_mem_s1_agent:rf_sink_endofpacket
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wire cmd_mux_013_src_valid; // cmd_mux_013:src_valid -> nios2_onchip_mem_s1_agent:cp_valid
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wire [113:0] cmd_mux_013_src_data; // cmd_mux_013:src_data -> nios2_onchip_mem_s1_agent:cp_data
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wire cmd_mux_013_src_ready; // nios2_onchip_mem_s1_agent:cp_ready -> cmd_mux_013:src_ready
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wire [33:0] cmd_mux_013_src_channel; // cmd_mux_013:src_channel -> nios2_onchip_mem_s1_agent:cp_channel
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wire cmd_mux_013_src_startofpacket; // cmd_mux_013:src_startofpacket -> nios2_onchip_mem_s1_agent:cp_startofpacket
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wire cmd_mux_013_src_endofpacket; // cmd_mux_013:src_endofpacket -> nios2_onchip_mem_s1_agent:cp_endofpacket
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wire [31:0] sdram_s1_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
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wire sdram_s1_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
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wire sdram_s1_agent_m0_debugaccess; // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
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wire [31:0] sdram_s1_agent_m0_address; // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
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wire [3:0] sdram_s1_agent_m0_byteenable; // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
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wire sdram_s1_agent_m0_read; // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
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wire sdram_s1_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
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wire sdram_s1_agent_m0_lock; // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
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wire [31:0] sdram_s1_agent_m0_writedata; // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
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wire sdram_s1_agent_m0_write; // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
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wire [2:0] sdram_s1_agent_m0_burstcount; // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
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wire sdram_s1_agent_rf_source_valid; // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
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wire [114:0] sdram_s1_agent_rf_source_data; // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
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wire sdram_s1_agent_rf_source_ready; // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
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wire sdram_s1_agent_rf_source_startofpacket; // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
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wire sdram_s1_agent_rf_source_endofpacket; // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
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wire sdram_s1_agent_rsp_fifo_out_valid; // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
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wire [114:0] sdram_s1_agent_rsp_fifo_out_data; // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
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wire sdram_s1_agent_rsp_fifo_out_ready; // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
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wire sdram_s1_agent_rsp_fifo_out_startofpacket; // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
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wire sdram_s1_agent_rsp_fifo_out_endofpacket; // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
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wire cmd_mux_014_src_valid; // cmd_mux_014:src_valid -> sdram_s1_agent:cp_valid
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wire [113:0] cmd_mux_014_src_data; // cmd_mux_014:src_data -> sdram_s1_agent:cp_data
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wire cmd_mux_014_src_ready; // sdram_s1_agent:cp_ready -> cmd_mux_014:src_ready
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wire [33:0] cmd_mux_014_src_channel; // cmd_mux_014:src_channel -> sdram_s1_agent:cp_channel
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wire cmd_mux_014_src_startofpacket; // cmd_mux_014:src_startofpacket -> sdram_s1_agent:cp_startofpacket
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wire cmd_mux_014_src_endofpacket; // cmd_mux_014:src_endofpacket -> sdram_s1_agent:cp_endofpacket
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wire [31:0] io_led_red_s1_agent_m0_readdata; // io_led_red_s1_translator:uav_readdata -> io_led_red_s1_agent:m0_readdata
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wire io_led_red_s1_agent_m0_waitrequest; // io_led_red_s1_translator:uav_waitrequest -> io_led_red_s1_agent:m0_waitrequest
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wire io_led_red_s1_agent_m0_debugaccess; // io_led_red_s1_agent:m0_debugaccess -> io_led_red_s1_translator:uav_debugaccess
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wire [31:0] io_led_red_s1_agent_m0_address; // io_led_red_s1_agent:m0_address -> io_led_red_s1_translator:uav_address
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wire [3:0] io_led_red_s1_agent_m0_byteenable; // io_led_red_s1_agent:m0_byteenable -> io_led_red_s1_translator:uav_byteenable
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wire io_led_red_s1_agent_m0_read; // io_led_red_s1_agent:m0_read -> io_led_red_s1_translator:uav_read
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wire io_led_red_s1_agent_m0_readdatavalid; // io_led_red_s1_translator:uav_readdatavalid -> io_led_red_s1_agent:m0_readdatavalid
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wire io_led_red_s1_agent_m0_lock; // io_led_red_s1_agent:m0_lock -> io_led_red_s1_translator:uav_lock
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wire [31:0] io_led_red_s1_agent_m0_writedata; // io_led_red_s1_agent:m0_writedata -> io_led_red_s1_translator:uav_writedata
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wire io_led_red_s1_agent_m0_write; // io_led_red_s1_agent:m0_write -> io_led_red_s1_translator:uav_write
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wire [2:0] io_led_red_s1_agent_m0_burstcount; // io_led_red_s1_agent:m0_burstcount -> io_led_red_s1_translator:uav_burstcount
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wire io_led_red_s1_agent_rf_source_valid; // io_led_red_s1_agent:rf_source_valid -> io_led_red_s1_agent_rsp_fifo:in_valid
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wire [114:0] io_led_red_s1_agent_rf_source_data; // io_led_red_s1_agent:rf_source_data -> io_led_red_s1_agent_rsp_fifo:in_data
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wire io_led_red_s1_agent_rf_source_ready; // io_led_red_s1_agent_rsp_fifo:in_ready -> io_led_red_s1_agent:rf_source_ready
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wire io_led_red_s1_agent_rf_source_startofpacket; // io_led_red_s1_agent:rf_source_startofpacket -> io_led_red_s1_agent_rsp_fifo:in_startofpacket
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wire io_led_red_s1_agent_rf_source_endofpacket; // io_led_red_s1_agent:rf_source_endofpacket -> io_led_red_s1_agent_rsp_fifo:in_endofpacket
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wire io_led_red_s1_agent_rsp_fifo_out_valid; // io_led_red_s1_agent_rsp_fifo:out_valid -> io_led_red_s1_agent:rf_sink_valid
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wire [114:0] io_led_red_s1_agent_rsp_fifo_out_data; // io_led_red_s1_agent_rsp_fifo:out_data -> io_led_red_s1_agent:rf_sink_data
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wire io_led_red_s1_agent_rsp_fifo_out_ready; // io_led_red_s1_agent:rf_sink_ready -> io_led_red_s1_agent_rsp_fifo:out_ready
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wire io_led_red_s1_agent_rsp_fifo_out_startofpacket; // io_led_red_s1_agent_rsp_fifo:out_startofpacket -> io_led_red_s1_agent:rf_sink_startofpacket
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wire io_led_red_s1_agent_rsp_fifo_out_endofpacket; // io_led_red_s1_agent_rsp_fifo:out_endofpacket -> io_led_red_s1_agent:rf_sink_endofpacket
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wire cmd_mux_015_src_valid; // cmd_mux_015:src_valid -> io_led_red_s1_agent:cp_valid
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wire [113:0] cmd_mux_015_src_data; // cmd_mux_015:src_data -> io_led_red_s1_agent:cp_data
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wire cmd_mux_015_src_ready; // io_led_red_s1_agent:cp_ready -> cmd_mux_015:src_ready
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wire [33:0] cmd_mux_015_src_channel; // cmd_mux_015:src_channel -> io_led_red_s1_agent:cp_channel
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wire cmd_mux_015_src_startofpacket; // cmd_mux_015:src_startofpacket -> io_led_red_s1_agent:cp_startofpacket
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wire cmd_mux_015_src_endofpacket; // cmd_mux_015:src_endofpacket -> io_led_red_s1_agent:cp_endofpacket
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wire [31:0] nios2_timer_s1_agent_m0_readdata; // nios2_timer_s1_translator:uav_readdata -> nios2_timer_s1_agent:m0_readdata
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wire nios2_timer_s1_agent_m0_waitrequest; // nios2_timer_s1_translator:uav_waitrequest -> nios2_timer_s1_agent:m0_waitrequest
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wire nios2_timer_s1_agent_m0_debugaccess; // nios2_timer_s1_agent:m0_debugaccess -> nios2_timer_s1_translator:uav_debugaccess
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wire [31:0] nios2_timer_s1_agent_m0_address; // nios2_timer_s1_agent:m0_address -> nios2_timer_s1_translator:uav_address
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wire [3:0] nios2_timer_s1_agent_m0_byteenable; // nios2_timer_s1_agent:m0_byteenable -> nios2_timer_s1_translator:uav_byteenable
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wire nios2_timer_s1_agent_m0_read; // nios2_timer_s1_agent:m0_read -> nios2_timer_s1_translator:uav_read
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wire nios2_timer_s1_agent_m0_readdatavalid; // nios2_timer_s1_translator:uav_readdatavalid -> nios2_timer_s1_agent:m0_readdatavalid
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wire nios2_timer_s1_agent_m0_lock; // nios2_timer_s1_agent:m0_lock -> nios2_timer_s1_translator:uav_lock
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wire [31:0] nios2_timer_s1_agent_m0_writedata; // nios2_timer_s1_agent:m0_writedata -> nios2_timer_s1_translator:uav_writedata
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wire nios2_timer_s1_agent_m0_write; // nios2_timer_s1_agent:m0_write -> nios2_timer_s1_translator:uav_write
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wire [2:0] nios2_timer_s1_agent_m0_burstcount; // nios2_timer_s1_agent:m0_burstcount -> nios2_timer_s1_translator:uav_burstcount
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wire nios2_timer_s1_agent_rf_source_valid; // nios2_timer_s1_agent:rf_source_valid -> nios2_timer_s1_agent_rsp_fifo:in_valid
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wire [114:0] nios2_timer_s1_agent_rf_source_data; // nios2_timer_s1_agent:rf_source_data -> nios2_timer_s1_agent_rsp_fifo:in_data
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wire nios2_timer_s1_agent_rf_source_ready; // nios2_timer_s1_agent_rsp_fifo:in_ready -> nios2_timer_s1_agent:rf_source_ready
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wire nios2_timer_s1_agent_rf_source_startofpacket; // nios2_timer_s1_agent:rf_source_startofpacket -> nios2_timer_s1_agent_rsp_fifo:in_startofpacket
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wire nios2_timer_s1_agent_rf_source_endofpacket; // nios2_timer_s1_agent:rf_source_endofpacket -> nios2_timer_s1_agent_rsp_fifo:in_endofpacket
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wire nios2_timer_s1_agent_rsp_fifo_out_valid; // nios2_timer_s1_agent_rsp_fifo:out_valid -> nios2_timer_s1_agent:rf_sink_valid
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wire [114:0] nios2_timer_s1_agent_rsp_fifo_out_data; // nios2_timer_s1_agent_rsp_fifo:out_data -> nios2_timer_s1_agent:rf_sink_data
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wire nios2_timer_s1_agent_rsp_fifo_out_ready; // nios2_timer_s1_agent:rf_sink_ready -> nios2_timer_s1_agent_rsp_fifo:out_ready
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wire nios2_timer_s1_agent_rsp_fifo_out_startofpacket; // nios2_timer_s1_agent_rsp_fifo:out_startofpacket -> nios2_timer_s1_agent:rf_sink_startofpacket
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wire nios2_timer_s1_agent_rsp_fifo_out_endofpacket; // nios2_timer_s1_agent_rsp_fifo:out_endofpacket -> nios2_timer_s1_agent:rf_sink_endofpacket
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wire cmd_mux_016_src_valid; // cmd_mux_016:src_valid -> nios2_timer_s1_agent:cp_valid
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wire [113:0] cmd_mux_016_src_data; // cmd_mux_016:src_data -> nios2_timer_s1_agent:cp_data
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wire cmd_mux_016_src_ready; // nios2_timer_s1_agent:cp_ready -> cmd_mux_016:src_ready
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wire [33:0] cmd_mux_016_src_channel; // cmd_mux_016:src_channel -> nios2_timer_s1_agent:cp_channel
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wire cmd_mux_016_src_startofpacket; // cmd_mux_016:src_startofpacket -> nios2_timer_s1_agent:cp_startofpacket
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wire cmd_mux_016_src_endofpacket; // cmd_mux_016:src_endofpacket -> nios2_timer_s1_agent:cp_endofpacket
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wire [31:0] io_keys_s1_agent_m0_readdata; // io_keys_s1_translator:uav_readdata -> io_keys_s1_agent:m0_readdata
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wire io_keys_s1_agent_m0_waitrequest; // io_keys_s1_translator:uav_waitrequest -> io_keys_s1_agent:m0_waitrequest
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wire io_keys_s1_agent_m0_debugaccess; // io_keys_s1_agent:m0_debugaccess -> io_keys_s1_translator:uav_debugaccess
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wire [31:0] io_keys_s1_agent_m0_address; // io_keys_s1_agent:m0_address -> io_keys_s1_translator:uav_address
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wire [3:0] io_keys_s1_agent_m0_byteenable; // io_keys_s1_agent:m0_byteenable -> io_keys_s1_translator:uav_byteenable
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wire io_keys_s1_agent_m0_read; // io_keys_s1_agent:m0_read -> io_keys_s1_translator:uav_read
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wire io_keys_s1_agent_m0_readdatavalid; // io_keys_s1_translator:uav_readdatavalid -> io_keys_s1_agent:m0_readdatavalid
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wire io_keys_s1_agent_m0_lock; // io_keys_s1_agent:m0_lock -> io_keys_s1_translator:uav_lock
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wire [31:0] io_keys_s1_agent_m0_writedata; // io_keys_s1_agent:m0_writedata -> io_keys_s1_translator:uav_writedata
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wire io_keys_s1_agent_m0_write; // io_keys_s1_agent:m0_write -> io_keys_s1_translator:uav_write
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wire [2:0] io_keys_s1_agent_m0_burstcount; // io_keys_s1_agent:m0_burstcount -> io_keys_s1_translator:uav_burstcount
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wire io_keys_s1_agent_rf_source_valid; // io_keys_s1_agent:rf_source_valid -> io_keys_s1_agent_rsp_fifo:in_valid
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wire [114:0] io_keys_s1_agent_rf_source_data; // io_keys_s1_agent:rf_source_data -> io_keys_s1_agent_rsp_fifo:in_data
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wire io_keys_s1_agent_rf_source_ready; // io_keys_s1_agent_rsp_fifo:in_ready -> io_keys_s1_agent:rf_source_ready
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wire io_keys_s1_agent_rf_source_startofpacket; // io_keys_s1_agent:rf_source_startofpacket -> io_keys_s1_agent_rsp_fifo:in_startofpacket
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wire io_keys_s1_agent_rf_source_endofpacket; // io_keys_s1_agent:rf_source_endofpacket -> io_keys_s1_agent_rsp_fifo:in_endofpacket
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wire io_keys_s1_agent_rsp_fifo_out_valid; // io_keys_s1_agent_rsp_fifo:out_valid -> io_keys_s1_agent:rf_sink_valid
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wire [114:0] io_keys_s1_agent_rsp_fifo_out_data; // io_keys_s1_agent_rsp_fifo:out_data -> io_keys_s1_agent:rf_sink_data
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wire io_keys_s1_agent_rsp_fifo_out_ready; // io_keys_s1_agent:rf_sink_ready -> io_keys_s1_agent_rsp_fifo:out_ready
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wire io_keys_s1_agent_rsp_fifo_out_startofpacket; // io_keys_s1_agent_rsp_fifo:out_startofpacket -> io_keys_s1_agent:rf_sink_startofpacket
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wire io_keys_s1_agent_rsp_fifo_out_endofpacket; // io_keys_s1_agent_rsp_fifo:out_endofpacket -> io_keys_s1_agent:rf_sink_endofpacket
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wire cmd_mux_017_src_valid; // cmd_mux_017:src_valid -> io_keys_s1_agent:cp_valid
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wire [113:0] cmd_mux_017_src_data; // cmd_mux_017:src_data -> io_keys_s1_agent:cp_data
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wire cmd_mux_017_src_ready; // io_keys_s1_agent:cp_ready -> cmd_mux_017:src_ready
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wire [33:0] cmd_mux_017_src_channel; // cmd_mux_017:src_channel -> io_keys_s1_agent:cp_channel
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wire cmd_mux_017_src_startofpacket; // cmd_mux_017:src_startofpacket -> io_keys_s1_agent:cp_startofpacket
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wire cmd_mux_017_src_endofpacket; // cmd_mux_017:src_endofpacket -> io_keys_s1_agent:cp_endofpacket
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wire [31:0] io_switches_s1_agent_m0_readdata; // io_switches_s1_translator:uav_readdata -> io_switches_s1_agent:m0_readdata
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wire io_switches_s1_agent_m0_waitrequest; // io_switches_s1_translator:uav_waitrequest -> io_switches_s1_agent:m0_waitrequest
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wire io_switches_s1_agent_m0_debugaccess; // io_switches_s1_agent:m0_debugaccess -> io_switches_s1_translator:uav_debugaccess
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wire [31:0] io_switches_s1_agent_m0_address; // io_switches_s1_agent:m0_address -> io_switches_s1_translator:uav_address
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wire [3:0] io_switches_s1_agent_m0_byteenable; // io_switches_s1_agent:m0_byteenable -> io_switches_s1_translator:uav_byteenable
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wire io_switches_s1_agent_m0_read; // io_switches_s1_agent:m0_read -> io_switches_s1_translator:uav_read
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wire io_switches_s1_agent_m0_readdatavalid; // io_switches_s1_translator:uav_readdatavalid -> io_switches_s1_agent:m0_readdatavalid
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wire io_switches_s1_agent_m0_lock; // io_switches_s1_agent:m0_lock -> io_switches_s1_translator:uav_lock
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wire [31:0] io_switches_s1_agent_m0_writedata; // io_switches_s1_agent:m0_writedata -> io_switches_s1_translator:uav_writedata
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wire io_switches_s1_agent_m0_write; // io_switches_s1_agent:m0_write -> io_switches_s1_translator:uav_write
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wire [2:0] io_switches_s1_agent_m0_burstcount; // io_switches_s1_agent:m0_burstcount -> io_switches_s1_translator:uav_burstcount
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wire io_switches_s1_agent_rf_source_valid; // io_switches_s1_agent:rf_source_valid -> io_switches_s1_agent_rsp_fifo:in_valid
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wire [114:0] io_switches_s1_agent_rf_source_data; // io_switches_s1_agent:rf_source_data -> io_switches_s1_agent_rsp_fifo:in_data
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wire io_switches_s1_agent_rf_source_ready; // io_switches_s1_agent_rsp_fifo:in_ready -> io_switches_s1_agent:rf_source_ready
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wire io_switches_s1_agent_rf_source_startofpacket; // io_switches_s1_agent:rf_source_startofpacket -> io_switches_s1_agent_rsp_fifo:in_startofpacket
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wire io_switches_s1_agent_rf_source_endofpacket; // io_switches_s1_agent:rf_source_endofpacket -> io_switches_s1_agent_rsp_fifo:in_endofpacket
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wire io_switches_s1_agent_rsp_fifo_out_valid; // io_switches_s1_agent_rsp_fifo:out_valid -> io_switches_s1_agent:rf_sink_valid
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wire [114:0] io_switches_s1_agent_rsp_fifo_out_data; // io_switches_s1_agent_rsp_fifo:out_data -> io_switches_s1_agent:rf_sink_data
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wire io_switches_s1_agent_rsp_fifo_out_ready; // io_switches_s1_agent:rf_sink_ready -> io_switches_s1_agent_rsp_fifo:out_ready
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wire io_switches_s1_agent_rsp_fifo_out_startofpacket; // io_switches_s1_agent_rsp_fifo:out_startofpacket -> io_switches_s1_agent:rf_sink_startofpacket
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wire io_switches_s1_agent_rsp_fifo_out_endofpacket; // io_switches_s1_agent_rsp_fifo:out_endofpacket -> io_switches_s1_agent:rf_sink_endofpacket
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wire cmd_mux_018_src_valid; // cmd_mux_018:src_valid -> io_switches_s1_agent:cp_valid
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wire [113:0] cmd_mux_018_src_data; // cmd_mux_018:src_data -> io_switches_s1_agent:cp_data
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wire cmd_mux_018_src_ready; // io_switches_s1_agent:cp_ready -> cmd_mux_018:src_ready
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wire [33:0] cmd_mux_018_src_channel; // cmd_mux_018:src_channel -> io_switches_s1_agent:cp_channel
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wire cmd_mux_018_src_startofpacket; // cmd_mux_018:src_startofpacket -> io_switches_s1_agent:cp_startofpacket
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wire cmd_mux_018_src_endofpacket; // cmd_mux_018:src_endofpacket -> io_switches_s1_agent:cp_endofpacket
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wire [31:0] io_led_green_s1_agent_m0_readdata; // io_led_green_s1_translator:uav_readdata -> io_led_green_s1_agent:m0_readdata
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wire io_led_green_s1_agent_m0_waitrequest; // io_led_green_s1_translator:uav_waitrequest -> io_led_green_s1_agent:m0_waitrequest
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wire io_led_green_s1_agent_m0_debugaccess; // io_led_green_s1_agent:m0_debugaccess -> io_led_green_s1_translator:uav_debugaccess
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wire [31:0] io_led_green_s1_agent_m0_address; // io_led_green_s1_agent:m0_address -> io_led_green_s1_translator:uav_address
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wire [3:0] io_led_green_s1_agent_m0_byteenable; // io_led_green_s1_agent:m0_byteenable -> io_led_green_s1_translator:uav_byteenable
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wire io_led_green_s1_agent_m0_read; // io_led_green_s1_agent:m0_read -> io_led_green_s1_translator:uav_read
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wire io_led_green_s1_agent_m0_readdatavalid; // io_led_green_s1_translator:uav_readdatavalid -> io_led_green_s1_agent:m0_readdatavalid
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wire io_led_green_s1_agent_m0_lock; // io_led_green_s1_agent:m0_lock -> io_led_green_s1_translator:uav_lock
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wire [31:0] io_led_green_s1_agent_m0_writedata; // io_led_green_s1_agent:m0_writedata -> io_led_green_s1_translator:uav_writedata
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wire io_led_green_s1_agent_m0_write; // io_led_green_s1_agent:m0_write -> io_led_green_s1_translator:uav_write
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wire [2:0] io_led_green_s1_agent_m0_burstcount; // io_led_green_s1_agent:m0_burstcount -> io_led_green_s1_translator:uav_burstcount
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wire io_led_green_s1_agent_rf_source_valid; // io_led_green_s1_agent:rf_source_valid -> io_led_green_s1_agent_rsp_fifo:in_valid
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wire [114:0] io_led_green_s1_agent_rf_source_data; // io_led_green_s1_agent:rf_source_data -> io_led_green_s1_agent_rsp_fifo:in_data
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wire io_led_green_s1_agent_rf_source_ready; // io_led_green_s1_agent_rsp_fifo:in_ready -> io_led_green_s1_agent:rf_source_ready
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wire io_led_green_s1_agent_rf_source_startofpacket; // io_led_green_s1_agent:rf_source_startofpacket -> io_led_green_s1_agent_rsp_fifo:in_startofpacket
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wire io_led_green_s1_agent_rf_source_endofpacket; // io_led_green_s1_agent:rf_source_endofpacket -> io_led_green_s1_agent_rsp_fifo:in_endofpacket
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wire io_led_green_s1_agent_rsp_fifo_out_valid; // io_led_green_s1_agent_rsp_fifo:out_valid -> io_led_green_s1_agent:rf_sink_valid
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wire [114:0] io_led_green_s1_agent_rsp_fifo_out_data; // io_led_green_s1_agent_rsp_fifo:out_data -> io_led_green_s1_agent:rf_sink_data
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wire io_led_green_s1_agent_rsp_fifo_out_ready; // io_led_green_s1_agent:rf_sink_ready -> io_led_green_s1_agent_rsp_fifo:out_ready
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wire io_led_green_s1_agent_rsp_fifo_out_startofpacket; // io_led_green_s1_agent_rsp_fifo:out_startofpacket -> io_led_green_s1_agent:rf_sink_startofpacket
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wire io_led_green_s1_agent_rsp_fifo_out_endofpacket; // io_led_green_s1_agent_rsp_fifo:out_endofpacket -> io_led_green_s1_agent:rf_sink_endofpacket
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wire cmd_mux_019_src_valid; // cmd_mux_019:src_valid -> io_led_green_s1_agent:cp_valid
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wire [113:0] cmd_mux_019_src_data; // cmd_mux_019:src_data -> io_led_green_s1_agent:cp_data
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wire cmd_mux_019_src_ready; // io_led_green_s1_agent:cp_ready -> cmd_mux_019:src_ready
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wire [33:0] cmd_mux_019_src_channel; // cmd_mux_019:src_channel -> io_led_green_s1_agent:cp_channel
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wire cmd_mux_019_src_startofpacket; // cmd_mux_019:src_startofpacket -> io_led_green_s1_agent:cp_startofpacket
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wire cmd_mux_019_src_endofpacket; // cmd_mux_019:src_endofpacket -> io_led_green_s1_agent:cp_endofpacket
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wire [31:0] io_hex_s1_agent_m0_readdata; // io_hex_s1_translator:uav_readdata -> io_hex_s1_agent:m0_readdata
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wire io_hex_s1_agent_m0_waitrequest; // io_hex_s1_translator:uav_waitrequest -> io_hex_s1_agent:m0_waitrequest
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wire io_hex_s1_agent_m0_debugaccess; // io_hex_s1_agent:m0_debugaccess -> io_hex_s1_translator:uav_debugaccess
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wire [31:0] io_hex_s1_agent_m0_address; // io_hex_s1_agent:m0_address -> io_hex_s1_translator:uav_address
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wire [3:0] io_hex_s1_agent_m0_byteenable; // io_hex_s1_agent:m0_byteenable -> io_hex_s1_translator:uav_byteenable
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wire io_hex_s1_agent_m0_read; // io_hex_s1_agent:m0_read -> io_hex_s1_translator:uav_read
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wire io_hex_s1_agent_m0_readdatavalid; // io_hex_s1_translator:uav_readdatavalid -> io_hex_s1_agent:m0_readdatavalid
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wire io_hex_s1_agent_m0_lock; // io_hex_s1_agent:m0_lock -> io_hex_s1_translator:uav_lock
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wire [31:0] io_hex_s1_agent_m0_writedata; // io_hex_s1_agent:m0_writedata -> io_hex_s1_translator:uav_writedata
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wire io_hex_s1_agent_m0_write; // io_hex_s1_agent:m0_write -> io_hex_s1_translator:uav_write
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wire [2:0] io_hex_s1_agent_m0_burstcount; // io_hex_s1_agent:m0_burstcount -> io_hex_s1_translator:uav_burstcount
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wire io_hex_s1_agent_rf_source_valid; // io_hex_s1_agent:rf_source_valid -> io_hex_s1_agent_rsp_fifo:in_valid
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wire [114:0] io_hex_s1_agent_rf_source_data; // io_hex_s1_agent:rf_source_data -> io_hex_s1_agent_rsp_fifo:in_data
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wire io_hex_s1_agent_rf_source_ready; // io_hex_s1_agent_rsp_fifo:in_ready -> io_hex_s1_agent:rf_source_ready
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wire io_hex_s1_agent_rf_source_startofpacket; // io_hex_s1_agent:rf_source_startofpacket -> io_hex_s1_agent_rsp_fifo:in_startofpacket
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wire io_hex_s1_agent_rf_source_endofpacket; // io_hex_s1_agent:rf_source_endofpacket -> io_hex_s1_agent_rsp_fifo:in_endofpacket
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wire io_hex_s1_agent_rsp_fifo_out_valid; // io_hex_s1_agent_rsp_fifo:out_valid -> io_hex_s1_agent:rf_sink_valid
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wire [114:0] io_hex_s1_agent_rsp_fifo_out_data; // io_hex_s1_agent_rsp_fifo:out_data -> io_hex_s1_agent:rf_sink_data
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wire io_hex_s1_agent_rsp_fifo_out_ready; // io_hex_s1_agent:rf_sink_ready -> io_hex_s1_agent_rsp_fifo:out_ready
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wire io_hex_s1_agent_rsp_fifo_out_startofpacket; // io_hex_s1_agent_rsp_fifo:out_startofpacket -> io_hex_s1_agent:rf_sink_startofpacket
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wire io_hex_s1_agent_rsp_fifo_out_endofpacket; // io_hex_s1_agent_rsp_fifo:out_endofpacket -> io_hex_s1_agent:rf_sink_endofpacket
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wire cmd_mux_020_src_valid; // cmd_mux_020:src_valid -> io_hex_s1_agent:cp_valid
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wire [113:0] cmd_mux_020_src_data; // cmd_mux_020:src_data -> io_hex_s1_agent:cp_data
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wire cmd_mux_020_src_ready; // io_hex_s1_agent:cp_ready -> cmd_mux_020:src_ready
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wire [33:0] cmd_mux_020_src_channel; // cmd_mux_020:src_channel -> io_hex_s1_agent:cp_channel
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wire cmd_mux_020_src_startofpacket; // cmd_mux_020:src_startofpacket -> io_hex_s1_agent:cp_startofpacket
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wire cmd_mux_020_src_endofpacket; // cmd_mux_020:src_endofpacket -> io_hex_s1_agent:cp_endofpacket
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wire [31:0] vga_sprite_0_s1_agent_m0_readdata; // vga_sprite_0_s1_translator:uav_readdata -> vga_sprite_0_s1_agent:m0_readdata
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wire vga_sprite_0_s1_agent_m0_waitrequest; // vga_sprite_0_s1_translator:uav_waitrequest -> vga_sprite_0_s1_agent:m0_waitrequest
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wire vga_sprite_0_s1_agent_m0_debugaccess; // vga_sprite_0_s1_agent:m0_debugaccess -> vga_sprite_0_s1_translator:uav_debugaccess
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wire [31:0] vga_sprite_0_s1_agent_m0_address; // vga_sprite_0_s1_agent:m0_address -> vga_sprite_0_s1_translator:uav_address
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wire [3:0] vga_sprite_0_s1_agent_m0_byteenable; // vga_sprite_0_s1_agent:m0_byteenable -> vga_sprite_0_s1_translator:uav_byteenable
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wire vga_sprite_0_s1_agent_m0_read; // vga_sprite_0_s1_agent:m0_read -> vga_sprite_0_s1_translator:uav_read
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wire vga_sprite_0_s1_agent_m0_readdatavalid; // vga_sprite_0_s1_translator:uav_readdatavalid -> vga_sprite_0_s1_agent:m0_readdatavalid
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wire vga_sprite_0_s1_agent_m0_lock; // vga_sprite_0_s1_agent:m0_lock -> vga_sprite_0_s1_translator:uav_lock
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wire [31:0] vga_sprite_0_s1_agent_m0_writedata; // vga_sprite_0_s1_agent:m0_writedata -> vga_sprite_0_s1_translator:uav_writedata
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wire vga_sprite_0_s1_agent_m0_write; // vga_sprite_0_s1_agent:m0_write -> vga_sprite_0_s1_translator:uav_write
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wire [2:0] vga_sprite_0_s1_agent_m0_burstcount; // vga_sprite_0_s1_agent:m0_burstcount -> vga_sprite_0_s1_translator:uav_burstcount
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wire vga_sprite_0_s1_agent_rf_source_valid; // vga_sprite_0_s1_agent:rf_source_valid -> vga_sprite_0_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_0_s1_agent_rf_source_data; // vga_sprite_0_s1_agent:rf_source_data -> vga_sprite_0_s1_agent_rsp_fifo:in_data
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wire vga_sprite_0_s1_agent_rf_source_ready; // vga_sprite_0_s1_agent_rsp_fifo:in_ready -> vga_sprite_0_s1_agent:rf_source_ready
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wire vga_sprite_0_s1_agent_rf_source_startofpacket; // vga_sprite_0_s1_agent:rf_source_startofpacket -> vga_sprite_0_s1_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_0_s1_agent_rf_source_endofpacket; // vga_sprite_0_s1_agent:rf_source_endofpacket -> vga_sprite_0_s1_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_0_s1_agent_rsp_fifo_out_valid; // vga_sprite_0_s1_agent_rsp_fifo:out_valid -> vga_sprite_0_s1_agent:rf_sink_valid
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wire [114:0] vga_sprite_0_s1_agent_rsp_fifo_out_data; // vga_sprite_0_s1_agent_rsp_fifo:out_data -> vga_sprite_0_s1_agent:rf_sink_data
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wire vga_sprite_0_s1_agent_rsp_fifo_out_ready; // vga_sprite_0_s1_agent:rf_sink_ready -> vga_sprite_0_s1_agent_rsp_fifo:out_ready
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wire vga_sprite_0_s1_agent_rsp_fifo_out_startofpacket; // vga_sprite_0_s1_agent_rsp_fifo:out_startofpacket -> vga_sprite_0_s1_agent:rf_sink_startofpacket
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wire vga_sprite_0_s1_agent_rsp_fifo_out_endofpacket; // vga_sprite_0_s1_agent_rsp_fifo:out_endofpacket -> vga_sprite_0_s1_agent:rf_sink_endofpacket
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wire cmd_mux_021_src_valid; // cmd_mux_021:src_valid -> vga_sprite_0_s1_agent:cp_valid
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wire [113:0] cmd_mux_021_src_data; // cmd_mux_021:src_data -> vga_sprite_0_s1_agent:cp_data
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wire cmd_mux_021_src_ready; // vga_sprite_0_s1_agent:cp_ready -> cmd_mux_021:src_ready
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wire [33:0] cmd_mux_021_src_channel; // cmd_mux_021:src_channel -> vga_sprite_0_s1_agent:cp_channel
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wire cmd_mux_021_src_startofpacket; // cmd_mux_021:src_startofpacket -> vga_sprite_0_s1_agent:cp_startofpacket
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wire cmd_mux_021_src_endofpacket; // cmd_mux_021:src_endofpacket -> vga_sprite_0_s1_agent:cp_endofpacket
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wire [31:0] vga_sprite_1_s1_agent_m0_readdata; // vga_sprite_1_s1_translator:uav_readdata -> vga_sprite_1_s1_agent:m0_readdata
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wire vga_sprite_1_s1_agent_m0_waitrequest; // vga_sprite_1_s1_translator:uav_waitrequest -> vga_sprite_1_s1_agent:m0_waitrequest
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wire vga_sprite_1_s1_agent_m0_debugaccess; // vga_sprite_1_s1_agent:m0_debugaccess -> vga_sprite_1_s1_translator:uav_debugaccess
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wire [31:0] vga_sprite_1_s1_agent_m0_address; // vga_sprite_1_s1_agent:m0_address -> vga_sprite_1_s1_translator:uav_address
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wire [3:0] vga_sprite_1_s1_agent_m0_byteenable; // vga_sprite_1_s1_agent:m0_byteenable -> vga_sprite_1_s1_translator:uav_byteenable
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wire vga_sprite_1_s1_agent_m0_read; // vga_sprite_1_s1_agent:m0_read -> vga_sprite_1_s1_translator:uav_read
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wire vga_sprite_1_s1_agent_m0_readdatavalid; // vga_sprite_1_s1_translator:uav_readdatavalid -> vga_sprite_1_s1_agent:m0_readdatavalid
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wire vga_sprite_1_s1_agent_m0_lock; // vga_sprite_1_s1_agent:m0_lock -> vga_sprite_1_s1_translator:uav_lock
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wire [31:0] vga_sprite_1_s1_agent_m0_writedata; // vga_sprite_1_s1_agent:m0_writedata -> vga_sprite_1_s1_translator:uav_writedata
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wire vga_sprite_1_s1_agent_m0_write; // vga_sprite_1_s1_agent:m0_write -> vga_sprite_1_s1_translator:uav_write
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wire [2:0] vga_sprite_1_s1_agent_m0_burstcount; // vga_sprite_1_s1_agent:m0_burstcount -> vga_sprite_1_s1_translator:uav_burstcount
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wire vga_sprite_1_s1_agent_rf_source_valid; // vga_sprite_1_s1_agent:rf_source_valid -> vga_sprite_1_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_1_s1_agent_rf_source_data; // vga_sprite_1_s1_agent:rf_source_data -> vga_sprite_1_s1_agent_rsp_fifo:in_data
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wire vga_sprite_1_s1_agent_rf_source_ready; // vga_sprite_1_s1_agent_rsp_fifo:in_ready -> vga_sprite_1_s1_agent:rf_source_ready
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wire vga_sprite_1_s1_agent_rf_source_startofpacket; // vga_sprite_1_s1_agent:rf_source_startofpacket -> vga_sprite_1_s1_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_1_s1_agent_rf_source_endofpacket; // vga_sprite_1_s1_agent:rf_source_endofpacket -> vga_sprite_1_s1_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_1_s1_agent_rsp_fifo_out_valid; // vga_sprite_1_s1_agent_rsp_fifo:out_valid -> vga_sprite_1_s1_agent:rf_sink_valid
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wire [114:0] vga_sprite_1_s1_agent_rsp_fifo_out_data; // vga_sprite_1_s1_agent_rsp_fifo:out_data -> vga_sprite_1_s1_agent:rf_sink_data
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wire vga_sprite_1_s1_agent_rsp_fifo_out_ready; // vga_sprite_1_s1_agent:rf_sink_ready -> vga_sprite_1_s1_agent_rsp_fifo:out_ready
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wire vga_sprite_1_s1_agent_rsp_fifo_out_startofpacket; // vga_sprite_1_s1_agent_rsp_fifo:out_startofpacket -> vga_sprite_1_s1_agent:rf_sink_startofpacket
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wire vga_sprite_1_s1_agent_rsp_fifo_out_endofpacket; // vga_sprite_1_s1_agent_rsp_fifo:out_endofpacket -> vga_sprite_1_s1_agent:rf_sink_endofpacket
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wire cmd_mux_022_src_valid; // cmd_mux_022:src_valid -> vga_sprite_1_s1_agent:cp_valid
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wire [113:0] cmd_mux_022_src_data; // cmd_mux_022:src_data -> vga_sprite_1_s1_agent:cp_data
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wire cmd_mux_022_src_ready; // vga_sprite_1_s1_agent:cp_ready -> cmd_mux_022:src_ready
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wire [33:0] cmd_mux_022_src_channel; // cmd_mux_022:src_channel -> vga_sprite_1_s1_agent:cp_channel
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wire cmd_mux_022_src_startofpacket; // cmd_mux_022:src_startofpacket -> vga_sprite_1_s1_agent:cp_startofpacket
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wire cmd_mux_022_src_endofpacket; // cmd_mux_022:src_endofpacket -> vga_sprite_1_s1_agent:cp_endofpacket
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wire [31:0] vga_sprite_2_s1_agent_m0_readdata; // vga_sprite_2_s1_translator:uav_readdata -> vga_sprite_2_s1_agent:m0_readdata
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wire vga_sprite_2_s1_agent_m0_waitrequest; // vga_sprite_2_s1_translator:uav_waitrequest -> vga_sprite_2_s1_agent:m0_waitrequest
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wire vga_sprite_2_s1_agent_m0_debugaccess; // vga_sprite_2_s1_agent:m0_debugaccess -> vga_sprite_2_s1_translator:uav_debugaccess
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wire [31:0] vga_sprite_2_s1_agent_m0_address; // vga_sprite_2_s1_agent:m0_address -> vga_sprite_2_s1_translator:uav_address
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wire [3:0] vga_sprite_2_s1_agent_m0_byteenable; // vga_sprite_2_s1_agent:m0_byteenable -> vga_sprite_2_s1_translator:uav_byteenable
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wire vga_sprite_2_s1_agent_m0_read; // vga_sprite_2_s1_agent:m0_read -> vga_sprite_2_s1_translator:uav_read
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wire vga_sprite_2_s1_agent_m0_readdatavalid; // vga_sprite_2_s1_translator:uav_readdatavalid -> vga_sprite_2_s1_agent:m0_readdatavalid
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wire vga_sprite_2_s1_agent_m0_lock; // vga_sprite_2_s1_agent:m0_lock -> vga_sprite_2_s1_translator:uav_lock
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wire [31:0] vga_sprite_2_s1_agent_m0_writedata; // vga_sprite_2_s1_agent:m0_writedata -> vga_sprite_2_s1_translator:uav_writedata
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wire vga_sprite_2_s1_agent_m0_write; // vga_sprite_2_s1_agent:m0_write -> vga_sprite_2_s1_translator:uav_write
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wire [2:0] vga_sprite_2_s1_agent_m0_burstcount; // vga_sprite_2_s1_agent:m0_burstcount -> vga_sprite_2_s1_translator:uav_burstcount
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wire vga_sprite_2_s1_agent_rf_source_valid; // vga_sprite_2_s1_agent:rf_source_valid -> vga_sprite_2_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_2_s1_agent_rf_source_data; // vga_sprite_2_s1_agent:rf_source_data -> vga_sprite_2_s1_agent_rsp_fifo:in_data
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wire vga_sprite_2_s1_agent_rf_source_ready; // vga_sprite_2_s1_agent_rsp_fifo:in_ready -> vga_sprite_2_s1_agent:rf_source_ready
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wire vga_sprite_2_s1_agent_rf_source_startofpacket; // vga_sprite_2_s1_agent:rf_source_startofpacket -> vga_sprite_2_s1_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_2_s1_agent_rf_source_endofpacket; // vga_sprite_2_s1_agent:rf_source_endofpacket -> vga_sprite_2_s1_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_2_s1_agent_rsp_fifo_out_valid; // vga_sprite_2_s1_agent_rsp_fifo:out_valid -> vga_sprite_2_s1_agent:rf_sink_valid
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wire [114:0] vga_sprite_2_s1_agent_rsp_fifo_out_data; // vga_sprite_2_s1_agent_rsp_fifo:out_data -> vga_sprite_2_s1_agent:rf_sink_data
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wire vga_sprite_2_s1_agent_rsp_fifo_out_ready; // vga_sprite_2_s1_agent:rf_sink_ready -> vga_sprite_2_s1_agent_rsp_fifo:out_ready
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wire vga_sprite_2_s1_agent_rsp_fifo_out_startofpacket; // vga_sprite_2_s1_agent_rsp_fifo:out_startofpacket -> vga_sprite_2_s1_agent:rf_sink_startofpacket
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wire vga_sprite_2_s1_agent_rsp_fifo_out_endofpacket; // vga_sprite_2_s1_agent_rsp_fifo:out_endofpacket -> vga_sprite_2_s1_agent:rf_sink_endofpacket
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wire cmd_mux_023_src_valid; // cmd_mux_023:src_valid -> vga_sprite_2_s1_agent:cp_valid
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wire [113:0] cmd_mux_023_src_data; // cmd_mux_023:src_data -> vga_sprite_2_s1_agent:cp_data
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wire cmd_mux_023_src_ready; // vga_sprite_2_s1_agent:cp_ready -> cmd_mux_023:src_ready
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wire [33:0] cmd_mux_023_src_channel; // cmd_mux_023:src_channel -> vga_sprite_2_s1_agent:cp_channel
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wire cmd_mux_023_src_startofpacket; // cmd_mux_023:src_startofpacket -> vga_sprite_2_s1_agent:cp_startofpacket
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wire cmd_mux_023_src_endofpacket; // cmd_mux_023:src_endofpacket -> vga_sprite_2_s1_agent:cp_endofpacket
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wire [31:0] vga_sprite_3_s1_agent_m0_readdata; // vga_sprite_3_s1_translator:uav_readdata -> vga_sprite_3_s1_agent:m0_readdata
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wire vga_sprite_3_s1_agent_m0_waitrequest; // vga_sprite_3_s1_translator:uav_waitrequest -> vga_sprite_3_s1_agent:m0_waitrequest
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wire vga_sprite_3_s1_agent_m0_debugaccess; // vga_sprite_3_s1_agent:m0_debugaccess -> vga_sprite_3_s1_translator:uav_debugaccess
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wire [31:0] vga_sprite_3_s1_agent_m0_address; // vga_sprite_3_s1_agent:m0_address -> vga_sprite_3_s1_translator:uav_address
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wire [3:0] vga_sprite_3_s1_agent_m0_byteenable; // vga_sprite_3_s1_agent:m0_byteenable -> vga_sprite_3_s1_translator:uav_byteenable
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wire vga_sprite_3_s1_agent_m0_read; // vga_sprite_3_s1_agent:m0_read -> vga_sprite_3_s1_translator:uav_read
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wire vga_sprite_3_s1_agent_m0_readdatavalid; // vga_sprite_3_s1_translator:uav_readdatavalid -> vga_sprite_3_s1_agent:m0_readdatavalid
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wire vga_sprite_3_s1_agent_m0_lock; // vga_sprite_3_s1_agent:m0_lock -> vga_sprite_3_s1_translator:uav_lock
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wire [31:0] vga_sprite_3_s1_agent_m0_writedata; // vga_sprite_3_s1_agent:m0_writedata -> vga_sprite_3_s1_translator:uav_writedata
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wire vga_sprite_3_s1_agent_m0_write; // vga_sprite_3_s1_agent:m0_write -> vga_sprite_3_s1_translator:uav_write
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wire [2:0] vga_sprite_3_s1_agent_m0_burstcount; // vga_sprite_3_s1_agent:m0_burstcount -> vga_sprite_3_s1_translator:uav_burstcount
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wire vga_sprite_3_s1_agent_rf_source_valid; // vga_sprite_3_s1_agent:rf_source_valid -> vga_sprite_3_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_3_s1_agent_rf_source_data; // vga_sprite_3_s1_agent:rf_source_data -> vga_sprite_3_s1_agent_rsp_fifo:in_data
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wire vga_sprite_3_s1_agent_rf_source_ready; // vga_sprite_3_s1_agent_rsp_fifo:in_ready -> vga_sprite_3_s1_agent:rf_source_ready
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wire vga_sprite_3_s1_agent_rf_source_startofpacket; // vga_sprite_3_s1_agent:rf_source_startofpacket -> vga_sprite_3_s1_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_3_s1_agent_rf_source_endofpacket; // vga_sprite_3_s1_agent:rf_source_endofpacket -> vga_sprite_3_s1_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_3_s1_agent_rsp_fifo_out_valid; // vga_sprite_3_s1_agent_rsp_fifo:out_valid -> vga_sprite_3_s1_agent:rf_sink_valid
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wire [114:0] vga_sprite_3_s1_agent_rsp_fifo_out_data; // vga_sprite_3_s1_agent_rsp_fifo:out_data -> vga_sprite_3_s1_agent:rf_sink_data
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wire vga_sprite_3_s1_agent_rsp_fifo_out_ready; // vga_sprite_3_s1_agent:rf_sink_ready -> vga_sprite_3_s1_agent_rsp_fifo:out_ready
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wire vga_sprite_3_s1_agent_rsp_fifo_out_startofpacket; // vga_sprite_3_s1_agent_rsp_fifo:out_startofpacket -> vga_sprite_3_s1_agent:rf_sink_startofpacket
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wire vga_sprite_3_s1_agent_rsp_fifo_out_endofpacket; // vga_sprite_3_s1_agent_rsp_fifo:out_endofpacket -> vga_sprite_3_s1_agent:rf_sink_endofpacket
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wire cmd_mux_024_src_valid; // cmd_mux_024:src_valid -> vga_sprite_3_s1_agent:cp_valid
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wire [113:0] cmd_mux_024_src_data; // cmd_mux_024:src_data -> vga_sprite_3_s1_agent:cp_data
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wire cmd_mux_024_src_ready; // vga_sprite_3_s1_agent:cp_ready -> cmd_mux_024:src_ready
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wire [33:0] cmd_mux_024_src_channel; // cmd_mux_024:src_channel -> vga_sprite_3_s1_agent:cp_channel
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wire cmd_mux_024_src_startofpacket; // cmd_mux_024:src_startofpacket -> vga_sprite_3_s1_agent:cp_startofpacket
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wire cmd_mux_024_src_endofpacket; // cmd_mux_024:src_endofpacket -> vga_sprite_3_s1_agent:cp_endofpacket
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wire [31:0] io_vga_sync_s1_agent_m0_readdata; // io_vga_sync_s1_translator:uav_readdata -> io_vga_sync_s1_agent:m0_readdata
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wire io_vga_sync_s1_agent_m0_waitrequest; // io_vga_sync_s1_translator:uav_waitrequest -> io_vga_sync_s1_agent:m0_waitrequest
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wire io_vga_sync_s1_agent_m0_debugaccess; // io_vga_sync_s1_agent:m0_debugaccess -> io_vga_sync_s1_translator:uav_debugaccess
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wire [31:0] io_vga_sync_s1_agent_m0_address; // io_vga_sync_s1_agent:m0_address -> io_vga_sync_s1_translator:uav_address
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wire [3:0] io_vga_sync_s1_agent_m0_byteenable; // io_vga_sync_s1_agent:m0_byteenable -> io_vga_sync_s1_translator:uav_byteenable
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wire io_vga_sync_s1_agent_m0_read; // io_vga_sync_s1_agent:m0_read -> io_vga_sync_s1_translator:uav_read
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wire io_vga_sync_s1_agent_m0_readdatavalid; // io_vga_sync_s1_translator:uav_readdatavalid -> io_vga_sync_s1_agent:m0_readdatavalid
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wire io_vga_sync_s1_agent_m0_lock; // io_vga_sync_s1_agent:m0_lock -> io_vga_sync_s1_translator:uav_lock
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wire [31:0] io_vga_sync_s1_agent_m0_writedata; // io_vga_sync_s1_agent:m0_writedata -> io_vga_sync_s1_translator:uav_writedata
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wire io_vga_sync_s1_agent_m0_write; // io_vga_sync_s1_agent:m0_write -> io_vga_sync_s1_translator:uav_write
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wire [2:0] io_vga_sync_s1_agent_m0_burstcount; // io_vga_sync_s1_agent:m0_burstcount -> io_vga_sync_s1_translator:uav_burstcount
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wire io_vga_sync_s1_agent_rf_source_valid; // io_vga_sync_s1_agent:rf_source_valid -> io_vga_sync_s1_agent_rsp_fifo:in_valid
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wire [114:0] io_vga_sync_s1_agent_rf_source_data; // io_vga_sync_s1_agent:rf_source_data -> io_vga_sync_s1_agent_rsp_fifo:in_data
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wire io_vga_sync_s1_agent_rf_source_ready; // io_vga_sync_s1_agent_rsp_fifo:in_ready -> io_vga_sync_s1_agent:rf_source_ready
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wire io_vga_sync_s1_agent_rf_source_startofpacket; // io_vga_sync_s1_agent:rf_source_startofpacket -> io_vga_sync_s1_agent_rsp_fifo:in_startofpacket
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wire io_vga_sync_s1_agent_rf_source_endofpacket; // io_vga_sync_s1_agent:rf_source_endofpacket -> io_vga_sync_s1_agent_rsp_fifo:in_endofpacket
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wire io_vga_sync_s1_agent_rsp_fifo_out_valid; // io_vga_sync_s1_agent_rsp_fifo:out_valid -> io_vga_sync_s1_agent:rf_sink_valid
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wire [114:0] io_vga_sync_s1_agent_rsp_fifo_out_data; // io_vga_sync_s1_agent_rsp_fifo:out_data -> io_vga_sync_s1_agent:rf_sink_data
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wire io_vga_sync_s1_agent_rsp_fifo_out_ready; // io_vga_sync_s1_agent:rf_sink_ready -> io_vga_sync_s1_agent_rsp_fifo:out_ready
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wire io_vga_sync_s1_agent_rsp_fifo_out_startofpacket; // io_vga_sync_s1_agent_rsp_fifo:out_startofpacket -> io_vga_sync_s1_agent:rf_sink_startofpacket
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wire io_vga_sync_s1_agent_rsp_fifo_out_endofpacket; // io_vga_sync_s1_agent_rsp_fifo:out_endofpacket -> io_vga_sync_s1_agent:rf_sink_endofpacket
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wire cmd_mux_025_src_valid; // cmd_mux_025:src_valid -> io_vga_sync_s1_agent:cp_valid
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wire [113:0] cmd_mux_025_src_data; // cmd_mux_025:src_data -> io_vga_sync_s1_agent:cp_data
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wire cmd_mux_025_src_ready; // io_vga_sync_s1_agent:cp_ready -> cmd_mux_025:src_ready
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wire [33:0] cmd_mux_025_src_channel; // cmd_mux_025:src_channel -> io_vga_sync_s1_agent:cp_channel
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wire cmd_mux_025_src_startofpacket; // cmd_mux_025:src_startofpacket -> io_vga_sync_s1_agent:cp_startofpacket
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wire cmd_mux_025_src_endofpacket; // cmd_mux_025:src_endofpacket -> io_vga_sync_s1_agent:cp_endofpacket
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wire [31:0] vga_sprite_4_s1_agent_m0_readdata; // vga_sprite_4_s1_translator:uav_readdata -> vga_sprite_4_s1_agent:m0_readdata
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wire vga_sprite_4_s1_agent_m0_waitrequest; // vga_sprite_4_s1_translator:uav_waitrequest -> vga_sprite_4_s1_agent:m0_waitrequest
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wire vga_sprite_4_s1_agent_m0_debugaccess; // vga_sprite_4_s1_agent:m0_debugaccess -> vga_sprite_4_s1_translator:uav_debugaccess
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wire [31:0] vga_sprite_4_s1_agent_m0_address; // vga_sprite_4_s1_agent:m0_address -> vga_sprite_4_s1_translator:uav_address
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wire [3:0] vga_sprite_4_s1_agent_m0_byteenable; // vga_sprite_4_s1_agent:m0_byteenable -> vga_sprite_4_s1_translator:uav_byteenable
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wire vga_sprite_4_s1_agent_m0_read; // vga_sprite_4_s1_agent:m0_read -> vga_sprite_4_s1_translator:uav_read
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wire vga_sprite_4_s1_agent_m0_readdatavalid; // vga_sprite_4_s1_translator:uav_readdatavalid -> vga_sprite_4_s1_agent:m0_readdatavalid
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wire vga_sprite_4_s1_agent_m0_lock; // vga_sprite_4_s1_agent:m0_lock -> vga_sprite_4_s1_translator:uav_lock
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wire [31:0] vga_sprite_4_s1_agent_m0_writedata; // vga_sprite_4_s1_agent:m0_writedata -> vga_sprite_4_s1_translator:uav_writedata
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wire vga_sprite_4_s1_agent_m0_write; // vga_sprite_4_s1_agent:m0_write -> vga_sprite_4_s1_translator:uav_write
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wire [2:0] vga_sprite_4_s1_agent_m0_burstcount; // vga_sprite_4_s1_agent:m0_burstcount -> vga_sprite_4_s1_translator:uav_burstcount
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wire vga_sprite_4_s1_agent_rf_source_valid; // vga_sprite_4_s1_agent:rf_source_valid -> vga_sprite_4_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_4_s1_agent_rf_source_data; // vga_sprite_4_s1_agent:rf_source_data -> vga_sprite_4_s1_agent_rsp_fifo:in_data
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wire vga_sprite_4_s1_agent_rf_source_ready; // vga_sprite_4_s1_agent_rsp_fifo:in_ready -> vga_sprite_4_s1_agent:rf_source_ready
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wire vga_sprite_4_s1_agent_rf_source_startofpacket; // vga_sprite_4_s1_agent:rf_source_startofpacket -> vga_sprite_4_s1_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_4_s1_agent_rf_source_endofpacket; // vga_sprite_4_s1_agent:rf_source_endofpacket -> vga_sprite_4_s1_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_4_s1_agent_rsp_fifo_out_valid; // vga_sprite_4_s1_agent_rsp_fifo:out_valid -> vga_sprite_4_s1_agent:rf_sink_valid
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wire [114:0] vga_sprite_4_s1_agent_rsp_fifo_out_data; // vga_sprite_4_s1_agent_rsp_fifo:out_data -> vga_sprite_4_s1_agent:rf_sink_data
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wire vga_sprite_4_s1_agent_rsp_fifo_out_ready; // vga_sprite_4_s1_agent:rf_sink_ready -> vga_sprite_4_s1_agent_rsp_fifo:out_ready
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wire vga_sprite_4_s1_agent_rsp_fifo_out_startofpacket; // vga_sprite_4_s1_agent_rsp_fifo:out_startofpacket -> vga_sprite_4_s1_agent:rf_sink_startofpacket
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wire vga_sprite_4_s1_agent_rsp_fifo_out_endofpacket; // vga_sprite_4_s1_agent_rsp_fifo:out_endofpacket -> vga_sprite_4_s1_agent:rf_sink_endofpacket
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wire cmd_mux_026_src_valid; // cmd_mux_026:src_valid -> vga_sprite_4_s1_agent:cp_valid
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wire [113:0] cmd_mux_026_src_data; // cmd_mux_026:src_data -> vga_sprite_4_s1_agent:cp_data
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wire cmd_mux_026_src_ready; // vga_sprite_4_s1_agent:cp_ready -> cmd_mux_026:src_ready
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wire [33:0] cmd_mux_026_src_channel; // cmd_mux_026:src_channel -> vga_sprite_4_s1_agent:cp_channel
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wire cmd_mux_026_src_startofpacket; // cmd_mux_026:src_startofpacket -> vga_sprite_4_s1_agent:cp_startofpacket
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wire cmd_mux_026_src_endofpacket; // cmd_mux_026:src_endofpacket -> vga_sprite_4_s1_agent:cp_endofpacket
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wire [31:0] vga_sprite_5_s1_agent_m0_readdata; // vga_sprite_5_s1_translator:uav_readdata -> vga_sprite_5_s1_agent:m0_readdata
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wire vga_sprite_5_s1_agent_m0_waitrequest; // vga_sprite_5_s1_translator:uav_waitrequest -> vga_sprite_5_s1_agent:m0_waitrequest
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wire vga_sprite_5_s1_agent_m0_debugaccess; // vga_sprite_5_s1_agent:m0_debugaccess -> vga_sprite_5_s1_translator:uav_debugaccess
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wire [31:0] vga_sprite_5_s1_agent_m0_address; // vga_sprite_5_s1_agent:m0_address -> vga_sprite_5_s1_translator:uav_address
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wire [3:0] vga_sprite_5_s1_agent_m0_byteenable; // vga_sprite_5_s1_agent:m0_byteenable -> vga_sprite_5_s1_translator:uav_byteenable
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wire vga_sprite_5_s1_agent_m0_read; // vga_sprite_5_s1_agent:m0_read -> vga_sprite_5_s1_translator:uav_read
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wire vga_sprite_5_s1_agent_m0_readdatavalid; // vga_sprite_5_s1_translator:uav_readdatavalid -> vga_sprite_5_s1_agent:m0_readdatavalid
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wire vga_sprite_5_s1_agent_m0_lock; // vga_sprite_5_s1_agent:m0_lock -> vga_sprite_5_s1_translator:uav_lock
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wire [31:0] vga_sprite_5_s1_agent_m0_writedata; // vga_sprite_5_s1_agent:m0_writedata -> vga_sprite_5_s1_translator:uav_writedata
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wire vga_sprite_5_s1_agent_m0_write; // vga_sprite_5_s1_agent:m0_write -> vga_sprite_5_s1_translator:uav_write
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wire [2:0] vga_sprite_5_s1_agent_m0_burstcount; // vga_sprite_5_s1_agent:m0_burstcount -> vga_sprite_5_s1_translator:uav_burstcount
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wire vga_sprite_5_s1_agent_rf_source_valid; // vga_sprite_5_s1_agent:rf_source_valid -> vga_sprite_5_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_5_s1_agent_rf_source_data; // vga_sprite_5_s1_agent:rf_source_data -> vga_sprite_5_s1_agent_rsp_fifo:in_data
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wire vga_sprite_5_s1_agent_rf_source_ready; // vga_sprite_5_s1_agent_rsp_fifo:in_ready -> vga_sprite_5_s1_agent:rf_source_ready
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wire vga_sprite_5_s1_agent_rf_source_startofpacket; // vga_sprite_5_s1_agent:rf_source_startofpacket -> vga_sprite_5_s1_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_5_s1_agent_rf_source_endofpacket; // vga_sprite_5_s1_agent:rf_source_endofpacket -> vga_sprite_5_s1_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_5_s1_agent_rsp_fifo_out_valid; // vga_sprite_5_s1_agent_rsp_fifo:out_valid -> vga_sprite_5_s1_agent:rf_sink_valid
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wire [114:0] vga_sprite_5_s1_agent_rsp_fifo_out_data; // vga_sprite_5_s1_agent_rsp_fifo:out_data -> vga_sprite_5_s1_agent:rf_sink_data
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wire vga_sprite_5_s1_agent_rsp_fifo_out_ready; // vga_sprite_5_s1_agent:rf_sink_ready -> vga_sprite_5_s1_agent_rsp_fifo:out_ready
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wire vga_sprite_5_s1_agent_rsp_fifo_out_startofpacket; // vga_sprite_5_s1_agent_rsp_fifo:out_startofpacket -> vga_sprite_5_s1_agent:rf_sink_startofpacket
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wire vga_sprite_5_s1_agent_rsp_fifo_out_endofpacket; // vga_sprite_5_s1_agent_rsp_fifo:out_endofpacket -> vga_sprite_5_s1_agent:rf_sink_endofpacket
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wire cmd_mux_027_src_valid; // cmd_mux_027:src_valid -> vga_sprite_5_s1_agent:cp_valid
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wire [113:0] cmd_mux_027_src_data; // cmd_mux_027:src_data -> vga_sprite_5_s1_agent:cp_data
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wire cmd_mux_027_src_ready; // vga_sprite_5_s1_agent:cp_ready -> cmd_mux_027:src_ready
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wire [33:0] cmd_mux_027_src_channel; // cmd_mux_027:src_channel -> vga_sprite_5_s1_agent:cp_channel
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wire cmd_mux_027_src_startofpacket; // cmd_mux_027:src_startofpacket -> vga_sprite_5_s1_agent:cp_startofpacket
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wire cmd_mux_027_src_endofpacket; // cmd_mux_027:src_endofpacket -> vga_sprite_5_s1_agent:cp_endofpacket
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wire [31:0] vga_sprite_6_s1_agent_m0_readdata; // vga_sprite_6_s1_translator:uav_readdata -> vga_sprite_6_s1_agent:m0_readdata
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wire vga_sprite_6_s1_agent_m0_waitrequest; // vga_sprite_6_s1_translator:uav_waitrequest -> vga_sprite_6_s1_agent:m0_waitrequest
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wire vga_sprite_6_s1_agent_m0_debugaccess; // vga_sprite_6_s1_agent:m0_debugaccess -> vga_sprite_6_s1_translator:uav_debugaccess
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wire [31:0] vga_sprite_6_s1_agent_m0_address; // vga_sprite_6_s1_agent:m0_address -> vga_sprite_6_s1_translator:uav_address
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wire [3:0] vga_sprite_6_s1_agent_m0_byteenable; // vga_sprite_6_s1_agent:m0_byteenable -> vga_sprite_6_s1_translator:uav_byteenable
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wire vga_sprite_6_s1_agent_m0_read; // vga_sprite_6_s1_agent:m0_read -> vga_sprite_6_s1_translator:uav_read
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wire vga_sprite_6_s1_agent_m0_readdatavalid; // vga_sprite_6_s1_translator:uav_readdatavalid -> vga_sprite_6_s1_agent:m0_readdatavalid
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wire vga_sprite_6_s1_agent_m0_lock; // vga_sprite_6_s1_agent:m0_lock -> vga_sprite_6_s1_translator:uav_lock
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wire [31:0] vga_sprite_6_s1_agent_m0_writedata; // vga_sprite_6_s1_agent:m0_writedata -> vga_sprite_6_s1_translator:uav_writedata
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wire vga_sprite_6_s1_agent_m0_write; // vga_sprite_6_s1_agent:m0_write -> vga_sprite_6_s1_translator:uav_write
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wire [2:0] vga_sprite_6_s1_agent_m0_burstcount; // vga_sprite_6_s1_agent:m0_burstcount -> vga_sprite_6_s1_translator:uav_burstcount
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wire vga_sprite_6_s1_agent_rf_source_valid; // vga_sprite_6_s1_agent:rf_source_valid -> vga_sprite_6_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_6_s1_agent_rf_source_data; // vga_sprite_6_s1_agent:rf_source_data -> vga_sprite_6_s1_agent_rsp_fifo:in_data
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wire vga_sprite_6_s1_agent_rf_source_ready; // vga_sprite_6_s1_agent_rsp_fifo:in_ready -> vga_sprite_6_s1_agent:rf_source_ready
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wire vga_sprite_6_s1_agent_rf_source_startofpacket; // vga_sprite_6_s1_agent:rf_source_startofpacket -> vga_sprite_6_s1_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_6_s1_agent_rf_source_endofpacket; // vga_sprite_6_s1_agent:rf_source_endofpacket -> vga_sprite_6_s1_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_6_s1_agent_rsp_fifo_out_valid; // vga_sprite_6_s1_agent_rsp_fifo:out_valid -> vga_sprite_6_s1_agent:rf_sink_valid
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wire [114:0] vga_sprite_6_s1_agent_rsp_fifo_out_data; // vga_sprite_6_s1_agent_rsp_fifo:out_data -> vga_sprite_6_s1_agent:rf_sink_data
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wire vga_sprite_6_s1_agent_rsp_fifo_out_ready; // vga_sprite_6_s1_agent:rf_sink_ready -> vga_sprite_6_s1_agent_rsp_fifo:out_ready
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wire vga_sprite_6_s1_agent_rsp_fifo_out_startofpacket; // vga_sprite_6_s1_agent_rsp_fifo:out_startofpacket -> vga_sprite_6_s1_agent:rf_sink_startofpacket
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wire vga_sprite_6_s1_agent_rsp_fifo_out_endofpacket; // vga_sprite_6_s1_agent_rsp_fifo:out_endofpacket -> vga_sprite_6_s1_agent:rf_sink_endofpacket
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wire cmd_mux_028_src_valid; // cmd_mux_028:src_valid -> vga_sprite_6_s1_agent:cp_valid
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wire [113:0] cmd_mux_028_src_data; // cmd_mux_028:src_data -> vga_sprite_6_s1_agent:cp_data
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wire cmd_mux_028_src_ready; // vga_sprite_6_s1_agent:cp_ready -> cmd_mux_028:src_ready
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wire [33:0] cmd_mux_028_src_channel; // cmd_mux_028:src_channel -> vga_sprite_6_s1_agent:cp_channel
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wire cmd_mux_028_src_startofpacket; // cmd_mux_028:src_startofpacket -> vga_sprite_6_s1_agent:cp_startofpacket
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wire cmd_mux_028_src_endofpacket; // cmd_mux_028:src_endofpacket -> vga_sprite_6_s1_agent:cp_endofpacket
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wire [31:0] vga_sprite_7_s1_agent_m0_readdata; // vga_sprite_7_s1_translator:uav_readdata -> vga_sprite_7_s1_agent:m0_readdata
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wire vga_sprite_7_s1_agent_m0_waitrequest; // vga_sprite_7_s1_translator:uav_waitrequest -> vga_sprite_7_s1_agent:m0_waitrequest
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wire vga_sprite_7_s1_agent_m0_debugaccess; // vga_sprite_7_s1_agent:m0_debugaccess -> vga_sprite_7_s1_translator:uav_debugaccess
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wire [31:0] vga_sprite_7_s1_agent_m0_address; // vga_sprite_7_s1_agent:m0_address -> vga_sprite_7_s1_translator:uav_address
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wire [3:0] vga_sprite_7_s1_agent_m0_byteenable; // vga_sprite_7_s1_agent:m0_byteenable -> vga_sprite_7_s1_translator:uav_byteenable
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wire vga_sprite_7_s1_agent_m0_read; // vga_sprite_7_s1_agent:m0_read -> vga_sprite_7_s1_translator:uav_read
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wire vga_sprite_7_s1_agent_m0_readdatavalid; // vga_sprite_7_s1_translator:uav_readdatavalid -> vga_sprite_7_s1_agent:m0_readdatavalid
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wire vga_sprite_7_s1_agent_m0_lock; // vga_sprite_7_s1_agent:m0_lock -> vga_sprite_7_s1_translator:uav_lock
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wire [31:0] vga_sprite_7_s1_agent_m0_writedata; // vga_sprite_7_s1_agent:m0_writedata -> vga_sprite_7_s1_translator:uav_writedata
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wire vga_sprite_7_s1_agent_m0_write; // vga_sprite_7_s1_agent:m0_write -> vga_sprite_7_s1_translator:uav_write
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wire [2:0] vga_sprite_7_s1_agent_m0_burstcount; // vga_sprite_7_s1_agent:m0_burstcount -> vga_sprite_7_s1_translator:uav_burstcount
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wire vga_sprite_7_s1_agent_rf_source_valid; // vga_sprite_7_s1_agent:rf_source_valid -> vga_sprite_7_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_sprite_7_s1_agent_rf_source_data; // vga_sprite_7_s1_agent:rf_source_data -> vga_sprite_7_s1_agent_rsp_fifo:in_data
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wire vga_sprite_7_s1_agent_rf_source_ready; // vga_sprite_7_s1_agent_rsp_fifo:in_ready -> vga_sprite_7_s1_agent:rf_source_ready
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wire vga_sprite_7_s1_agent_rf_source_startofpacket; // vga_sprite_7_s1_agent:rf_source_startofpacket -> vga_sprite_7_s1_agent_rsp_fifo:in_startofpacket
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wire vga_sprite_7_s1_agent_rf_source_endofpacket; // vga_sprite_7_s1_agent:rf_source_endofpacket -> vga_sprite_7_s1_agent_rsp_fifo:in_endofpacket
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wire vga_sprite_7_s1_agent_rsp_fifo_out_valid; // vga_sprite_7_s1_agent_rsp_fifo:out_valid -> vga_sprite_7_s1_agent:rf_sink_valid
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wire [114:0] vga_sprite_7_s1_agent_rsp_fifo_out_data; // vga_sprite_7_s1_agent_rsp_fifo:out_data -> vga_sprite_7_s1_agent:rf_sink_data
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wire vga_sprite_7_s1_agent_rsp_fifo_out_ready; // vga_sprite_7_s1_agent:rf_sink_ready -> vga_sprite_7_s1_agent_rsp_fifo:out_ready
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wire vga_sprite_7_s1_agent_rsp_fifo_out_startofpacket; // vga_sprite_7_s1_agent_rsp_fifo:out_startofpacket -> vga_sprite_7_s1_agent:rf_sink_startofpacket
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wire vga_sprite_7_s1_agent_rsp_fifo_out_endofpacket; // vga_sprite_7_s1_agent_rsp_fifo:out_endofpacket -> vga_sprite_7_s1_agent:rf_sink_endofpacket
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wire cmd_mux_029_src_valid; // cmd_mux_029:src_valid -> vga_sprite_7_s1_agent:cp_valid
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wire [113:0] cmd_mux_029_src_data; // cmd_mux_029:src_data -> vga_sprite_7_s1_agent:cp_data
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wire cmd_mux_029_src_ready; // vga_sprite_7_s1_agent:cp_ready -> cmd_mux_029:src_ready
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wire [33:0] cmd_mux_029_src_channel; // cmd_mux_029:src_channel -> vga_sprite_7_s1_agent:cp_channel
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wire cmd_mux_029_src_startofpacket; // cmd_mux_029:src_startofpacket -> vga_sprite_7_s1_agent:cp_startofpacket
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wire cmd_mux_029_src_endofpacket; // cmd_mux_029:src_endofpacket -> vga_sprite_7_s1_agent:cp_endofpacket
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wire [31:0] vga_background_offset_s1_agent_m0_readdata; // vga_background_offset_s1_translator:uav_readdata -> vga_background_offset_s1_agent:m0_readdata
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wire vga_background_offset_s1_agent_m0_waitrequest; // vga_background_offset_s1_translator:uav_waitrequest -> vga_background_offset_s1_agent:m0_waitrequest
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wire vga_background_offset_s1_agent_m0_debugaccess; // vga_background_offset_s1_agent:m0_debugaccess -> vga_background_offset_s1_translator:uav_debugaccess
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wire [31:0] vga_background_offset_s1_agent_m0_address; // vga_background_offset_s1_agent:m0_address -> vga_background_offset_s1_translator:uav_address
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wire [3:0] vga_background_offset_s1_agent_m0_byteenable; // vga_background_offset_s1_agent:m0_byteenable -> vga_background_offset_s1_translator:uav_byteenable
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wire vga_background_offset_s1_agent_m0_read; // vga_background_offset_s1_agent:m0_read -> vga_background_offset_s1_translator:uav_read
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wire vga_background_offset_s1_agent_m0_readdatavalid; // vga_background_offset_s1_translator:uav_readdatavalid -> vga_background_offset_s1_agent:m0_readdatavalid
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wire vga_background_offset_s1_agent_m0_lock; // vga_background_offset_s1_agent:m0_lock -> vga_background_offset_s1_translator:uav_lock
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wire [31:0] vga_background_offset_s1_agent_m0_writedata; // vga_background_offset_s1_agent:m0_writedata -> vga_background_offset_s1_translator:uav_writedata
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wire vga_background_offset_s1_agent_m0_write; // vga_background_offset_s1_agent:m0_write -> vga_background_offset_s1_translator:uav_write
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wire [2:0] vga_background_offset_s1_agent_m0_burstcount; // vga_background_offset_s1_agent:m0_burstcount -> vga_background_offset_s1_translator:uav_burstcount
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wire vga_background_offset_s1_agent_rf_source_valid; // vga_background_offset_s1_agent:rf_source_valid -> vga_background_offset_s1_agent_rsp_fifo:in_valid
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wire [114:0] vga_background_offset_s1_agent_rf_source_data; // vga_background_offset_s1_agent:rf_source_data -> vga_background_offset_s1_agent_rsp_fifo:in_data
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wire vga_background_offset_s1_agent_rf_source_ready; // vga_background_offset_s1_agent_rsp_fifo:in_ready -> vga_background_offset_s1_agent:rf_source_ready
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wire vga_background_offset_s1_agent_rf_source_startofpacket; // vga_background_offset_s1_agent:rf_source_startofpacket -> vga_background_offset_s1_agent_rsp_fifo:in_startofpacket
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wire vga_background_offset_s1_agent_rf_source_endofpacket; // vga_background_offset_s1_agent:rf_source_endofpacket -> vga_background_offset_s1_agent_rsp_fifo:in_endofpacket
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wire vga_background_offset_s1_agent_rsp_fifo_out_valid; // vga_background_offset_s1_agent_rsp_fifo:out_valid -> vga_background_offset_s1_agent:rf_sink_valid
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wire [114:0] vga_background_offset_s1_agent_rsp_fifo_out_data; // vga_background_offset_s1_agent_rsp_fifo:out_data -> vga_background_offset_s1_agent:rf_sink_data
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wire vga_background_offset_s1_agent_rsp_fifo_out_ready; // vga_background_offset_s1_agent:rf_sink_ready -> vga_background_offset_s1_agent_rsp_fifo:out_ready
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wire vga_background_offset_s1_agent_rsp_fifo_out_startofpacket; // vga_background_offset_s1_agent_rsp_fifo:out_startofpacket -> vga_background_offset_s1_agent:rf_sink_startofpacket
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wire vga_background_offset_s1_agent_rsp_fifo_out_endofpacket; // vga_background_offset_s1_agent_rsp_fifo:out_endofpacket -> vga_background_offset_s1_agent:rf_sink_endofpacket
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wire cmd_mux_030_src_valid; // cmd_mux_030:src_valid -> vga_background_offset_s1_agent:cp_valid
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wire [113:0] cmd_mux_030_src_data; // cmd_mux_030:src_data -> vga_background_offset_s1_agent:cp_data
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wire cmd_mux_030_src_ready; // vga_background_offset_s1_agent:cp_ready -> cmd_mux_030:src_ready
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wire [33:0] cmd_mux_030_src_channel; // cmd_mux_030:src_channel -> vga_background_offset_s1_agent:cp_channel
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wire cmd_mux_030_src_startofpacket; // cmd_mux_030:src_startofpacket -> vga_background_offset_s1_agent:cp_startofpacket
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wire cmd_mux_030_src_endofpacket; // cmd_mux_030:src_endofpacket -> vga_background_offset_s1_agent:cp_endofpacket
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wire [31:0] audio_pio_s1_agent_m0_readdata; // audio_pio_s1_translator:uav_readdata -> audio_pio_s1_agent:m0_readdata
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wire audio_pio_s1_agent_m0_waitrequest; // audio_pio_s1_translator:uav_waitrequest -> audio_pio_s1_agent:m0_waitrequest
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wire audio_pio_s1_agent_m0_debugaccess; // audio_pio_s1_agent:m0_debugaccess -> audio_pio_s1_translator:uav_debugaccess
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wire [31:0] audio_pio_s1_agent_m0_address; // audio_pio_s1_agent:m0_address -> audio_pio_s1_translator:uav_address
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wire [3:0] audio_pio_s1_agent_m0_byteenable; // audio_pio_s1_agent:m0_byteenable -> audio_pio_s1_translator:uav_byteenable
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wire audio_pio_s1_agent_m0_read; // audio_pio_s1_agent:m0_read -> audio_pio_s1_translator:uav_read
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wire audio_pio_s1_agent_m0_readdatavalid; // audio_pio_s1_translator:uav_readdatavalid -> audio_pio_s1_agent:m0_readdatavalid
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wire audio_pio_s1_agent_m0_lock; // audio_pio_s1_agent:m0_lock -> audio_pio_s1_translator:uav_lock
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wire [31:0] audio_pio_s1_agent_m0_writedata; // audio_pio_s1_agent:m0_writedata -> audio_pio_s1_translator:uav_writedata
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wire audio_pio_s1_agent_m0_write; // audio_pio_s1_agent:m0_write -> audio_pio_s1_translator:uav_write
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wire [2:0] audio_pio_s1_agent_m0_burstcount; // audio_pio_s1_agent:m0_burstcount -> audio_pio_s1_translator:uav_burstcount
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wire audio_pio_s1_agent_rf_source_valid; // audio_pio_s1_agent:rf_source_valid -> audio_pio_s1_agent_rsp_fifo:in_valid
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wire [114:0] audio_pio_s1_agent_rf_source_data; // audio_pio_s1_agent:rf_source_data -> audio_pio_s1_agent_rsp_fifo:in_data
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wire audio_pio_s1_agent_rf_source_ready; // audio_pio_s1_agent_rsp_fifo:in_ready -> audio_pio_s1_agent:rf_source_ready
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wire audio_pio_s1_agent_rf_source_startofpacket; // audio_pio_s1_agent:rf_source_startofpacket -> audio_pio_s1_agent_rsp_fifo:in_startofpacket
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wire audio_pio_s1_agent_rf_source_endofpacket; // audio_pio_s1_agent:rf_source_endofpacket -> audio_pio_s1_agent_rsp_fifo:in_endofpacket
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wire audio_pio_s1_agent_rsp_fifo_out_valid; // audio_pio_s1_agent_rsp_fifo:out_valid -> audio_pio_s1_agent:rf_sink_valid
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wire [114:0] audio_pio_s1_agent_rsp_fifo_out_data; // audio_pio_s1_agent_rsp_fifo:out_data -> audio_pio_s1_agent:rf_sink_data
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wire audio_pio_s1_agent_rsp_fifo_out_ready; // audio_pio_s1_agent:rf_sink_ready -> audio_pio_s1_agent_rsp_fifo:out_ready
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wire audio_pio_s1_agent_rsp_fifo_out_startofpacket; // audio_pio_s1_agent_rsp_fifo:out_startofpacket -> audio_pio_s1_agent:rf_sink_startofpacket
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wire audio_pio_s1_agent_rsp_fifo_out_endofpacket; // audio_pio_s1_agent_rsp_fifo:out_endofpacket -> audio_pio_s1_agent:rf_sink_endofpacket
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wire cmd_mux_031_src_valid; // cmd_mux_031:src_valid -> audio_pio_s1_agent:cp_valid
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wire [113:0] cmd_mux_031_src_data; // cmd_mux_031:src_data -> audio_pio_s1_agent:cp_data
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wire cmd_mux_031_src_ready; // audio_pio_s1_agent:cp_ready -> cmd_mux_031:src_ready
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wire [33:0] cmd_mux_031_src_channel; // cmd_mux_031:src_channel -> audio_pio_s1_agent:cp_channel
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wire cmd_mux_031_src_startofpacket; // cmd_mux_031:src_startofpacket -> audio_pio_s1_agent:cp_startofpacket
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wire cmd_mux_031_src_endofpacket; // cmd_mux_031:src_endofpacket -> audio_pio_s1_agent:cp_endofpacket
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wire [31:0] audio_timer_s1_agent_m0_readdata; // audio_timer_s1_translator:uav_readdata -> audio_timer_s1_agent:m0_readdata
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wire audio_timer_s1_agent_m0_waitrequest; // audio_timer_s1_translator:uav_waitrequest -> audio_timer_s1_agent:m0_waitrequest
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wire audio_timer_s1_agent_m0_debugaccess; // audio_timer_s1_agent:m0_debugaccess -> audio_timer_s1_translator:uav_debugaccess
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wire [31:0] audio_timer_s1_agent_m0_address; // audio_timer_s1_agent:m0_address -> audio_timer_s1_translator:uav_address
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wire [3:0] audio_timer_s1_agent_m0_byteenable; // audio_timer_s1_agent:m0_byteenable -> audio_timer_s1_translator:uav_byteenable
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wire audio_timer_s1_agent_m0_read; // audio_timer_s1_agent:m0_read -> audio_timer_s1_translator:uav_read
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wire audio_timer_s1_agent_m0_readdatavalid; // audio_timer_s1_translator:uav_readdatavalid -> audio_timer_s1_agent:m0_readdatavalid
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wire audio_timer_s1_agent_m0_lock; // audio_timer_s1_agent:m0_lock -> audio_timer_s1_translator:uav_lock
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wire [31:0] audio_timer_s1_agent_m0_writedata; // audio_timer_s1_agent:m0_writedata -> audio_timer_s1_translator:uav_writedata
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wire audio_timer_s1_agent_m0_write; // audio_timer_s1_agent:m0_write -> audio_timer_s1_translator:uav_write
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wire [2:0] audio_timer_s1_agent_m0_burstcount; // audio_timer_s1_agent:m0_burstcount -> audio_timer_s1_translator:uav_burstcount
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wire audio_timer_s1_agent_rf_source_valid; // audio_timer_s1_agent:rf_source_valid -> audio_timer_s1_agent_rsp_fifo:in_valid
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wire [114:0] audio_timer_s1_agent_rf_source_data; // audio_timer_s1_agent:rf_source_data -> audio_timer_s1_agent_rsp_fifo:in_data
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wire audio_timer_s1_agent_rf_source_ready; // audio_timer_s1_agent_rsp_fifo:in_ready -> audio_timer_s1_agent:rf_source_ready
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wire audio_timer_s1_agent_rf_source_startofpacket; // audio_timer_s1_agent:rf_source_startofpacket -> audio_timer_s1_agent_rsp_fifo:in_startofpacket
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wire audio_timer_s1_agent_rf_source_endofpacket; // audio_timer_s1_agent:rf_source_endofpacket -> audio_timer_s1_agent_rsp_fifo:in_endofpacket
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wire audio_timer_s1_agent_rsp_fifo_out_valid; // audio_timer_s1_agent_rsp_fifo:out_valid -> audio_timer_s1_agent:rf_sink_valid
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wire [114:0] audio_timer_s1_agent_rsp_fifo_out_data; // audio_timer_s1_agent_rsp_fifo:out_data -> audio_timer_s1_agent:rf_sink_data
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wire audio_timer_s1_agent_rsp_fifo_out_ready; // audio_timer_s1_agent:rf_sink_ready -> audio_timer_s1_agent_rsp_fifo:out_ready
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wire audio_timer_s1_agent_rsp_fifo_out_startofpacket; // audio_timer_s1_agent_rsp_fifo:out_startofpacket -> audio_timer_s1_agent:rf_sink_startofpacket
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wire audio_timer_s1_agent_rsp_fifo_out_endofpacket; // audio_timer_s1_agent_rsp_fifo:out_endofpacket -> audio_timer_s1_agent:rf_sink_endofpacket
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wire cmd_mux_032_src_valid; // cmd_mux_032:src_valid -> audio_timer_s1_agent:cp_valid
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wire [113:0] cmd_mux_032_src_data; // cmd_mux_032:src_data -> audio_timer_s1_agent:cp_data
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wire cmd_mux_032_src_ready; // audio_timer_s1_agent:cp_ready -> cmd_mux_032:src_ready
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wire [33:0] cmd_mux_032_src_channel; // cmd_mux_032:src_channel -> audio_timer_s1_agent:cp_channel
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wire cmd_mux_032_src_startofpacket; // cmd_mux_032:src_startofpacket -> audio_timer_s1_agent:cp_startofpacket
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wire cmd_mux_032_src_endofpacket; // cmd_mux_032:src_endofpacket -> audio_timer_s1_agent:cp_endofpacket
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wire [31:0] usb_keycode_s2_agent_m0_readdata; // usb_keycode_s2_translator:uav_readdata -> usb_keycode_s2_agent:m0_readdata
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wire usb_keycode_s2_agent_m0_waitrequest; // usb_keycode_s2_translator:uav_waitrequest -> usb_keycode_s2_agent:m0_waitrequest
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wire usb_keycode_s2_agent_m0_debugaccess; // usb_keycode_s2_agent:m0_debugaccess -> usb_keycode_s2_translator:uav_debugaccess
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wire [31:0] usb_keycode_s2_agent_m0_address; // usb_keycode_s2_agent:m0_address -> usb_keycode_s2_translator:uav_address
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wire [3:0] usb_keycode_s2_agent_m0_byteenable; // usb_keycode_s2_agent:m0_byteenable -> usb_keycode_s2_translator:uav_byteenable
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wire usb_keycode_s2_agent_m0_read; // usb_keycode_s2_agent:m0_read -> usb_keycode_s2_translator:uav_read
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wire usb_keycode_s2_agent_m0_readdatavalid; // usb_keycode_s2_translator:uav_readdatavalid -> usb_keycode_s2_agent:m0_readdatavalid
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wire usb_keycode_s2_agent_m0_lock; // usb_keycode_s2_agent:m0_lock -> usb_keycode_s2_translator:uav_lock
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wire [31:0] usb_keycode_s2_agent_m0_writedata; // usb_keycode_s2_agent:m0_writedata -> usb_keycode_s2_translator:uav_writedata
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wire usb_keycode_s2_agent_m0_write; // usb_keycode_s2_agent:m0_write -> usb_keycode_s2_translator:uav_write
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wire [2:0] usb_keycode_s2_agent_m0_burstcount; // usb_keycode_s2_agent:m0_burstcount -> usb_keycode_s2_translator:uav_burstcount
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wire usb_keycode_s2_agent_rf_source_valid; // usb_keycode_s2_agent:rf_source_valid -> usb_keycode_s2_agent_rsp_fifo:in_valid
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wire [114:0] usb_keycode_s2_agent_rf_source_data; // usb_keycode_s2_agent:rf_source_data -> usb_keycode_s2_agent_rsp_fifo:in_data
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wire usb_keycode_s2_agent_rf_source_ready; // usb_keycode_s2_agent_rsp_fifo:in_ready -> usb_keycode_s2_agent:rf_source_ready
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wire usb_keycode_s2_agent_rf_source_startofpacket; // usb_keycode_s2_agent:rf_source_startofpacket -> usb_keycode_s2_agent_rsp_fifo:in_startofpacket
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wire usb_keycode_s2_agent_rf_source_endofpacket; // usb_keycode_s2_agent:rf_source_endofpacket -> usb_keycode_s2_agent_rsp_fifo:in_endofpacket
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wire usb_keycode_s2_agent_rsp_fifo_out_valid; // usb_keycode_s2_agent_rsp_fifo:out_valid -> usb_keycode_s2_agent:rf_sink_valid
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wire [114:0] usb_keycode_s2_agent_rsp_fifo_out_data; // usb_keycode_s2_agent_rsp_fifo:out_data -> usb_keycode_s2_agent:rf_sink_data
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wire usb_keycode_s2_agent_rsp_fifo_out_ready; // usb_keycode_s2_agent:rf_sink_ready -> usb_keycode_s2_agent_rsp_fifo:out_ready
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wire usb_keycode_s2_agent_rsp_fifo_out_startofpacket; // usb_keycode_s2_agent_rsp_fifo:out_startofpacket -> usb_keycode_s2_agent:rf_sink_startofpacket
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wire usb_keycode_s2_agent_rsp_fifo_out_endofpacket; // usb_keycode_s2_agent_rsp_fifo:out_endofpacket -> usb_keycode_s2_agent:rf_sink_endofpacket
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wire cmd_mux_033_src_valid; // cmd_mux_033:src_valid -> usb_keycode_s2_agent:cp_valid
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wire [113:0] cmd_mux_033_src_data; // cmd_mux_033:src_data -> usb_keycode_s2_agent:cp_data
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wire cmd_mux_033_src_ready; // usb_keycode_s2_agent:cp_ready -> cmd_mux_033:src_ready
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wire [33:0] cmd_mux_033_src_channel; // cmd_mux_033:src_channel -> usb_keycode_s2_agent:cp_channel
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wire cmd_mux_033_src_startofpacket; // cmd_mux_033:src_startofpacket -> usb_keycode_s2_agent:cp_startofpacket
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wire cmd_mux_033_src_endofpacket; // cmd_mux_033:src_endofpacket -> usb_keycode_s2_agent:cp_endofpacket
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wire nios2_cpu_data_master_agent_cp_valid; // nios2_cpu_data_master_agent:cp_valid -> router:sink_valid
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wire [113:0] nios2_cpu_data_master_agent_cp_data; // nios2_cpu_data_master_agent:cp_data -> router:sink_data
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wire nios2_cpu_data_master_agent_cp_ready; // router:sink_ready -> nios2_cpu_data_master_agent:cp_ready
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wire nios2_cpu_data_master_agent_cp_startofpacket; // nios2_cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
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wire nios2_cpu_data_master_agent_cp_endofpacket; // nios2_cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
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wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
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wire [113:0] router_src_data; // router:src_data -> cmd_demux:sink_data
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wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
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wire [33:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
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wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
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wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
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wire nios2_dma_m_read_agent_cp_valid; // nios2_dma_m_read_agent:cp_valid -> router_001:sink_valid
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wire [113:0] nios2_dma_m_read_agent_cp_data; // nios2_dma_m_read_agent:cp_data -> router_001:sink_data
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wire nios2_dma_m_read_agent_cp_ready; // router_001:sink_ready -> nios2_dma_m_read_agent:cp_ready
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wire nios2_dma_m_read_agent_cp_startofpacket; // nios2_dma_m_read_agent:cp_startofpacket -> router_001:sink_startofpacket
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wire nios2_dma_m_read_agent_cp_endofpacket; // nios2_dma_m_read_agent:cp_endofpacket -> router_001:sink_endofpacket
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wire nios2_dma_m_write_agent_cp_valid; // nios2_dma_m_write_agent:cp_valid -> router_002:sink_valid
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wire [113:0] nios2_dma_m_write_agent_cp_data; // nios2_dma_m_write_agent:cp_data -> router_002:sink_data
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wire nios2_dma_m_write_agent_cp_ready; // router_002:sink_ready -> nios2_dma_m_write_agent:cp_ready
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wire nios2_dma_m_write_agent_cp_startofpacket; // nios2_dma_m_write_agent:cp_startofpacket -> router_002:sink_startofpacket
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wire nios2_dma_m_write_agent_cp_endofpacket; // nios2_dma_m_write_agent:cp_endofpacket -> router_002:sink_endofpacket
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wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid
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wire [113:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data
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wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready
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wire [33:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel
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wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
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wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
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wire nios2_cpu_instruction_master_agent_cp_valid; // nios2_cpu_instruction_master_agent:cp_valid -> router_003:sink_valid
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wire [113:0] nios2_cpu_instruction_master_agent_cp_data; // nios2_cpu_instruction_master_agent:cp_data -> router_003:sink_data
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wire nios2_cpu_instruction_master_agent_cp_ready; // router_003:sink_ready -> nios2_cpu_instruction_master_agent:cp_ready
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wire nios2_cpu_instruction_master_agent_cp_startofpacket; // nios2_cpu_instruction_master_agent:cp_startofpacket -> router_003:sink_startofpacket
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wire nios2_cpu_instruction_master_agent_cp_endofpacket; // nios2_cpu_instruction_master_agent:cp_endofpacket -> router_003:sink_endofpacket
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wire router_003_src_valid; // router_003:src_valid -> cmd_demux_003:sink_valid
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wire [113:0] router_003_src_data; // router_003:src_data -> cmd_demux_003:sink_data
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wire router_003_src_ready; // cmd_demux_003:sink_ready -> router_003:src_ready
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wire [33:0] router_003_src_channel; // router_003:src_channel -> cmd_demux_003:sink_channel
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wire router_003_src_startofpacket; // router_003:src_startofpacket -> cmd_demux_003:sink_startofpacket
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wire router_003_src_endofpacket; // router_003:src_endofpacket -> cmd_demux_003:sink_endofpacket
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rp_valid; // nios2_jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_004:sink_valid
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wire [113:0] nios2_jtag_uart_avalon_jtag_slave_agent_rp_data; // nios2_jtag_uart_avalon_jtag_slave_agent:rp_data -> router_004:sink_data
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_004:sink_ready -> nios2_jtag_uart_avalon_jtag_slave_agent:rp_ready
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // nios2_jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // nios2_jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
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wire router_004_src_valid; // router_004:src_valid -> rsp_demux:sink_valid
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wire [113:0] router_004_src_data; // router_004:src_data -> rsp_demux:sink_data
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wire router_004_src_ready; // rsp_demux:sink_ready -> router_004:src_ready
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wire [33:0] router_004_src_channel; // router_004:src_channel -> rsp_demux:sink_channel
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wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux:sink_startofpacket
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wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux:sink_endofpacket
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wire eth1_mdio_avalon_slave_agent_rp_valid; // eth1_mdio_avalon_slave_agent:rp_valid -> router_005:sink_valid
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wire [113:0] eth1_mdio_avalon_slave_agent_rp_data; // eth1_mdio_avalon_slave_agent:rp_data -> router_005:sink_data
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wire eth1_mdio_avalon_slave_agent_rp_ready; // router_005:sink_ready -> eth1_mdio_avalon_slave_agent:rp_ready
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wire eth1_mdio_avalon_slave_agent_rp_startofpacket; // eth1_mdio_avalon_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
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wire eth1_mdio_avalon_slave_agent_rp_endofpacket; // eth1_mdio_avalon_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
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wire router_005_src_valid; // router_005:src_valid -> rsp_demux_001:sink_valid
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wire [113:0] router_005_src_data; // router_005:src_data -> rsp_demux_001:sink_data
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wire router_005_src_ready; // rsp_demux_001:sink_ready -> router_005:src_ready
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wire [33:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_001:sink_channel
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wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_001:sink_startofpacket
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wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_001:sink_endofpacket
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wire eth0_mdio_avalon_slave_agent_rp_valid; // eth0_mdio_avalon_slave_agent:rp_valid -> router_006:sink_valid
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wire [113:0] eth0_mdio_avalon_slave_agent_rp_data; // eth0_mdio_avalon_slave_agent:rp_data -> router_006:sink_data
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wire eth0_mdio_avalon_slave_agent_rp_ready; // router_006:sink_ready -> eth0_mdio_avalon_slave_agent:rp_ready
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wire eth0_mdio_avalon_slave_agent_rp_startofpacket; // eth0_mdio_avalon_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
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wire eth0_mdio_avalon_slave_agent_rp_endofpacket; // eth0_mdio_avalon_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
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wire router_006_src_valid; // router_006:src_valid -> rsp_demux_002:sink_valid
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wire [113:0] router_006_src_data; // router_006:src_data -> rsp_demux_002:sink_data
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wire router_006_src_ready; // rsp_demux_002:sink_ready -> router_006:src_ready
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wire [33:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_002:sink_channel
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wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_002:sink_startofpacket
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wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_002:sink_endofpacket
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wire sram_multiplexer_avl_agent_rp_valid; // sram_multiplexer_avl_agent:rp_valid -> router_007:sink_valid
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wire [95:0] sram_multiplexer_avl_agent_rp_data; // sram_multiplexer_avl_agent:rp_data -> router_007:sink_data
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wire sram_multiplexer_avl_agent_rp_ready; // router_007:sink_ready -> sram_multiplexer_avl_agent:rp_ready
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wire sram_multiplexer_avl_agent_rp_startofpacket; // sram_multiplexer_avl_agent:rp_startofpacket -> router_007:sink_startofpacket
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wire sram_multiplexer_avl_agent_rp_endofpacket; // sram_multiplexer_avl_agent:rp_endofpacket -> router_007:sink_endofpacket
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wire vga_sprite_params_avl_agent_rp_valid; // vga_sprite_params_avl_agent:rp_valid -> router_008:sink_valid
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wire [113:0] vga_sprite_params_avl_agent_rp_data; // vga_sprite_params_avl_agent:rp_data -> router_008:sink_data
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wire vga_sprite_params_avl_agent_rp_ready; // router_008:sink_ready -> vga_sprite_params_avl_agent:rp_ready
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wire vga_sprite_params_avl_agent_rp_startofpacket; // vga_sprite_params_avl_agent:rp_startofpacket -> router_008:sink_startofpacket
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wire vga_sprite_params_avl_agent_rp_endofpacket; // vga_sprite_params_avl_agent:rp_endofpacket -> router_008:sink_endofpacket
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wire router_008_src_valid; // router_008:src_valid -> rsp_demux_004:sink_valid
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wire [113:0] router_008_src_data; // router_008:src_data -> rsp_demux_004:sink_data
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wire router_008_src_ready; // rsp_demux_004:sink_ready -> router_008:src_ready
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wire [33:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_004:sink_channel
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wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_004:sink_startofpacket
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wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_004:sink_endofpacket
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wire nios2_sysid_control_slave_agent_rp_valid; // nios2_sysid_control_slave_agent:rp_valid -> router_009:sink_valid
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wire [113:0] nios2_sysid_control_slave_agent_rp_data; // nios2_sysid_control_slave_agent:rp_data -> router_009:sink_data
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wire nios2_sysid_control_slave_agent_rp_ready; // router_009:sink_ready -> nios2_sysid_control_slave_agent:rp_ready
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wire nios2_sysid_control_slave_agent_rp_startofpacket; // nios2_sysid_control_slave_agent:rp_startofpacket -> router_009:sink_startofpacket
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wire nios2_sysid_control_slave_agent_rp_endofpacket; // nios2_sysid_control_slave_agent:rp_endofpacket -> router_009:sink_endofpacket
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wire router_009_src_valid; // router_009:src_valid -> rsp_demux_005:sink_valid
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wire [113:0] router_009_src_data; // router_009:src_data -> rsp_demux_005:sink_data
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wire router_009_src_ready; // rsp_demux_005:sink_ready -> router_009:src_ready
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wire [33:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_005:sink_channel
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wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_005:sink_startofpacket
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wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_005:sink_endofpacket
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wire eth0_rx_dma_csr_agent_rp_valid; // eth0_rx_dma_csr_agent:rp_valid -> router_010:sink_valid
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wire [113:0] eth0_rx_dma_csr_agent_rp_data; // eth0_rx_dma_csr_agent:rp_data -> router_010:sink_data
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wire eth0_rx_dma_csr_agent_rp_ready; // router_010:sink_ready -> eth0_rx_dma_csr_agent:rp_ready
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wire eth0_rx_dma_csr_agent_rp_startofpacket; // eth0_rx_dma_csr_agent:rp_startofpacket -> router_010:sink_startofpacket
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wire eth0_rx_dma_csr_agent_rp_endofpacket; // eth0_rx_dma_csr_agent:rp_endofpacket -> router_010:sink_endofpacket
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wire router_010_src_valid; // router_010:src_valid -> rsp_demux_006:sink_valid
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wire [113:0] router_010_src_data; // router_010:src_data -> rsp_demux_006:sink_data
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wire router_010_src_ready; // rsp_demux_006:sink_ready -> router_010:src_ready
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wire [33:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_006:sink_channel
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wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_006:sink_startofpacket
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wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_006:sink_endofpacket
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wire eth0_tx_dma_csr_agent_rp_valid; // eth0_tx_dma_csr_agent:rp_valid -> router_011:sink_valid
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wire [113:0] eth0_tx_dma_csr_agent_rp_data; // eth0_tx_dma_csr_agent:rp_data -> router_011:sink_data
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wire eth0_tx_dma_csr_agent_rp_ready; // router_011:sink_ready -> eth0_tx_dma_csr_agent:rp_ready
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wire eth0_tx_dma_csr_agent_rp_startofpacket; // eth0_tx_dma_csr_agent:rp_startofpacket -> router_011:sink_startofpacket
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wire eth0_tx_dma_csr_agent_rp_endofpacket; // eth0_tx_dma_csr_agent:rp_endofpacket -> router_011:sink_endofpacket
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wire router_011_src_valid; // router_011:src_valid -> rsp_demux_007:sink_valid
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wire [113:0] router_011_src_data; // router_011:src_data -> rsp_demux_007:sink_data
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wire router_011_src_ready; // rsp_demux_007:sink_ready -> router_011:src_ready
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wire [33:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_007:sink_channel
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wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_007:sink_startofpacket
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wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_007:sink_endofpacket
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wire eth1_rx_dma_csr_agent_rp_valid; // eth1_rx_dma_csr_agent:rp_valid -> router_012:sink_valid
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wire [113:0] eth1_rx_dma_csr_agent_rp_data; // eth1_rx_dma_csr_agent:rp_data -> router_012:sink_data
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wire eth1_rx_dma_csr_agent_rp_ready; // router_012:sink_ready -> eth1_rx_dma_csr_agent:rp_ready
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wire eth1_rx_dma_csr_agent_rp_startofpacket; // eth1_rx_dma_csr_agent:rp_startofpacket -> router_012:sink_startofpacket
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wire eth1_rx_dma_csr_agent_rp_endofpacket; // eth1_rx_dma_csr_agent:rp_endofpacket -> router_012:sink_endofpacket
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wire router_012_src_valid; // router_012:src_valid -> rsp_demux_008:sink_valid
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wire [113:0] router_012_src_data; // router_012:src_data -> rsp_demux_008:sink_data
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wire router_012_src_ready; // rsp_demux_008:sink_ready -> router_012:src_ready
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wire [33:0] router_012_src_channel; // router_012:src_channel -> rsp_demux_008:sink_channel
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wire router_012_src_startofpacket; // router_012:src_startofpacket -> rsp_demux_008:sink_startofpacket
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wire router_012_src_endofpacket; // router_012:src_endofpacket -> rsp_demux_008:sink_endofpacket
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wire eth1_tx_dma_csr_agent_rp_valid; // eth1_tx_dma_csr_agent:rp_valid -> router_013:sink_valid
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wire [113:0] eth1_tx_dma_csr_agent_rp_data; // eth1_tx_dma_csr_agent:rp_data -> router_013:sink_data
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wire eth1_tx_dma_csr_agent_rp_ready; // router_013:sink_ready -> eth1_tx_dma_csr_agent:rp_ready
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wire eth1_tx_dma_csr_agent_rp_startofpacket; // eth1_tx_dma_csr_agent:rp_startofpacket -> router_013:sink_startofpacket
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wire eth1_tx_dma_csr_agent_rp_endofpacket; // eth1_tx_dma_csr_agent:rp_endofpacket -> router_013:sink_endofpacket
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wire router_013_src_valid; // router_013:src_valid -> rsp_demux_009:sink_valid
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wire [113:0] router_013_src_data; // router_013:src_data -> rsp_demux_009:sink_data
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wire router_013_src_ready; // rsp_demux_009:sink_ready -> router_013:src_ready
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wire [33:0] router_013_src_channel; // router_013:src_channel -> rsp_demux_009:sink_channel
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wire router_013_src_startofpacket; // router_013:src_startofpacket -> rsp_demux_009:sink_startofpacket
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wire router_013_src_endofpacket; // router_013:src_endofpacket -> rsp_demux_009:sink_endofpacket
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wire nios2_dma_csr_agent_rp_valid; // nios2_dma_csr_agent:rp_valid -> router_014:sink_valid
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wire [113:0] nios2_dma_csr_agent_rp_data; // nios2_dma_csr_agent:rp_data -> router_014:sink_data
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wire nios2_dma_csr_agent_rp_ready; // router_014:sink_ready -> nios2_dma_csr_agent:rp_ready
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wire nios2_dma_csr_agent_rp_startofpacket; // nios2_dma_csr_agent:rp_startofpacket -> router_014:sink_startofpacket
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wire nios2_dma_csr_agent_rp_endofpacket; // nios2_dma_csr_agent:rp_endofpacket -> router_014:sink_endofpacket
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wire router_014_src_valid; // router_014:src_valid -> rsp_demux_010:sink_valid
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wire [113:0] router_014_src_data; // router_014:src_data -> rsp_demux_010:sink_data
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wire router_014_src_ready; // rsp_demux_010:sink_ready -> router_014:src_ready
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wire [33:0] router_014_src_channel; // router_014:src_channel -> rsp_demux_010:sink_channel
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wire router_014_src_startofpacket; // router_014:src_startofpacket -> rsp_demux_010:sink_startofpacket
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wire router_014_src_endofpacket; // router_014:src_endofpacket -> rsp_demux_010:sink_endofpacket
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wire nios2_cpu_debug_mem_slave_agent_rp_valid; // nios2_cpu_debug_mem_slave_agent:rp_valid -> router_015:sink_valid
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wire [113:0] nios2_cpu_debug_mem_slave_agent_rp_data; // nios2_cpu_debug_mem_slave_agent:rp_data -> router_015:sink_data
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wire nios2_cpu_debug_mem_slave_agent_rp_ready; // router_015:sink_ready -> nios2_cpu_debug_mem_slave_agent:rp_ready
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wire nios2_cpu_debug_mem_slave_agent_rp_startofpacket; // nios2_cpu_debug_mem_slave_agent:rp_startofpacket -> router_015:sink_startofpacket
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wire nios2_cpu_debug_mem_slave_agent_rp_endofpacket; // nios2_cpu_debug_mem_slave_agent:rp_endofpacket -> router_015:sink_endofpacket
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wire router_015_src_valid; // router_015:src_valid -> rsp_demux_011:sink_valid
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wire [113:0] router_015_src_data; // router_015:src_data -> rsp_demux_011:sink_data
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wire router_015_src_ready; // rsp_demux_011:sink_ready -> router_015:src_ready
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wire [33:0] router_015_src_channel; // router_015:src_channel -> rsp_demux_011:sink_channel
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wire router_015_src_startofpacket; // router_015:src_startofpacket -> rsp_demux_011:sink_startofpacket
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wire router_015_src_endofpacket; // router_015:src_endofpacket -> rsp_demux_011:sink_endofpacket
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wire nios2_pll_pll_slave_agent_rp_valid; // nios2_pll_pll_slave_agent:rp_valid -> router_016:sink_valid
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wire [113:0] nios2_pll_pll_slave_agent_rp_data; // nios2_pll_pll_slave_agent:rp_data -> router_016:sink_data
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wire nios2_pll_pll_slave_agent_rp_ready; // router_016:sink_ready -> nios2_pll_pll_slave_agent:rp_ready
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wire nios2_pll_pll_slave_agent_rp_startofpacket; // nios2_pll_pll_slave_agent:rp_startofpacket -> router_016:sink_startofpacket
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wire nios2_pll_pll_slave_agent_rp_endofpacket; // nios2_pll_pll_slave_agent:rp_endofpacket -> router_016:sink_endofpacket
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wire router_016_src_valid; // router_016:src_valid -> rsp_demux_012:sink_valid
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wire [113:0] router_016_src_data; // router_016:src_data -> rsp_demux_012:sink_data
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wire router_016_src_ready; // rsp_demux_012:sink_ready -> router_016:src_ready
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wire [33:0] router_016_src_channel; // router_016:src_channel -> rsp_demux_012:sink_channel
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wire router_016_src_startofpacket; // router_016:src_startofpacket -> rsp_demux_012:sink_startofpacket
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wire router_016_src_endofpacket; // router_016:src_endofpacket -> rsp_demux_012:sink_endofpacket
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wire nios2_onchip_mem_s1_agent_rp_valid; // nios2_onchip_mem_s1_agent:rp_valid -> router_017:sink_valid
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wire [113:0] nios2_onchip_mem_s1_agent_rp_data; // nios2_onchip_mem_s1_agent:rp_data -> router_017:sink_data
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wire nios2_onchip_mem_s1_agent_rp_ready; // router_017:sink_ready -> nios2_onchip_mem_s1_agent:rp_ready
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wire nios2_onchip_mem_s1_agent_rp_startofpacket; // nios2_onchip_mem_s1_agent:rp_startofpacket -> router_017:sink_startofpacket
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wire nios2_onchip_mem_s1_agent_rp_endofpacket; // nios2_onchip_mem_s1_agent:rp_endofpacket -> router_017:sink_endofpacket
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wire router_017_src_valid; // router_017:src_valid -> rsp_demux_013:sink_valid
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wire [113:0] router_017_src_data; // router_017:src_data -> rsp_demux_013:sink_data
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wire router_017_src_ready; // rsp_demux_013:sink_ready -> router_017:src_ready
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wire [33:0] router_017_src_channel; // router_017:src_channel -> rsp_demux_013:sink_channel
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wire router_017_src_startofpacket; // router_017:src_startofpacket -> rsp_demux_013:sink_startofpacket
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wire router_017_src_endofpacket; // router_017:src_endofpacket -> rsp_demux_013:sink_endofpacket
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wire sdram_s1_agent_rp_valid; // sdram_s1_agent:rp_valid -> router_018:sink_valid
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wire [113:0] sdram_s1_agent_rp_data; // sdram_s1_agent:rp_data -> router_018:sink_data
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wire sdram_s1_agent_rp_ready; // router_018:sink_ready -> sdram_s1_agent:rp_ready
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wire sdram_s1_agent_rp_startofpacket; // sdram_s1_agent:rp_startofpacket -> router_018:sink_startofpacket
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wire sdram_s1_agent_rp_endofpacket; // sdram_s1_agent:rp_endofpacket -> router_018:sink_endofpacket
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wire router_018_src_valid; // router_018:src_valid -> rsp_demux_014:sink_valid
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wire [113:0] router_018_src_data; // router_018:src_data -> rsp_demux_014:sink_data
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wire router_018_src_ready; // rsp_demux_014:sink_ready -> router_018:src_ready
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wire [33:0] router_018_src_channel; // router_018:src_channel -> rsp_demux_014:sink_channel
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wire router_018_src_startofpacket; // router_018:src_startofpacket -> rsp_demux_014:sink_startofpacket
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wire router_018_src_endofpacket; // router_018:src_endofpacket -> rsp_demux_014:sink_endofpacket
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wire io_led_red_s1_agent_rp_valid; // io_led_red_s1_agent:rp_valid -> router_019:sink_valid
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wire [113:0] io_led_red_s1_agent_rp_data; // io_led_red_s1_agent:rp_data -> router_019:sink_data
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wire io_led_red_s1_agent_rp_ready; // router_019:sink_ready -> io_led_red_s1_agent:rp_ready
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wire io_led_red_s1_agent_rp_startofpacket; // io_led_red_s1_agent:rp_startofpacket -> router_019:sink_startofpacket
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wire io_led_red_s1_agent_rp_endofpacket; // io_led_red_s1_agent:rp_endofpacket -> router_019:sink_endofpacket
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wire router_019_src_valid; // router_019:src_valid -> rsp_demux_015:sink_valid
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wire [113:0] router_019_src_data; // router_019:src_data -> rsp_demux_015:sink_data
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wire router_019_src_ready; // rsp_demux_015:sink_ready -> router_019:src_ready
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wire [33:0] router_019_src_channel; // router_019:src_channel -> rsp_demux_015:sink_channel
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wire router_019_src_startofpacket; // router_019:src_startofpacket -> rsp_demux_015:sink_startofpacket
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wire router_019_src_endofpacket; // router_019:src_endofpacket -> rsp_demux_015:sink_endofpacket
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wire nios2_timer_s1_agent_rp_valid; // nios2_timer_s1_agent:rp_valid -> router_020:sink_valid
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wire [113:0] nios2_timer_s1_agent_rp_data; // nios2_timer_s1_agent:rp_data -> router_020:sink_data
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wire nios2_timer_s1_agent_rp_ready; // router_020:sink_ready -> nios2_timer_s1_agent:rp_ready
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wire nios2_timer_s1_agent_rp_startofpacket; // nios2_timer_s1_agent:rp_startofpacket -> router_020:sink_startofpacket
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wire nios2_timer_s1_agent_rp_endofpacket; // nios2_timer_s1_agent:rp_endofpacket -> router_020:sink_endofpacket
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wire router_020_src_valid; // router_020:src_valid -> rsp_demux_016:sink_valid
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wire [113:0] router_020_src_data; // router_020:src_data -> rsp_demux_016:sink_data
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wire router_020_src_ready; // rsp_demux_016:sink_ready -> router_020:src_ready
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wire [33:0] router_020_src_channel; // router_020:src_channel -> rsp_demux_016:sink_channel
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wire router_020_src_startofpacket; // router_020:src_startofpacket -> rsp_demux_016:sink_startofpacket
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wire router_020_src_endofpacket; // router_020:src_endofpacket -> rsp_demux_016:sink_endofpacket
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wire io_keys_s1_agent_rp_valid; // io_keys_s1_agent:rp_valid -> router_021:sink_valid
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wire [113:0] io_keys_s1_agent_rp_data; // io_keys_s1_agent:rp_data -> router_021:sink_data
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wire io_keys_s1_agent_rp_ready; // router_021:sink_ready -> io_keys_s1_agent:rp_ready
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wire io_keys_s1_agent_rp_startofpacket; // io_keys_s1_agent:rp_startofpacket -> router_021:sink_startofpacket
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wire io_keys_s1_agent_rp_endofpacket; // io_keys_s1_agent:rp_endofpacket -> router_021:sink_endofpacket
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wire router_021_src_valid; // router_021:src_valid -> rsp_demux_017:sink_valid
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wire [113:0] router_021_src_data; // router_021:src_data -> rsp_demux_017:sink_data
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wire router_021_src_ready; // rsp_demux_017:sink_ready -> router_021:src_ready
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wire [33:0] router_021_src_channel; // router_021:src_channel -> rsp_demux_017:sink_channel
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wire router_021_src_startofpacket; // router_021:src_startofpacket -> rsp_demux_017:sink_startofpacket
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wire router_021_src_endofpacket; // router_021:src_endofpacket -> rsp_demux_017:sink_endofpacket
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wire io_switches_s1_agent_rp_valid; // io_switches_s1_agent:rp_valid -> router_022:sink_valid
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wire [113:0] io_switches_s1_agent_rp_data; // io_switches_s1_agent:rp_data -> router_022:sink_data
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wire io_switches_s1_agent_rp_ready; // router_022:sink_ready -> io_switches_s1_agent:rp_ready
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wire io_switches_s1_agent_rp_startofpacket; // io_switches_s1_agent:rp_startofpacket -> router_022:sink_startofpacket
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wire io_switches_s1_agent_rp_endofpacket; // io_switches_s1_agent:rp_endofpacket -> router_022:sink_endofpacket
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wire router_022_src_valid; // router_022:src_valid -> rsp_demux_018:sink_valid
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wire [113:0] router_022_src_data; // router_022:src_data -> rsp_demux_018:sink_data
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wire router_022_src_ready; // rsp_demux_018:sink_ready -> router_022:src_ready
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wire [33:0] router_022_src_channel; // router_022:src_channel -> rsp_demux_018:sink_channel
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wire router_022_src_startofpacket; // router_022:src_startofpacket -> rsp_demux_018:sink_startofpacket
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wire router_022_src_endofpacket; // router_022:src_endofpacket -> rsp_demux_018:sink_endofpacket
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wire io_led_green_s1_agent_rp_valid; // io_led_green_s1_agent:rp_valid -> router_023:sink_valid
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wire [113:0] io_led_green_s1_agent_rp_data; // io_led_green_s1_agent:rp_data -> router_023:sink_data
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wire io_led_green_s1_agent_rp_ready; // router_023:sink_ready -> io_led_green_s1_agent:rp_ready
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wire io_led_green_s1_agent_rp_startofpacket; // io_led_green_s1_agent:rp_startofpacket -> router_023:sink_startofpacket
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wire io_led_green_s1_agent_rp_endofpacket; // io_led_green_s1_agent:rp_endofpacket -> router_023:sink_endofpacket
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wire router_023_src_valid; // router_023:src_valid -> rsp_demux_019:sink_valid
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wire [113:0] router_023_src_data; // router_023:src_data -> rsp_demux_019:sink_data
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wire router_023_src_ready; // rsp_demux_019:sink_ready -> router_023:src_ready
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wire [33:0] router_023_src_channel; // router_023:src_channel -> rsp_demux_019:sink_channel
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wire router_023_src_startofpacket; // router_023:src_startofpacket -> rsp_demux_019:sink_startofpacket
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wire router_023_src_endofpacket; // router_023:src_endofpacket -> rsp_demux_019:sink_endofpacket
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wire io_hex_s1_agent_rp_valid; // io_hex_s1_agent:rp_valid -> router_024:sink_valid
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wire [113:0] io_hex_s1_agent_rp_data; // io_hex_s1_agent:rp_data -> router_024:sink_data
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wire io_hex_s1_agent_rp_ready; // router_024:sink_ready -> io_hex_s1_agent:rp_ready
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wire io_hex_s1_agent_rp_startofpacket; // io_hex_s1_agent:rp_startofpacket -> router_024:sink_startofpacket
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wire io_hex_s1_agent_rp_endofpacket; // io_hex_s1_agent:rp_endofpacket -> router_024:sink_endofpacket
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wire router_024_src_valid; // router_024:src_valid -> rsp_demux_020:sink_valid
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wire [113:0] router_024_src_data; // router_024:src_data -> rsp_demux_020:sink_data
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wire router_024_src_ready; // rsp_demux_020:sink_ready -> router_024:src_ready
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wire [33:0] router_024_src_channel; // router_024:src_channel -> rsp_demux_020:sink_channel
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wire router_024_src_startofpacket; // router_024:src_startofpacket -> rsp_demux_020:sink_startofpacket
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wire router_024_src_endofpacket; // router_024:src_endofpacket -> rsp_demux_020:sink_endofpacket
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wire vga_sprite_0_s1_agent_rp_valid; // vga_sprite_0_s1_agent:rp_valid -> router_025:sink_valid
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wire [113:0] vga_sprite_0_s1_agent_rp_data; // vga_sprite_0_s1_agent:rp_data -> router_025:sink_data
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wire vga_sprite_0_s1_agent_rp_ready; // router_025:sink_ready -> vga_sprite_0_s1_agent:rp_ready
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wire vga_sprite_0_s1_agent_rp_startofpacket; // vga_sprite_0_s1_agent:rp_startofpacket -> router_025:sink_startofpacket
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wire vga_sprite_0_s1_agent_rp_endofpacket; // vga_sprite_0_s1_agent:rp_endofpacket -> router_025:sink_endofpacket
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wire router_025_src_valid; // router_025:src_valid -> rsp_demux_021:sink_valid
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wire [113:0] router_025_src_data; // router_025:src_data -> rsp_demux_021:sink_data
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wire router_025_src_ready; // rsp_demux_021:sink_ready -> router_025:src_ready
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wire [33:0] router_025_src_channel; // router_025:src_channel -> rsp_demux_021:sink_channel
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wire router_025_src_startofpacket; // router_025:src_startofpacket -> rsp_demux_021:sink_startofpacket
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wire router_025_src_endofpacket; // router_025:src_endofpacket -> rsp_demux_021:sink_endofpacket
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wire vga_sprite_1_s1_agent_rp_valid; // vga_sprite_1_s1_agent:rp_valid -> router_026:sink_valid
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wire [113:0] vga_sprite_1_s1_agent_rp_data; // vga_sprite_1_s1_agent:rp_data -> router_026:sink_data
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wire vga_sprite_1_s1_agent_rp_ready; // router_026:sink_ready -> vga_sprite_1_s1_agent:rp_ready
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wire vga_sprite_1_s1_agent_rp_startofpacket; // vga_sprite_1_s1_agent:rp_startofpacket -> router_026:sink_startofpacket
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wire vga_sprite_1_s1_agent_rp_endofpacket; // vga_sprite_1_s1_agent:rp_endofpacket -> router_026:sink_endofpacket
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wire router_026_src_valid; // router_026:src_valid -> rsp_demux_022:sink_valid
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wire [113:0] router_026_src_data; // router_026:src_data -> rsp_demux_022:sink_data
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wire router_026_src_ready; // rsp_demux_022:sink_ready -> router_026:src_ready
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wire [33:0] router_026_src_channel; // router_026:src_channel -> rsp_demux_022:sink_channel
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wire router_026_src_startofpacket; // router_026:src_startofpacket -> rsp_demux_022:sink_startofpacket
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wire router_026_src_endofpacket; // router_026:src_endofpacket -> rsp_demux_022:sink_endofpacket
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wire vga_sprite_2_s1_agent_rp_valid; // vga_sprite_2_s1_agent:rp_valid -> router_027:sink_valid
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wire [113:0] vga_sprite_2_s1_agent_rp_data; // vga_sprite_2_s1_agent:rp_data -> router_027:sink_data
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wire vga_sprite_2_s1_agent_rp_ready; // router_027:sink_ready -> vga_sprite_2_s1_agent:rp_ready
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wire vga_sprite_2_s1_agent_rp_startofpacket; // vga_sprite_2_s1_agent:rp_startofpacket -> router_027:sink_startofpacket
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wire vga_sprite_2_s1_agent_rp_endofpacket; // vga_sprite_2_s1_agent:rp_endofpacket -> router_027:sink_endofpacket
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wire router_027_src_valid; // router_027:src_valid -> rsp_demux_023:sink_valid
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wire [113:0] router_027_src_data; // router_027:src_data -> rsp_demux_023:sink_data
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wire router_027_src_ready; // rsp_demux_023:sink_ready -> router_027:src_ready
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wire [33:0] router_027_src_channel; // router_027:src_channel -> rsp_demux_023:sink_channel
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wire router_027_src_startofpacket; // router_027:src_startofpacket -> rsp_demux_023:sink_startofpacket
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wire router_027_src_endofpacket; // router_027:src_endofpacket -> rsp_demux_023:sink_endofpacket
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wire vga_sprite_3_s1_agent_rp_valid; // vga_sprite_3_s1_agent:rp_valid -> router_028:sink_valid
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wire [113:0] vga_sprite_3_s1_agent_rp_data; // vga_sprite_3_s1_agent:rp_data -> router_028:sink_data
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wire vga_sprite_3_s1_agent_rp_ready; // router_028:sink_ready -> vga_sprite_3_s1_agent:rp_ready
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wire vga_sprite_3_s1_agent_rp_startofpacket; // vga_sprite_3_s1_agent:rp_startofpacket -> router_028:sink_startofpacket
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wire vga_sprite_3_s1_agent_rp_endofpacket; // vga_sprite_3_s1_agent:rp_endofpacket -> router_028:sink_endofpacket
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wire router_028_src_valid; // router_028:src_valid -> rsp_demux_024:sink_valid
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wire [113:0] router_028_src_data; // router_028:src_data -> rsp_demux_024:sink_data
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wire router_028_src_ready; // rsp_demux_024:sink_ready -> router_028:src_ready
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wire [33:0] router_028_src_channel; // router_028:src_channel -> rsp_demux_024:sink_channel
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wire router_028_src_startofpacket; // router_028:src_startofpacket -> rsp_demux_024:sink_startofpacket
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wire router_028_src_endofpacket; // router_028:src_endofpacket -> rsp_demux_024:sink_endofpacket
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wire io_vga_sync_s1_agent_rp_valid; // io_vga_sync_s1_agent:rp_valid -> router_029:sink_valid
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wire [113:0] io_vga_sync_s1_agent_rp_data; // io_vga_sync_s1_agent:rp_data -> router_029:sink_data
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wire io_vga_sync_s1_agent_rp_ready; // router_029:sink_ready -> io_vga_sync_s1_agent:rp_ready
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wire io_vga_sync_s1_agent_rp_startofpacket; // io_vga_sync_s1_agent:rp_startofpacket -> router_029:sink_startofpacket
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wire io_vga_sync_s1_agent_rp_endofpacket; // io_vga_sync_s1_agent:rp_endofpacket -> router_029:sink_endofpacket
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wire router_029_src_valid; // router_029:src_valid -> rsp_demux_025:sink_valid
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wire [113:0] router_029_src_data; // router_029:src_data -> rsp_demux_025:sink_data
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wire router_029_src_ready; // rsp_demux_025:sink_ready -> router_029:src_ready
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wire [33:0] router_029_src_channel; // router_029:src_channel -> rsp_demux_025:sink_channel
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wire router_029_src_startofpacket; // router_029:src_startofpacket -> rsp_demux_025:sink_startofpacket
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wire router_029_src_endofpacket; // router_029:src_endofpacket -> rsp_demux_025:sink_endofpacket
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wire vga_sprite_4_s1_agent_rp_valid; // vga_sprite_4_s1_agent:rp_valid -> router_030:sink_valid
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wire [113:0] vga_sprite_4_s1_agent_rp_data; // vga_sprite_4_s1_agent:rp_data -> router_030:sink_data
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wire vga_sprite_4_s1_agent_rp_ready; // router_030:sink_ready -> vga_sprite_4_s1_agent:rp_ready
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wire vga_sprite_4_s1_agent_rp_startofpacket; // vga_sprite_4_s1_agent:rp_startofpacket -> router_030:sink_startofpacket
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wire vga_sprite_4_s1_agent_rp_endofpacket; // vga_sprite_4_s1_agent:rp_endofpacket -> router_030:sink_endofpacket
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wire router_030_src_valid; // router_030:src_valid -> rsp_demux_026:sink_valid
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wire [113:0] router_030_src_data; // router_030:src_data -> rsp_demux_026:sink_data
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wire router_030_src_ready; // rsp_demux_026:sink_ready -> router_030:src_ready
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wire [33:0] router_030_src_channel; // router_030:src_channel -> rsp_demux_026:sink_channel
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wire router_030_src_startofpacket; // router_030:src_startofpacket -> rsp_demux_026:sink_startofpacket
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wire router_030_src_endofpacket; // router_030:src_endofpacket -> rsp_demux_026:sink_endofpacket
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wire vga_sprite_5_s1_agent_rp_valid; // vga_sprite_5_s1_agent:rp_valid -> router_031:sink_valid
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wire [113:0] vga_sprite_5_s1_agent_rp_data; // vga_sprite_5_s1_agent:rp_data -> router_031:sink_data
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wire vga_sprite_5_s1_agent_rp_ready; // router_031:sink_ready -> vga_sprite_5_s1_agent:rp_ready
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wire vga_sprite_5_s1_agent_rp_startofpacket; // vga_sprite_5_s1_agent:rp_startofpacket -> router_031:sink_startofpacket
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wire vga_sprite_5_s1_agent_rp_endofpacket; // vga_sprite_5_s1_agent:rp_endofpacket -> router_031:sink_endofpacket
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wire router_031_src_valid; // router_031:src_valid -> rsp_demux_027:sink_valid
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wire [113:0] router_031_src_data; // router_031:src_data -> rsp_demux_027:sink_data
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wire router_031_src_ready; // rsp_demux_027:sink_ready -> router_031:src_ready
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wire [33:0] router_031_src_channel; // router_031:src_channel -> rsp_demux_027:sink_channel
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wire router_031_src_startofpacket; // router_031:src_startofpacket -> rsp_demux_027:sink_startofpacket
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wire router_031_src_endofpacket; // router_031:src_endofpacket -> rsp_demux_027:sink_endofpacket
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wire vga_sprite_6_s1_agent_rp_valid; // vga_sprite_6_s1_agent:rp_valid -> router_032:sink_valid
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wire [113:0] vga_sprite_6_s1_agent_rp_data; // vga_sprite_6_s1_agent:rp_data -> router_032:sink_data
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wire vga_sprite_6_s1_agent_rp_ready; // router_032:sink_ready -> vga_sprite_6_s1_agent:rp_ready
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wire vga_sprite_6_s1_agent_rp_startofpacket; // vga_sprite_6_s1_agent:rp_startofpacket -> router_032:sink_startofpacket
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wire vga_sprite_6_s1_agent_rp_endofpacket; // vga_sprite_6_s1_agent:rp_endofpacket -> router_032:sink_endofpacket
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wire router_032_src_valid; // router_032:src_valid -> rsp_demux_028:sink_valid
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wire [113:0] router_032_src_data; // router_032:src_data -> rsp_demux_028:sink_data
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wire router_032_src_ready; // rsp_demux_028:sink_ready -> router_032:src_ready
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wire [33:0] router_032_src_channel; // router_032:src_channel -> rsp_demux_028:sink_channel
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wire router_032_src_startofpacket; // router_032:src_startofpacket -> rsp_demux_028:sink_startofpacket
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wire router_032_src_endofpacket; // router_032:src_endofpacket -> rsp_demux_028:sink_endofpacket
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wire vga_sprite_7_s1_agent_rp_valid; // vga_sprite_7_s1_agent:rp_valid -> router_033:sink_valid
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wire [113:0] vga_sprite_7_s1_agent_rp_data; // vga_sprite_7_s1_agent:rp_data -> router_033:sink_data
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wire vga_sprite_7_s1_agent_rp_ready; // router_033:sink_ready -> vga_sprite_7_s1_agent:rp_ready
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wire vga_sprite_7_s1_agent_rp_startofpacket; // vga_sprite_7_s1_agent:rp_startofpacket -> router_033:sink_startofpacket
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wire vga_sprite_7_s1_agent_rp_endofpacket; // vga_sprite_7_s1_agent:rp_endofpacket -> router_033:sink_endofpacket
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wire router_033_src_valid; // router_033:src_valid -> rsp_demux_029:sink_valid
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wire [113:0] router_033_src_data; // router_033:src_data -> rsp_demux_029:sink_data
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wire router_033_src_ready; // rsp_demux_029:sink_ready -> router_033:src_ready
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wire [33:0] router_033_src_channel; // router_033:src_channel -> rsp_demux_029:sink_channel
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wire router_033_src_startofpacket; // router_033:src_startofpacket -> rsp_demux_029:sink_startofpacket
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wire router_033_src_endofpacket; // router_033:src_endofpacket -> rsp_demux_029:sink_endofpacket
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wire vga_background_offset_s1_agent_rp_valid; // vga_background_offset_s1_agent:rp_valid -> router_034:sink_valid
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wire [113:0] vga_background_offset_s1_agent_rp_data; // vga_background_offset_s1_agent:rp_data -> router_034:sink_data
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wire vga_background_offset_s1_agent_rp_ready; // router_034:sink_ready -> vga_background_offset_s1_agent:rp_ready
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wire vga_background_offset_s1_agent_rp_startofpacket; // vga_background_offset_s1_agent:rp_startofpacket -> router_034:sink_startofpacket
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wire vga_background_offset_s1_agent_rp_endofpacket; // vga_background_offset_s1_agent:rp_endofpacket -> router_034:sink_endofpacket
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wire router_034_src_valid; // router_034:src_valid -> rsp_demux_030:sink_valid
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wire [113:0] router_034_src_data; // router_034:src_data -> rsp_demux_030:sink_data
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wire router_034_src_ready; // rsp_demux_030:sink_ready -> router_034:src_ready
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wire [33:0] router_034_src_channel; // router_034:src_channel -> rsp_demux_030:sink_channel
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wire router_034_src_startofpacket; // router_034:src_startofpacket -> rsp_demux_030:sink_startofpacket
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wire router_034_src_endofpacket; // router_034:src_endofpacket -> rsp_demux_030:sink_endofpacket
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wire audio_pio_s1_agent_rp_valid; // audio_pio_s1_agent:rp_valid -> router_035:sink_valid
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wire [113:0] audio_pio_s1_agent_rp_data; // audio_pio_s1_agent:rp_data -> router_035:sink_data
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wire audio_pio_s1_agent_rp_ready; // router_035:sink_ready -> audio_pio_s1_agent:rp_ready
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wire audio_pio_s1_agent_rp_startofpacket; // audio_pio_s1_agent:rp_startofpacket -> router_035:sink_startofpacket
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wire audio_pio_s1_agent_rp_endofpacket; // audio_pio_s1_agent:rp_endofpacket -> router_035:sink_endofpacket
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wire router_035_src_valid; // router_035:src_valid -> rsp_demux_031:sink_valid
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wire [113:0] router_035_src_data; // router_035:src_data -> rsp_demux_031:sink_data
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wire router_035_src_ready; // rsp_demux_031:sink_ready -> router_035:src_ready
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wire [33:0] router_035_src_channel; // router_035:src_channel -> rsp_demux_031:sink_channel
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wire router_035_src_startofpacket; // router_035:src_startofpacket -> rsp_demux_031:sink_startofpacket
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wire router_035_src_endofpacket; // router_035:src_endofpacket -> rsp_demux_031:sink_endofpacket
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wire audio_timer_s1_agent_rp_valid; // audio_timer_s1_agent:rp_valid -> router_036:sink_valid
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wire [113:0] audio_timer_s1_agent_rp_data; // audio_timer_s1_agent:rp_data -> router_036:sink_data
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wire audio_timer_s1_agent_rp_ready; // router_036:sink_ready -> audio_timer_s1_agent:rp_ready
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wire audio_timer_s1_agent_rp_startofpacket; // audio_timer_s1_agent:rp_startofpacket -> router_036:sink_startofpacket
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wire audio_timer_s1_agent_rp_endofpacket; // audio_timer_s1_agent:rp_endofpacket -> router_036:sink_endofpacket
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wire router_036_src_valid; // router_036:src_valid -> rsp_demux_032:sink_valid
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wire [113:0] router_036_src_data; // router_036:src_data -> rsp_demux_032:sink_data
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wire router_036_src_ready; // rsp_demux_032:sink_ready -> router_036:src_ready
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wire [33:0] router_036_src_channel; // router_036:src_channel -> rsp_demux_032:sink_channel
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wire router_036_src_startofpacket; // router_036:src_startofpacket -> rsp_demux_032:sink_startofpacket
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wire router_036_src_endofpacket; // router_036:src_endofpacket -> rsp_demux_032:sink_endofpacket
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wire usb_keycode_s2_agent_rp_valid; // usb_keycode_s2_agent:rp_valid -> router_037:sink_valid
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wire [113:0] usb_keycode_s2_agent_rp_data; // usb_keycode_s2_agent:rp_data -> router_037:sink_data
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wire usb_keycode_s2_agent_rp_ready; // router_037:sink_ready -> usb_keycode_s2_agent:rp_ready
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wire usb_keycode_s2_agent_rp_startofpacket; // usb_keycode_s2_agent:rp_startofpacket -> router_037:sink_startofpacket
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wire usb_keycode_s2_agent_rp_endofpacket; // usb_keycode_s2_agent:rp_endofpacket -> router_037:sink_endofpacket
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wire router_037_src_valid; // router_037:src_valid -> rsp_demux_033:sink_valid
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wire [113:0] router_037_src_data; // router_037:src_data -> rsp_demux_033:sink_data
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wire router_037_src_ready; // rsp_demux_033:sink_ready -> router_037:src_ready
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wire [33:0] router_037_src_channel; // router_037:src_channel -> rsp_demux_033:sink_channel
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wire router_037_src_startofpacket; // router_037:src_startofpacket -> rsp_demux_033:sink_startofpacket
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wire router_037_src_endofpacket; // router_037:src_endofpacket -> rsp_demux_033:sink_endofpacket
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wire router_001_src_valid; // router_001:src_valid -> nios2_dma_m_read_limiter:cmd_sink_valid
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wire [113:0] router_001_src_data; // router_001:src_data -> nios2_dma_m_read_limiter:cmd_sink_data
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wire router_001_src_ready; // nios2_dma_m_read_limiter:cmd_sink_ready -> router_001:src_ready
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wire [33:0] router_001_src_channel; // router_001:src_channel -> nios2_dma_m_read_limiter:cmd_sink_channel
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wire router_001_src_startofpacket; // router_001:src_startofpacket -> nios2_dma_m_read_limiter:cmd_sink_startofpacket
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wire router_001_src_endofpacket; // router_001:src_endofpacket -> nios2_dma_m_read_limiter:cmd_sink_endofpacket
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wire [113:0] nios2_dma_m_read_limiter_cmd_src_data; // nios2_dma_m_read_limiter:cmd_src_data -> cmd_demux_001:sink_data
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wire nios2_dma_m_read_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> nios2_dma_m_read_limiter:cmd_src_ready
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wire [33:0] nios2_dma_m_read_limiter_cmd_src_channel; // nios2_dma_m_read_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
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wire nios2_dma_m_read_limiter_cmd_src_startofpacket; // nios2_dma_m_read_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
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wire nios2_dma_m_read_limiter_cmd_src_endofpacket; // nios2_dma_m_read_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
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wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_dma_m_read_limiter:rsp_sink_valid
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wire [113:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_dma_m_read_limiter:rsp_sink_data
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wire rsp_mux_001_src_ready; // nios2_dma_m_read_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
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wire [33:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_dma_m_read_limiter:rsp_sink_channel
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wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_dma_m_read_limiter:rsp_sink_startofpacket
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wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_dma_m_read_limiter:rsp_sink_endofpacket
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wire nios2_dma_m_read_limiter_rsp_src_valid; // nios2_dma_m_read_limiter:rsp_src_valid -> nios2_dma_m_read_agent:rp_valid
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wire [113:0] nios2_dma_m_read_limiter_rsp_src_data; // nios2_dma_m_read_limiter:rsp_src_data -> nios2_dma_m_read_agent:rp_data
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wire nios2_dma_m_read_limiter_rsp_src_ready; // nios2_dma_m_read_agent:rp_ready -> nios2_dma_m_read_limiter:rsp_src_ready
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wire [33:0] nios2_dma_m_read_limiter_rsp_src_channel; // nios2_dma_m_read_limiter:rsp_src_channel -> nios2_dma_m_read_agent:rp_channel
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wire nios2_dma_m_read_limiter_rsp_src_startofpacket; // nios2_dma_m_read_limiter:rsp_src_startofpacket -> nios2_dma_m_read_agent:rp_startofpacket
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wire nios2_dma_m_read_limiter_rsp_src_endofpacket; // nios2_dma_m_read_limiter:rsp_src_endofpacket -> nios2_dma_m_read_agent:rp_endofpacket
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wire sram_multiplexer_avl_burst_adapter_source0_valid; // sram_multiplexer_avl_burst_adapter:source0_valid -> sram_multiplexer_avl_agent:cp_valid
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wire [95:0] sram_multiplexer_avl_burst_adapter_source0_data; // sram_multiplexer_avl_burst_adapter:source0_data -> sram_multiplexer_avl_agent:cp_data
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wire sram_multiplexer_avl_burst_adapter_source0_ready; // sram_multiplexer_avl_agent:cp_ready -> sram_multiplexer_avl_burst_adapter:source0_ready
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wire [33:0] sram_multiplexer_avl_burst_adapter_source0_channel; // sram_multiplexer_avl_burst_adapter:source0_channel -> sram_multiplexer_avl_agent:cp_channel
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wire sram_multiplexer_avl_burst_adapter_source0_startofpacket; // sram_multiplexer_avl_burst_adapter:source0_startofpacket -> sram_multiplexer_avl_agent:cp_startofpacket
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wire sram_multiplexer_avl_burst_adapter_source0_endofpacket; // sram_multiplexer_avl_burst_adapter:source0_endofpacket -> sram_multiplexer_avl_agent:cp_endofpacket
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wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
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wire [113:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
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wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
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wire [33:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
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wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
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wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
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wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
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wire [113:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
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wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
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wire [33:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
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wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
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wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
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wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
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wire [113:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
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wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
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wire [33:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
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wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
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wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
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wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
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wire [113:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
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wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
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wire [33:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
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wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
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wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
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wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
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wire [113:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
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wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
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wire [33:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
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wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
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wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
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wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
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wire [113:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
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wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
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wire [33:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
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wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
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wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
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wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
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wire [113:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
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wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
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wire [33:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
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wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
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wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
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wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
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wire [113:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
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wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
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wire [33:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
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wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
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wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
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wire cmd_demux_src8_valid; // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
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wire [113:0] cmd_demux_src8_data; // cmd_demux:src8_data -> cmd_mux_008:sink0_data
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wire cmd_demux_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
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wire [33:0] cmd_demux_src8_channel; // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
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wire cmd_demux_src8_startofpacket; // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
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wire cmd_demux_src8_endofpacket; // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
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wire cmd_demux_src9_valid; // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
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wire [113:0] cmd_demux_src9_data; // cmd_demux:src9_data -> cmd_mux_009:sink0_data
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wire cmd_demux_src9_ready; // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
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wire [33:0] cmd_demux_src9_channel; // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
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wire cmd_demux_src9_startofpacket; // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
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wire cmd_demux_src9_endofpacket; // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
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wire cmd_demux_src10_valid; // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
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wire [113:0] cmd_demux_src10_data; // cmd_demux:src10_data -> cmd_mux_010:sink0_data
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wire cmd_demux_src10_ready; // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
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wire [33:0] cmd_demux_src10_channel; // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
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wire cmd_demux_src10_startofpacket; // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
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wire cmd_demux_src10_endofpacket; // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
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wire cmd_demux_src11_valid; // cmd_demux:src11_valid -> cmd_mux_011:sink0_valid
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wire [113:0] cmd_demux_src11_data; // cmd_demux:src11_data -> cmd_mux_011:sink0_data
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wire cmd_demux_src11_ready; // cmd_mux_011:sink0_ready -> cmd_demux:src11_ready
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wire [33:0] cmd_demux_src11_channel; // cmd_demux:src11_channel -> cmd_mux_011:sink0_channel
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wire cmd_demux_src11_startofpacket; // cmd_demux:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
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wire cmd_demux_src11_endofpacket; // cmd_demux:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
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wire cmd_demux_src12_valid; // cmd_demux:src12_valid -> cmd_mux_012:sink0_valid
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wire [113:0] cmd_demux_src12_data; // cmd_demux:src12_data -> cmd_mux_012:sink0_data
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wire cmd_demux_src12_ready; // cmd_mux_012:sink0_ready -> cmd_demux:src12_ready
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wire [33:0] cmd_demux_src12_channel; // cmd_demux:src12_channel -> cmd_mux_012:sink0_channel
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wire cmd_demux_src12_startofpacket; // cmd_demux:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
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wire cmd_demux_src12_endofpacket; // cmd_demux:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
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wire cmd_demux_src13_valid; // cmd_demux:src13_valid -> cmd_mux_013:sink0_valid
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wire [113:0] cmd_demux_src13_data; // cmd_demux:src13_data -> cmd_mux_013:sink0_data
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wire cmd_demux_src13_ready; // cmd_mux_013:sink0_ready -> cmd_demux:src13_ready
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wire [33:0] cmd_demux_src13_channel; // cmd_demux:src13_channel -> cmd_mux_013:sink0_channel
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wire cmd_demux_src13_startofpacket; // cmd_demux:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
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wire cmd_demux_src13_endofpacket; // cmd_demux:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
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wire cmd_demux_src14_valid; // cmd_demux:src14_valid -> cmd_mux_014:sink0_valid
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wire [113:0] cmd_demux_src14_data; // cmd_demux:src14_data -> cmd_mux_014:sink0_data
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wire cmd_demux_src14_ready; // cmd_mux_014:sink0_ready -> cmd_demux:src14_ready
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wire [33:0] cmd_demux_src14_channel; // cmd_demux:src14_channel -> cmd_mux_014:sink0_channel
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wire cmd_demux_src14_startofpacket; // cmd_demux:src14_startofpacket -> cmd_mux_014:sink0_startofpacket
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wire cmd_demux_src14_endofpacket; // cmd_demux:src14_endofpacket -> cmd_mux_014:sink0_endofpacket
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wire cmd_demux_src15_valid; // cmd_demux:src15_valid -> cmd_mux_015:sink0_valid
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wire [113:0] cmd_demux_src15_data; // cmd_demux:src15_data -> cmd_mux_015:sink0_data
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wire cmd_demux_src15_ready; // cmd_mux_015:sink0_ready -> cmd_demux:src15_ready
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wire [33:0] cmd_demux_src15_channel; // cmd_demux:src15_channel -> cmd_mux_015:sink0_channel
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wire cmd_demux_src15_startofpacket; // cmd_demux:src15_startofpacket -> cmd_mux_015:sink0_startofpacket
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wire cmd_demux_src15_endofpacket; // cmd_demux:src15_endofpacket -> cmd_mux_015:sink0_endofpacket
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wire cmd_demux_src16_valid; // cmd_demux:src16_valid -> cmd_mux_016:sink0_valid
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wire [113:0] cmd_demux_src16_data; // cmd_demux:src16_data -> cmd_mux_016:sink0_data
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wire cmd_demux_src16_ready; // cmd_mux_016:sink0_ready -> cmd_demux:src16_ready
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wire [33:0] cmd_demux_src16_channel; // cmd_demux:src16_channel -> cmd_mux_016:sink0_channel
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wire cmd_demux_src16_startofpacket; // cmd_demux:src16_startofpacket -> cmd_mux_016:sink0_startofpacket
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wire cmd_demux_src16_endofpacket; // cmd_demux:src16_endofpacket -> cmd_mux_016:sink0_endofpacket
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wire cmd_demux_src17_valid; // cmd_demux:src17_valid -> cmd_mux_017:sink0_valid
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wire [113:0] cmd_demux_src17_data; // cmd_demux:src17_data -> cmd_mux_017:sink0_data
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wire cmd_demux_src17_ready; // cmd_mux_017:sink0_ready -> cmd_demux:src17_ready
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wire [33:0] cmd_demux_src17_channel; // cmd_demux:src17_channel -> cmd_mux_017:sink0_channel
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wire cmd_demux_src17_startofpacket; // cmd_demux:src17_startofpacket -> cmd_mux_017:sink0_startofpacket
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wire cmd_demux_src17_endofpacket; // cmd_demux:src17_endofpacket -> cmd_mux_017:sink0_endofpacket
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wire cmd_demux_src18_valid; // cmd_demux:src18_valid -> cmd_mux_018:sink0_valid
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wire [113:0] cmd_demux_src18_data; // cmd_demux:src18_data -> cmd_mux_018:sink0_data
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wire cmd_demux_src18_ready; // cmd_mux_018:sink0_ready -> cmd_demux:src18_ready
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wire [33:0] cmd_demux_src18_channel; // cmd_demux:src18_channel -> cmd_mux_018:sink0_channel
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wire cmd_demux_src18_startofpacket; // cmd_demux:src18_startofpacket -> cmd_mux_018:sink0_startofpacket
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wire cmd_demux_src18_endofpacket; // cmd_demux:src18_endofpacket -> cmd_mux_018:sink0_endofpacket
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wire cmd_demux_src19_valid; // cmd_demux:src19_valid -> cmd_mux_019:sink0_valid
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wire [113:0] cmd_demux_src19_data; // cmd_demux:src19_data -> cmd_mux_019:sink0_data
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wire cmd_demux_src19_ready; // cmd_mux_019:sink0_ready -> cmd_demux:src19_ready
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wire [33:0] cmd_demux_src19_channel; // cmd_demux:src19_channel -> cmd_mux_019:sink0_channel
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wire cmd_demux_src19_startofpacket; // cmd_demux:src19_startofpacket -> cmd_mux_019:sink0_startofpacket
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wire cmd_demux_src19_endofpacket; // cmd_demux:src19_endofpacket -> cmd_mux_019:sink0_endofpacket
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wire cmd_demux_src20_valid; // cmd_demux:src20_valid -> cmd_mux_020:sink0_valid
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wire [113:0] cmd_demux_src20_data; // cmd_demux:src20_data -> cmd_mux_020:sink0_data
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wire cmd_demux_src20_ready; // cmd_mux_020:sink0_ready -> cmd_demux:src20_ready
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wire [33:0] cmd_demux_src20_channel; // cmd_demux:src20_channel -> cmd_mux_020:sink0_channel
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wire cmd_demux_src20_startofpacket; // cmd_demux:src20_startofpacket -> cmd_mux_020:sink0_startofpacket
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wire cmd_demux_src20_endofpacket; // cmd_demux:src20_endofpacket -> cmd_mux_020:sink0_endofpacket
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wire cmd_demux_src21_valid; // cmd_demux:src21_valid -> cmd_mux_021:sink0_valid
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wire [113:0] cmd_demux_src21_data; // cmd_demux:src21_data -> cmd_mux_021:sink0_data
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wire cmd_demux_src21_ready; // cmd_mux_021:sink0_ready -> cmd_demux:src21_ready
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wire [33:0] cmd_demux_src21_channel; // cmd_demux:src21_channel -> cmd_mux_021:sink0_channel
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wire cmd_demux_src21_startofpacket; // cmd_demux:src21_startofpacket -> cmd_mux_021:sink0_startofpacket
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wire cmd_demux_src21_endofpacket; // cmd_demux:src21_endofpacket -> cmd_mux_021:sink0_endofpacket
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wire cmd_demux_src22_valid; // cmd_demux:src22_valid -> cmd_mux_022:sink0_valid
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wire [113:0] cmd_demux_src22_data; // cmd_demux:src22_data -> cmd_mux_022:sink0_data
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wire cmd_demux_src22_ready; // cmd_mux_022:sink0_ready -> cmd_demux:src22_ready
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wire [33:0] cmd_demux_src22_channel; // cmd_demux:src22_channel -> cmd_mux_022:sink0_channel
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wire cmd_demux_src22_startofpacket; // cmd_demux:src22_startofpacket -> cmd_mux_022:sink0_startofpacket
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wire cmd_demux_src22_endofpacket; // cmd_demux:src22_endofpacket -> cmd_mux_022:sink0_endofpacket
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wire cmd_demux_src23_valid; // cmd_demux:src23_valid -> cmd_mux_023:sink0_valid
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wire [113:0] cmd_demux_src23_data; // cmd_demux:src23_data -> cmd_mux_023:sink0_data
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wire cmd_demux_src23_ready; // cmd_mux_023:sink0_ready -> cmd_demux:src23_ready
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wire [33:0] cmd_demux_src23_channel; // cmd_demux:src23_channel -> cmd_mux_023:sink0_channel
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wire cmd_demux_src23_startofpacket; // cmd_demux:src23_startofpacket -> cmd_mux_023:sink0_startofpacket
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wire cmd_demux_src23_endofpacket; // cmd_demux:src23_endofpacket -> cmd_mux_023:sink0_endofpacket
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wire cmd_demux_src24_valid; // cmd_demux:src24_valid -> cmd_mux_024:sink0_valid
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wire [113:0] cmd_demux_src24_data; // cmd_demux:src24_data -> cmd_mux_024:sink0_data
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wire cmd_demux_src24_ready; // cmd_mux_024:sink0_ready -> cmd_demux:src24_ready
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wire [33:0] cmd_demux_src24_channel; // cmd_demux:src24_channel -> cmd_mux_024:sink0_channel
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wire cmd_demux_src24_startofpacket; // cmd_demux:src24_startofpacket -> cmd_mux_024:sink0_startofpacket
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wire cmd_demux_src24_endofpacket; // cmd_demux:src24_endofpacket -> cmd_mux_024:sink0_endofpacket
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wire cmd_demux_src25_valid; // cmd_demux:src25_valid -> cmd_mux_025:sink0_valid
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wire [113:0] cmd_demux_src25_data; // cmd_demux:src25_data -> cmd_mux_025:sink0_data
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wire cmd_demux_src25_ready; // cmd_mux_025:sink0_ready -> cmd_demux:src25_ready
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wire [33:0] cmd_demux_src25_channel; // cmd_demux:src25_channel -> cmd_mux_025:sink0_channel
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wire cmd_demux_src25_startofpacket; // cmd_demux:src25_startofpacket -> cmd_mux_025:sink0_startofpacket
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wire cmd_demux_src25_endofpacket; // cmd_demux:src25_endofpacket -> cmd_mux_025:sink0_endofpacket
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wire cmd_demux_src26_valid; // cmd_demux:src26_valid -> cmd_mux_026:sink0_valid
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wire [113:0] cmd_demux_src26_data; // cmd_demux:src26_data -> cmd_mux_026:sink0_data
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wire cmd_demux_src26_ready; // cmd_mux_026:sink0_ready -> cmd_demux:src26_ready
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wire [33:0] cmd_demux_src26_channel; // cmd_demux:src26_channel -> cmd_mux_026:sink0_channel
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wire cmd_demux_src26_startofpacket; // cmd_demux:src26_startofpacket -> cmd_mux_026:sink0_startofpacket
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wire cmd_demux_src26_endofpacket; // cmd_demux:src26_endofpacket -> cmd_mux_026:sink0_endofpacket
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wire cmd_demux_src27_valid; // cmd_demux:src27_valid -> cmd_mux_027:sink0_valid
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wire [113:0] cmd_demux_src27_data; // cmd_demux:src27_data -> cmd_mux_027:sink0_data
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wire cmd_demux_src27_ready; // cmd_mux_027:sink0_ready -> cmd_demux:src27_ready
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wire [33:0] cmd_demux_src27_channel; // cmd_demux:src27_channel -> cmd_mux_027:sink0_channel
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wire cmd_demux_src27_startofpacket; // cmd_demux:src27_startofpacket -> cmd_mux_027:sink0_startofpacket
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wire cmd_demux_src27_endofpacket; // cmd_demux:src27_endofpacket -> cmd_mux_027:sink0_endofpacket
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wire cmd_demux_src28_valid; // cmd_demux:src28_valid -> cmd_mux_028:sink0_valid
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wire [113:0] cmd_demux_src28_data; // cmd_demux:src28_data -> cmd_mux_028:sink0_data
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wire cmd_demux_src28_ready; // cmd_mux_028:sink0_ready -> cmd_demux:src28_ready
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wire [33:0] cmd_demux_src28_channel; // cmd_demux:src28_channel -> cmd_mux_028:sink0_channel
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wire cmd_demux_src28_startofpacket; // cmd_demux:src28_startofpacket -> cmd_mux_028:sink0_startofpacket
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wire cmd_demux_src28_endofpacket; // cmd_demux:src28_endofpacket -> cmd_mux_028:sink0_endofpacket
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wire cmd_demux_src29_valid; // cmd_demux:src29_valid -> cmd_mux_029:sink0_valid
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wire [113:0] cmd_demux_src29_data; // cmd_demux:src29_data -> cmd_mux_029:sink0_data
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wire cmd_demux_src29_ready; // cmd_mux_029:sink0_ready -> cmd_demux:src29_ready
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wire [33:0] cmd_demux_src29_channel; // cmd_demux:src29_channel -> cmd_mux_029:sink0_channel
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wire cmd_demux_src29_startofpacket; // cmd_demux:src29_startofpacket -> cmd_mux_029:sink0_startofpacket
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wire cmd_demux_src29_endofpacket; // cmd_demux:src29_endofpacket -> cmd_mux_029:sink0_endofpacket
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wire cmd_demux_src30_valid; // cmd_demux:src30_valid -> cmd_mux_030:sink0_valid
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wire [113:0] cmd_demux_src30_data; // cmd_demux:src30_data -> cmd_mux_030:sink0_data
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wire cmd_demux_src30_ready; // cmd_mux_030:sink0_ready -> cmd_demux:src30_ready
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wire [33:0] cmd_demux_src30_channel; // cmd_demux:src30_channel -> cmd_mux_030:sink0_channel
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wire cmd_demux_src30_startofpacket; // cmd_demux:src30_startofpacket -> cmd_mux_030:sink0_startofpacket
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wire cmd_demux_src30_endofpacket; // cmd_demux:src30_endofpacket -> cmd_mux_030:sink0_endofpacket
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wire cmd_demux_src31_valid; // cmd_demux:src31_valid -> cmd_mux_031:sink0_valid
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wire [113:0] cmd_demux_src31_data; // cmd_demux:src31_data -> cmd_mux_031:sink0_data
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wire cmd_demux_src31_ready; // cmd_mux_031:sink0_ready -> cmd_demux:src31_ready
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wire [33:0] cmd_demux_src31_channel; // cmd_demux:src31_channel -> cmd_mux_031:sink0_channel
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wire cmd_demux_src31_startofpacket; // cmd_demux:src31_startofpacket -> cmd_mux_031:sink0_startofpacket
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wire cmd_demux_src31_endofpacket; // cmd_demux:src31_endofpacket -> cmd_mux_031:sink0_endofpacket
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wire cmd_demux_src32_valid; // cmd_demux:src32_valid -> cmd_mux_032:sink0_valid
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wire [113:0] cmd_demux_src32_data; // cmd_demux:src32_data -> cmd_mux_032:sink0_data
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wire cmd_demux_src32_ready; // cmd_mux_032:sink0_ready -> cmd_demux:src32_ready
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wire [33:0] cmd_demux_src32_channel; // cmd_demux:src32_channel -> cmd_mux_032:sink0_channel
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wire cmd_demux_src32_startofpacket; // cmd_demux:src32_startofpacket -> cmd_mux_032:sink0_startofpacket
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wire cmd_demux_src32_endofpacket; // cmd_demux:src32_endofpacket -> cmd_mux_032:sink0_endofpacket
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wire cmd_demux_src33_valid; // cmd_demux:src33_valid -> cmd_mux_033:sink0_valid
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wire [113:0] cmd_demux_src33_data; // cmd_demux:src33_data -> cmd_mux_033:sink0_data
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wire cmd_demux_src33_ready; // cmd_mux_033:sink0_ready -> cmd_demux:src33_ready
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wire [33:0] cmd_demux_src33_channel; // cmd_demux:src33_channel -> cmd_mux_033:sink0_channel
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wire cmd_demux_src33_startofpacket; // cmd_demux:src33_startofpacket -> cmd_mux_033:sink0_startofpacket
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wire cmd_demux_src33_endofpacket; // cmd_demux:src33_endofpacket -> cmd_mux_033:sink0_endofpacket
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wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
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wire [113:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
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wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
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wire [33:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
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wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
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wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
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wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
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wire [113:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
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wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
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wire [33:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
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wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
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wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
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wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
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wire [113:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
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wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
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wire [33:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
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wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
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wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
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wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink1_valid
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wire [113:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink1_data
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wire cmd_demux_001_src3_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src3_ready
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wire [33:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink1_channel
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wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink1_startofpacket
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wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink1_endofpacket
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wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink1_valid
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wire [113:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink1_data
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wire cmd_demux_001_src4_ready; // cmd_mux_004:sink1_ready -> cmd_demux_001:src4_ready
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wire [33:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink1_channel
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wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink1_startofpacket
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wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink1_endofpacket
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wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> cmd_mux_005:sink1_valid
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wire [113:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> cmd_mux_005:sink1_data
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wire cmd_demux_001_src5_ready; // cmd_mux_005:sink1_ready -> cmd_demux_001:src5_ready
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wire [33:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> cmd_mux_005:sink1_channel
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wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink1_startofpacket
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wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink1_endofpacket
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wire cmd_demux_001_src6_valid; // cmd_demux_001:src6_valid -> cmd_mux_006:sink1_valid
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wire [113:0] cmd_demux_001_src6_data; // cmd_demux_001:src6_data -> cmd_mux_006:sink1_data
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wire cmd_demux_001_src6_ready; // cmd_mux_006:sink1_ready -> cmd_demux_001:src6_ready
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wire [33:0] cmd_demux_001_src6_channel; // cmd_demux_001:src6_channel -> cmd_mux_006:sink1_channel
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wire cmd_demux_001_src6_startofpacket; // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink1_startofpacket
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wire cmd_demux_001_src6_endofpacket; // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink1_endofpacket
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wire cmd_demux_001_src7_valid; // cmd_demux_001:src7_valid -> cmd_mux_007:sink1_valid
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wire [113:0] cmd_demux_001_src7_data; // cmd_demux_001:src7_data -> cmd_mux_007:sink1_data
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wire cmd_demux_001_src7_ready; // cmd_mux_007:sink1_ready -> cmd_demux_001:src7_ready
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wire [33:0] cmd_demux_001_src7_channel; // cmd_demux_001:src7_channel -> cmd_mux_007:sink1_channel
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wire cmd_demux_001_src7_startofpacket; // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink1_startofpacket
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wire cmd_demux_001_src7_endofpacket; // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink1_endofpacket
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wire cmd_demux_001_src8_valid; // cmd_demux_001:src8_valid -> cmd_mux_008:sink1_valid
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wire [113:0] cmd_demux_001_src8_data; // cmd_demux_001:src8_data -> cmd_mux_008:sink1_data
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wire cmd_demux_001_src8_ready; // cmd_mux_008:sink1_ready -> cmd_demux_001:src8_ready
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wire [33:0] cmd_demux_001_src8_channel; // cmd_demux_001:src8_channel -> cmd_mux_008:sink1_channel
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wire cmd_demux_001_src8_startofpacket; // cmd_demux_001:src8_startofpacket -> cmd_mux_008:sink1_startofpacket
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wire cmd_demux_001_src8_endofpacket; // cmd_demux_001:src8_endofpacket -> cmd_mux_008:sink1_endofpacket
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wire cmd_demux_001_src9_valid; // cmd_demux_001:src9_valid -> cmd_mux_009:sink1_valid
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wire [113:0] cmd_demux_001_src9_data; // cmd_demux_001:src9_data -> cmd_mux_009:sink1_data
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wire cmd_demux_001_src9_ready; // cmd_mux_009:sink1_ready -> cmd_demux_001:src9_ready
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wire [33:0] cmd_demux_001_src9_channel; // cmd_demux_001:src9_channel -> cmd_mux_009:sink1_channel
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wire cmd_demux_001_src9_startofpacket; // cmd_demux_001:src9_startofpacket -> cmd_mux_009:sink1_startofpacket
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wire cmd_demux_001_src9_endofpacket; // cmd_demux_001:src9_endofpacket -> cmd_mux_009:sink1_endofpacket
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wire cmd_demux_001_src10_valid; // cmd_demux_001:src10_valid -> cmd_mux_011:sink1_valid
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wire [113:0] cmd_demux_001_src10_data; // cmd_demux_001:src10_data -> cmd_mux_011:sink1_data
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wire cmd_demux_001_src10_ready; // cmd_mux_011:sink1_ready -> cmd_demux_001:src10_ready
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wire [33:0] cmd_demux_001_src10_channel; // cmd_demux_001:src10_channel -> cmd_mux_011:sink1_channel
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wire cmd_demux_001_src10_startofpacket; // cmd_demux_001:src10_startofpacket -> cmd_mux_011:sink1_startofpacket
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wire cmd_demux_001_src10_endofpacket; // cmd_demux_001:src10_endofpacket -> cmd_mux_011:sink1_endofpacket
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wire cmd_demux_001_src11_valid; // cmd_demux_001:src11_valid -> cmd_mux_012:sink1_valid
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wire [113:0] cmd_demux_001_src11_data; // cmd_demux_001:src11_data -> cmd_mux_012:sink1_data
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wire cmd_demux_001_src11_ready; // cmd_mux_012:sink1_ready -> cmd_demux_001:src11_ready
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wire [33:0] cmd_demux_001_src11_channel; // cmd_demux_001:src11_channel -> cmd_mux_012:sink1_channel
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wire cmd_demux_001_src11_startofpacket; // cmd_demux_001:src11_startofpacket -> cmd_mux_012:sink1_startofpacket
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wire cmd_demux_001_src11_endofpacket; // cmd_demux_001:src11_endofpacket -> cmd_mux_012:sink1_endofpacket
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wire cmd_demux_001_src12_valid; // cmd_demux_001:src12_valid -> cmd_mux_013:sink1_valid
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wire [113:0] cmd_demux_001_src12_data; // cmd_demux_001:src12_data -> cmd_mux_013:sink1_data
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wire cmd_demux_001_src12_ready; // cmd_mux_013:sink1_ready -> cmd_demux_001:src12_ready
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wire [33:0] cmd_demux_001_src12_channel; // cmd_demux_001:src12_channel -> cmd_mux_013:sink1_channel
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wire cmd_demux_001_src12_startofpacket; // cmd_demux_001:src12_startofpacket -> cmd_mux_013:sink1_startofpacket
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wire cmd_demux_001_src12_endofpacket; // cmd_demux_001:src12_endofpacket -> cmd_mux_013:sink1_endofpacket
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wire cmd_demux_001_src13_valid; // cmd_demux_001:src13_valid -> cmd_mux_014:sink1_valid
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wire [113:0] cmd_demux_001_src13_data; // cmd_demux_001:src13_data -> cmd_mux_014:sink1_data
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wire cmd_demux_001_src13_ready; // cmd_mux_014:sink1_ready -> cmd_demux_001:src13_ready
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wire [33:0] cmd_demux_001_src13_channel; // cmd_demux_001:src13_channel -> cmd_mux_014:sink1_channel
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wire cmd_demux_001_src13_startofpacket; // cmd_demux_001:src13_startofpacket -> cmd_mux_014:sink1_startofpacket
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wire cmd_demux_001_src13_endofpacket; // cmd_demux_001:src13_endofpacket -> cmd_mux_014:sink1_endofpacket
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wire cmd_demux_001_src14_valid; // cmd_demux_001:src14_valid -> cmd_mux_015:sink1_valid
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wire [113:0] cmd_demux_001_src14_data; // cmd_demux_001:src14_data -> cmd_mux_015:sink1_data
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wire cmd_demux_001_src14_ready; // cmd_mux_015:sink1_ready -> cmd_demux_001:src14_ready
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wire [33:0] cmd_demux_001_src14_channel; // cmd_demux_001:src14_channel -> cmd_mux_015:sink1_channel
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wire cmd_demux_001_src14_startofpacket; // cmd_demux_001:src14_startofpacket -> cmd_mux_015:sink1_startofpacket
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wire cmd_demux_001_src14_endofpacket; // cmd_demux_001:src14_endofpacket -> cmd_mux_015:sink1_endofpacket
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wire cmd_demux_001_src15_valid; // cmd_demux_001:src15_valid -> cmd_mux_016:sink1_valid
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wire [113:0] cmd_demux_001_src15_data; // cmd_demux_001:src15_data -> cmd_mux_016:sink1_data
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wire cmd_demux_001_src15_ready; // cmd_mux_016:sink1_ready -> cmd_demux_001:src15_ready
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wire [33:0] cmd_demux_001_src15_channel; // cmd_demux_001:src15_channel -> cmd_mux_016:sink1_channel
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wire cmd_demux_001_src15_startofpacket; // cmd_demux_001:src15_startofpacket -> cmd_mux_016:sink1_startofpacket
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wire cmd_demux_001_src15_endofpacket; // cmd_demux_001:src15_endofpacket -> cmd_mux_016:sink1_endofpacket
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wire cmd_demux_001_src16_valid; // cmd_demux_001:src16_valid -> cmd_mux_017:sink1_valid
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wire [113:0] cmd_demux_001_src16_data; // cmd_demux_001:src16_data -> cmd_mux_017:sink1_data
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wire cmd_demux_001_src16_ready; // cmd_mux_017:sink1_ready -> cmd_demux_001:src16_ready
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wire [33:0] cmd_demux_001_src16_channel; // cmd_demux_001:src16_channel -> cmd_mux_017:sink1_channel
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wire cmd_demux_001_src16_startofpacket; // cmd_demux_001:src16_startofpacket -> cmd_mux_017:sink1_startofpacket
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wire cmd_demux_001_src16_endofpacket; // cmd_demux_001:src16_endofpacket -> cmd_mux_017:sink1_endofpacket
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wire cmd_demux_001_src17_valid; // cmd_demux_001:src17_valid -> cmd_mux_018:sink1_valid
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wire [113:0] cmd_demux_001_src17_data; // cmd_demux_001:src17_data -> cmd_mux_018:sink1_data
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wire cmd_demux_001_src17_ready; // cmd_mux_018:sink1_ready -> cmd_demux_001:src17_ready
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wire [33:0] cmd_demux_001_src17_channel; // cmd_demux_001:src17_channel -> cmd_mux_018:sink1_channel
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wire cmd_demux_001_src17_startofpacket; // cmd_demux_001:src17_startofpacket -> cmd_mux_018:sink1_startofpacket
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wire cmd_demux_001_src17_endofpacket; // cmd_demux_001:src17_endofpacket -> cmd_mux_018:sink1_endofpacket
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wire cmd_demux_001_src18_valid; // cmd_demux_001:src18_valid -> cmd_mux_019:sink1_valid
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wire [113:0] cmd_demux_001_src18_data; // cmd_demux_001:src18_data -> cmd_mux_019:sink1_data
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wire cmd_demux_001_src18_ready; // cmd_mux_019:sink1_ready -> cmd_demux_001:src18_ready
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wire [33:0] cmd_demux_001_src18_channel; // cmd_demux_001:src18_channel -> cmd_mux_019:sink1_channel
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wire cmd_demux_001_src18_startofpacket; // cmd_demux_001:src18_startofpacket -> cmd_mux_019:sink1_startofpacket
|
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wire cmd_demux_001_src18_endofpacket; // cmd_demux_001:src18_endofpacket -> cmd_mux_019:sink1_endofpacket
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wire cmd_demux_001_src19_valid; // cmd_demux_001:src19_valid -> cmd_mux_020:sink1_valid
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wire [113:0] cmd_demux_001_src19_data; // cmd_demux_001:src19_data -> cmd_mux_020:sink1_data
|
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wire cmd_demux_001_src19_ready; // cmd_mux_020:sink1_ready -> cmd_demux_001:src19_ready
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wire [33:0] cmd_demux_001_src19_channel; // cmd_demux_001:src19_channel -> cmd_mux_020:sink1_channel
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wire cmd_demux_001_src19_startofpacket; // cmd_demux_001:src19_startofpacket -> cmd_mux_020:sink1_startofpacket
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wire cmd_demux_001_src19_endofpacket; // cmd_demux_001:src19_endofpacket -> cmd_mux_020:sink1_endofpacket
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wire cmd_demux_001_src20_valid; // cmd_demux_001:src20_valid -> cmd_mux_021:sink1_valid
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wire [113:0] cmd_demux_001_src20_data; // cmd_demux_001:src20_data -> cmd_mux_021:sink1_data
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wire cmd_demux_001_src20_ready; // cmd_mux_021:sink1_ready -> cmd_demux_001:src20_ready
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wire [33:0] cmd_demux_001_src20_channel; // cmd_demux_001:src20_channel -> cmd_mux_021:sink1_channel
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wire cmd_demux_001_src20_startofpacket; // cmd_demux_001:src20_startofpacket -> cmd_mux_021:sink1_startofpacket
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wire cmd_demux_001_src20_endofpacket; // cmd_demux_001:src20_endofpacket -> cmd_mux_021:sink1_endofpacket
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wire cmd_demux_001_src21_valid; // cmd_demux_001:src21_valid -> cmd_mux_022:sink1_valid
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wire [113:0] cmd_demux_001_src21_data; // cmd_demux_001:src21_data -> cmd_mux_022:sink1_data
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wire cmd_demux_001_src21_ready; // cmd_mux_022:sink1_ready -> cmd_demux_001:src21_ready
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wire [33:0] cmd_demux_001_src21_channel; // cmd_demux_001:src21_channel -> cmd_mux_022:sink1_channel
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wire cmd_demux_001_src21_startofpacket; // cmd_demux_001:src21_startofpacket -> cmd_mux_022:sink1_startofpacket
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wire cmd_demux_001_src21_endofpacket; // cmd_demux_001:src21_endofpacket -> cmd_mux_022:sink1_endofpacket
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wire cmd_demux_001_src22_valid; // cmd_demux_001:src22_valid -> cmd_mux_023:sink1_valid
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wire [113:0] cmd_demux_001_src22_data; // cmd_demux_001:src22_data -> cmd_mux_023:sink1_data
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wire cmd_demux_001_src22_ready; // cmd_mux_023:sink1_ready -> cmd_demux_001:src22_ready
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wire [33:0] cmd_demux_001_src22_channel; // cmd_demux_001:src22_channel -> cmd_mux_023:sink1_channel
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wire cmd_demux_001_src22_startofpacket; // cmd_demux_001:src22_startofpacket -> cmd_mux_023:sink1_startofpacket
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wire cmd_demux_001_src22_endofpacket; // cmd_demux_001:src22_endofpacket -> cmd_mux_023:sink1_endofpacket
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wire cmd_demux_001_src23_valid; // cmd_demux_001:src23_valid -> cmd_mux_024:sink1_valid
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wire [113:0] cmd_demux_001_src23_data; // cmd_demux_001:src23_data -> cmd_mux_024:sink1_data
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wire cmd_demux_001_src23_ready; // cmd_mux_024:sink1_ready -> cmd_demux_001:src23_ready
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wire [33:0] cmd_demux_001_src23_channel; // cmd_demux_001:src23_channel -> cmd_mux_024:sink1_channel
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wire cmd_demux_001_src23_startofpacket; // cmd_demux_001:src23_startofpacket -> cmd_mux_024:sink1_startofpacket
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wire cmd_demux_001_src23_endofpacket; // cmd_demux_001:src23_endofpacket -> cmd_mux_024:sink1_endofpacket
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wire cmd_demux_001_src24_valid; // cmd_demux_001:src24_valid -> cmd_mux_025:sink1_valid
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wire [113:0] cmd_demux_001_src24_data; // cmd_demux_001:src24_data -> cmd_mux_025:sink1_data
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wire cmd_demux_001_src24_ready; // cmd_mux_025:sink1_ready -> cmd_demux_001:src24_ready
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wire [33:0] cmd_demux_001_src24_channel; // cmd_demux_001:src24_channel -> cmd_mux_025:sink1_channel
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wire cmd_demux_001_src24_startofpacket; // cmd_demux_001:src24_startofpacket -> cmd_mux_025:sink1_startofpacket
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wire cmd_demux_001_src24_endofpacket; // cmd_demux_001:src24_endofpacket -> cmd_mux_025:sink1_endofpacket
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wire cmd_demux_001_src25_valid; // cmd_demux_001:src25_valid -> cmd_mux_026:sink1_valid
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wire [113:0] cmd_demux_001_src25_data; // cmd_demux_001:src25_data -> cmd_mux_026:sink1_data
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wire cmd_demux_001_src25_ready; // cmd_mux_026:sink1_ready -> cmd_demux_001:src25_ready
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wire [33:0] cmd_demux_001_src25_channel; // cmd_demux_001:src25_channel -> cmd_mux_026:sink1_channel
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wire cmd_demux_001_src25_startofpacket; // cmd_demux_001:src25_startofpacket -> cmd_mux_026:sink1_startofpacket
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wire cmd_demux_001_src25_endofpacket; // cmd_demux_001:src25_endofpacket -> cmd_mux_026:sink1_endofpacket
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wire cmd_demux_001_src26_valid; // cmd_demux_001:src26_valid -> cmd_mux_027:sink1_valid
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wire [113:0] cmd_demux_001_src26_data; // cmd_demux_001:src26_data -> cmd_mux_027:sink1_data
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wire cmd_demux_001_src26_ready; // cmd_mux_027:sink1_ready -> cmd_demux_001:src26_ready
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wire [33:0] cmd_demux_001_src26_channel; // cmd_demux_001:src26_channel -> cmd_mux_027:sink1_channel
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wire cmd_demux_001_src26_startofpacket; // cmd_demux_001:src26_startofpacket -> cmd_mux_027:sink1_startofpacket
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wire cmd_demux_001_src26_endofpacket; // cmd_demux_001:src26_endofpacket -> cmd_mux_027:sink1_endofpacket
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wire cmd_demux_001_src27_valid; // cmd_demux_001:src27_valid -> cmd_mux_028:sink1_valid
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wire [113:0] cmd_demux_001_src27_data; // cmd_demux_001:src27_data -> cmd_mux_028:sink1_data
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wire cmd_demux_001_src27_ready; // cmd_mux_028:sink1_ready -> cmd_demux_001:src27_ready
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wire [33:0] cmd_demux_001_src27_channel; // cmd_demux_001:src27_channel -> cmd_mux_028:sink1_channel
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wire cmd_demux_001_src27_startofpacket; // cmd_demux_001:src27_startofpacket -> cmd_mux_028:sink1_startofpacket
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wire cmd_demux_001_src27_endofpacket; // cmd_demux_001:src27_endofpacket -> cmd_mux_028:sink1_endofpacket
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wire cmd_demux_001_src28_valid; // cmd_demux_001:src28_valid -> cmd_mux_029:sink1_valid
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wire [113:0] cmd_demux_001_src28_data; // cmd_demux_001:src28_data -> cmd_mux_029:sink1_data
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wire cmd_demux_001_src28_ready; // cmd_mux_029:sink1_ready -> cmd_demux_001:src28_ready
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wire [33:0] cmd_demux_001_src28_channel; // cmd_demux_001:src28_channel -> cmd_mux_029:sink1_channel
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wire cmd_demux_001_src28_startofpacket; // cmd_demux_001:src28_startofpacket -> cmd_mux_029:sink1_startofpacket
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wire cmd_demux_001_src28_endofpacket; // cmd_demux_001:src28_endofpacket -> cmd_mux_029:sink1_endofpacket
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wire cmd_demux_001_src29_valid; // cmd_demux_001:src29_valid -> cmd_mux_030:sink1_valid
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wire [113:0] cmd_demux_001_src29_data; // cmd_demux_001:src29_data -> cmd_mux_030:sink1_data
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wire cmd_demux_001_src29_ready; // cmd_mux_030:sink1_ready -> cmd_demux_001:src29_ready
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wire [33:0] cmd_demux_001_src29_channel; // cmd_demux_001:src29_channel -> cmd_mux_030:sink1_channel
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wire cmd_demux_001_src29_startofpacket; // cmd_demux_001:src29_startofpacket -> cmd_mux_030:sink1_startofpacket
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wire cmd_demux_001_src29_endofpacket; // cmd_demux_001:src29_endofpacket -> cmd_mux_030:sink1_endofpacket
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wire cmd_demux_001_src30_valid; // cmd_demux_001:src30_valid -> cmd_mux_033:sink1_valid
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wire [113:0] cmd_demux_001_src30_data; // cmd_demux_001:src30_data -> cmd_mux_033:sink1_data
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wire cmd_demux_001_src30_ready; // cmd_mux_033:sink1_ready -> cmd_demux_001:src30_ready
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wire [33:0] cmd_demux_001_src30_channel; // cmd_demux_001:src30_channel -> cmd_mux_033:sink1_channel
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wire cmd_demux_001_src30_startofpacket; // cmd_demux_001:src30_startofpacket -> cmd_mux_033:sink1_startofpacket
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wire cmd_demux_001_src30_endofpacket; // cmd_demux_001:src30_endofpacket -> cmd_mux_033:sink1_endofpacket
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wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
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wire [113:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux:sink2_data
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wire cmd_demux_002_src0_ready; // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
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wire [33:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
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wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
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wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
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wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink2_valid
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wire [113:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink2_data
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wire cmd_demux_002_src1_ready; // cmd_mux_001:sink2_ready -> cmd_demux_002:src1_ready
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wire [33:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink2_channel
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wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink2_startofpacket
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wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink2_endofpacket
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wire cmd_demux_002_src2_valid; // cmd_demux_002:src2_valid -> cmd_mux_002:sink2_valid
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wire [113:0] cmd_demux_002_src2_data; // cmd_demux_002:src2_data -> cmd_mux_002:sink2_data
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wire cmd_demux_002_src2_ready; // cmd_mux_002:sink2_ready -> cmd_demux_002:src2_ready
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wire [33:0] cmd_demux_002_src2_channel; // cmd_demux_002:src2_channel -> cmd_mux_002:sink2_channel
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wire cmd_demux_002_src2_startofpacket; // cmd_demux_002:src2_startofpacket -> cmd_mux_002:sink2_startofpacket
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wire cmd_demux_002_src2_endofpacket; // cmd_demux_002:src2_endofpacket -> cmd_mux_002:sink2_endofpacket
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wire cmd_demux_002_src3_valid; // cmd_demux_002:src3_valid -> cmd_mux_003:sink2_valid
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wire [113:0] cmd_demux_002_src3_data; // cmd_demux_002:src3_data -> cmd_mux_003:sink2_data
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wire cmd_demux_002_src3_ready; // cmd_mux_003:sink2_ready -> cmd_demux_002:src3_ready
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wire [33:0] cmd_demux_002_src3_channel; // cmd_demux_002:src3_channel -> cmd_mux_003:sink2_channel
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wire cmd_demux_002_src3_startofpacket; // cmd_demux_002:src3_startofpacket -> cmd_mux_003:sink2_startofpacket
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wire cmd_demux_002_src3_endofpacket; // cmd_demux_002:src3_endofpacket -> cmd_mux_003:sink2_endofpacket
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wire cmd_demux_002_src4_valid; // cmd_demux_002:src4_valid -> cmd_mux_004:sink2_valid
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wire [113:0] cmd_demux_002_src4_data; // cmd_demux_002:src4_data -> cmd_mux_004:sink2_data
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wire cmd_demux_002_src4_ready; // cmd_mux_004:sink2_ready -> cmd_demux_002:src4_ready
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wire [33:0] cmd_demux_002_src4_channel; // cmd_demux_002:src4_channel -> cmd_mux_004:sink2_channel
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wire cmd_demux_002_src4_startofpacket; // cmd_demux_002:src4_startofpacket -> cmd_mux_004:sink2_startofpacket
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wire cmd_demux_002_src4_endofpacket; // cmd_demux_002:src4_endofpacket -> cmd_mux_004:sink2_endofpacket
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wire cmd_demux_002_src5_valid; // cmd_demux_002:src5_valid -> cmd_mux_006:sink2_valid
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wire [113:0] cmd_demux_002_src5_data; // cmd_demux_002:src5_data -> cmd_mux_006:sink2_data
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wire cmd_demux_002_src5_ready; // cmd_mux_006:sink2_ready -> cmd_demux_002:src5_ready
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wire [33:0] cmd_demux_002_src5_channel; // cmd_demux_002:src5_channel -> cmd_mux_006:sink2_channel
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wire cmd_demux_002_src5_startofpacket; // cmd_demux_002:src5_startofpacket -> cmd_mux_006:sink2_startofpacket
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wire cmd_demux_002_src5_endofpacket; // cmd_demux_002:src5_endofpacket -> cmd_mux_006:sink2_endofpacket
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wire cmd_demux_002_src6_valid; // cmd_demux_002:src6_valid -> cmd_mux_007:sink2_valid
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wire [113:0] cmd_demux_002_src6_data; // cmd_demux_002:src6_data -> cmd_mux_007:sink2_data
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wire cmd_demux_002_src6_ready; // cmd_mux_007:sink2_ready -> cmd_demux_002:src6_ready
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wire [33:0] cmd_demux_002_src6_channel; // cmd_demux_002:src6_channel -> cmd_mux_007:sink2_channel
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wire cmd_demux_002_src6_startofpacket; // cmd_demux_002:src6_startofpacket -> cmd_mux_007:sink2_startofpacket
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wire cmd_demux_002_src6_endofpacket; // cmd_demux_002:src6_endofpacket -> cmd_mux_007:sink2_endofpacket
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wire cmd_demux_002_src7_valid; // cmd_demux_002:src7_valid -> cmd_mux_008:sink2_valid
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wire [113:0] cmd_demux_002_src7_data; // cmd_demux_002:src7_data -> cmd_mux_008:sink2_data
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wire cmd_demux_002_src7_ready; // cmd_mux_008:sink2_ready -> cmd_demux_002:src7_ready
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wire [33:0] cmd_demux_002_src7_channel; // cmd_demux_002:src7_channel -> cmd_mux_008:sink2_channel
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wire cmd_demux_002_src7_startofpacket; // cmd_demux_002:src7_startofpacket -> cmd_mux_008:sink2_startofpacket
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wire cmd_demux_002_src7_endofpacket; // cmd_demux_002:src7_endofpacket -> cmd_mux_008:sink2_endofpacket
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wire cmd_demux_002_src8_valid; // cmd_demux_002:src8_valid -> cmd_mux_009:sink2_valid
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wire [113:0] cmd_demux_002_src8_data; // cmd_demux_002:src8_data -> cmd_mux_009:sink2_data
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wire cmd_demux_002_src8_ready; // cmd_mux_009:sink2_ready -> cmd_demux_002:src8_ready
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wire [33:0] cmd_demux_002_src8_channel; // cmd_demux_002:src8_channel -> cmd_mux_009:sink2_channel
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wire cmd_demux_002_src8_startofpacket; // cmd_demux_002:src8_startofpacket -> cmd_mux_009:sink2_startofpacket
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wire cmd_demux_002_src8_endofpacket; // cmd_demux_002:src8_endofpacket -> cmd_mux_009:sink2_endofpacket
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wire cmd_demux_002_src9_valid; // cmd_demux_002:src9_valid -> cmd_mux_011:sink2_valid
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wire [113:0] cmd_demux_002_src9_data; // cmd_demux_002:src9_data -> cmd_mux_011:sink2_data
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wire cmd_demux_002_src9_ready; // cmd_mux_011:sink2_ready -> cmd_demux_002:src9_ready
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wire [33:0] cmd_demux_002_src9_channel; // cmd_demux_002:src9_channel -> cmd_mux_011:sink2_channel
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wire cmd_demux_002_src9_startofpacket; // cmd_demux_002:src9_startofpacket -> cmd_mux_011:sink2_startofpacket
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wire cmd_demux_002_src9_endofpacket; // cmd_demux_002:src9_endofpacket -> cmd_mux_011:sink2_endofpacket
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wire cmd_demux_002_src10_valid; // cmd_demux_002:src10_valid -> cmd_mux_012:sink2_valid
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wire [113:0] cmd_demux_002_src10_data; // cmd_demux_002:src10_data -> cmd_mux_012:sink2_data
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wire cmd_demux_002_src10_ready; // cmd_mux_012:sink2_ready -> cmd_demux_002:src10_ready
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wire [33:0] cmd_demux_002_src10_channel; // cmd_demux_002:src10_channel -> cmd_mux_012:sink2_channel
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wire cmd_demux_002_src10_startofpacket; // cmd_demux_002:src10_startofpacket -> cmd_mux_012:sink2_startofpacket
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wire cmd_demux_002_src10_endofpacket; // cmd_demux_002:src10_endofpacket -> cmd_mux_012:sink2_endofpacket
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wire cmd_demux_002_src11_valid; // cmd_demux_002:src11_valid -> cmd_mux_013:sink2_valid
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wire [113:0] cmd_demux_002_src11_data; // cmd_demux_002:src11_data -> cmd_mux_013:sink2_data
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wire cmd_demux_002_src11_ready; // cmd_mux_013:sink2_ready -> cmd_demux_002:src11_ready
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wire [33:0] cmd_demux_002_src11_channel; // cmd_demux_002:src11_channel -> cmd_mux_013:sink2_channel
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wire cmd_demux_002_src11_startofpacket; // cmd_demux_002:src11_startofpacket -> cmd_mux_013:sink2_startofpacket
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wire cmd_demux_002_src11_endofpacket; // cmd_demux_002:src11_endofpacket -> cmd_mux_013:sink2_endofpacket
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wire cmd_demux_002_src12_valid; // cmd_demux_002:src12_valid -> cmd_mux_014:sink2_valid
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wire [113:0] cmd_demux_002_src12_data; // cmd_demux_002:src12_data -> cmd_mux_014:sink2_data
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wire cmd_demux_002_src12_ready; // cmd_mux_014:sink2_ready -> cmd_demux_002:src12_ready
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wire [33:0] cmd_demux_002_src12_channel; // cmd_demux_002:src12_channel -> cmd_mux_014:sink2_channel
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wire cmd_demux_002_src12_startofpacket; // cmd_demux_002:src12_startofpacket -> cmd_mux_014:sink2_startofpacket
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wire cmd_demux_002_src12_endofpacket; // cmd_demux_002:src12_endofpacket -> cmd_mux_014:sink2_endofpacket
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wire cmd_demux_002_src13_valid; // cmd_demux_002:src13_valid -> cmd_mux_015:sink2_valid
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wire [113:0] cmd_demux_002_src13_data; // cmd_demux_002:src13_data -> cmd_mux_015:sink2_data
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wire cmd_demux_002_src13_ready; // cmd_mux_015:sink2_ready -> cmd_demux_002:src13_ready
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wire [33:0] cmd_demux_002_src13_channel; // cmd_demux_002:src13_channel -> cmd_mux_015:sink2_channel
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wire cmd_demux_002_src13_startofpacket; // cmd_demux_002:src13_startofpacket -> cmd_mux_015:sink2_startofpacket
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wire cmd_demux_002_src13_endofpacket; // cmd_demux_002:src13_endofpacket -> cmd_mux_015:sink2_endofpacket
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wire cmd_demux_002_src14_valid; // cmd_demux_002:src14_valid -> cmd_mux_016:sink2_valid
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wire [113:0] cmd_demux_002_src14_data; // cmd_demux_002:src14_data -> cmd_mux_016:sink2_data
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wire cmd_demux_002_src14_ready; // cmd_mux_016:sink2_ready -> cmd_demux_002:src14_ready
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wire [33:0] cmd_demux_002_src14_channel; // cmd_demux_002:src14_channel -> cmd_mux_016:sink2_channel
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wire cmd_demux_002_src14_startofpacket; // cmd_demux_002:src14_startofpacket -> cmd_mux_016:sink2_startofpacket
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wire cmd_demux_002_src14_endofpacket; // cmd_demux_002:src14_endofpacket -> cmd_mux_016:sink2_endofpacket
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wire cmd_demux_002_src15_valid; // cmd_demux_002:src15_valid -> cmd_mux_019:sink2_valid
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wire [113:0] cmd_demux_002_src15_data; // cmd_demux_002:src15_data -> cmd_mux_019:sink2_data
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wire cmd_demux_002_src15_ready; // cmd_mux_019:sink2_ready -> cmd_demux_002:src15_ready
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wire [33:0] cmd_demux_002_src15_channel; // cmd_demux_002:src15_channel -> cmd_mux_019:sink2_channel
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wire cmd_demux_002_src15_startofpacket; // cmd_demux_002:src15_startofpacket -> cmd_mux_019:sink2_startofpacket
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wire cmd_demux_002_src15_endofpacket; // cmd_demux_002:src15_endofpacket -> cmd_mux_019:sink2_endofpacket
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wire cmd_demux_002_src16_valid; // cmd_demux_002:src16_valid -> cmd_mux_020:sink2_valid
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wire [113:0] cmd_demux_002_src16_data; // cmd_demux_002:src16_data -> cmd_mux_020:sink2_data
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wire cmd_demux_002_src16_ready; // cmd_mux_020:sink2_ready -> cmd_demux_002:src16_ready
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wire [33:0] cmd_demux_002_src16_channel; // cmd_demux_002:src16_channel -> cmd_mux_020:sink2_channel
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wire cmd_demux_002_src16_startofpacket; // cmd_demux_002:src16_startofpacket -> cmd_mux_020:sink2_startofpacket
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wire cmd_demux_002_src16_endofpacket; // cmd_demux_002:src16_endofpacket -> cmd_mux_020:sink2_endofpacket
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wire cmd_demux_002_src17_valid; // cmd_demux_002:src17_valid -> cmd_mux_021:sink2_valid
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wire [113:0] cmd_demux_002_src17_data; // cmd_demux_002:src17_data -> cmd_mux_021:sink2_data
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wire cmd_demux_002_src17_ready; // cmd_mux_021:sink2_ready -> cmd_demux_002:src17_ready
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wire [33:0] cmd_demux_002_src17_channel; // cmd_demux_002:src17_channel -> cmd_mux_021:sink2_channel
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wire cmd_demux_002_src17_startofpacket; // cmd_demux_002:src17_startofpacket -> cmd_mux_021:sink2_startofpacket
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wire cmd_demux_002_src17_endofpacket; // cmd_demux_002:src17_endofpacket -> cmd_mux_021:sink2_endofpacket
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wire cmd_demux_002_src18_valid; // cmd_demux_002:src18_valid -> cmd_mux_022:sink2_valid
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wire [113:0] cmd_demux_002_src18_data; // cmd_demux_002:src18_data -> cmd_mux_022:sink2_data
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wire cmd_demux_002_src18_ready; // cmd_mux_022:sink2_ready -> cmd_demux_002:src18_ready
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wire [33:0] cmd_demux_002_src18_channel; // cmd_demux_002:src18_channel -> cmd_mux_022:sink2_channel
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wire cmd_demux_002_src18_startofpacket; // cmd_demux_002:src18_startofpacket -> cmd_mux_022:sink2_startofpacket
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wire cmd_demux_002_src18_endofpacket; // cmd_demux_002:src18_endofpacket -> cmd_mux_022:sink2_endofpacket
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wire cmd_demux_002_src19_valid; // cmd_demux_002:src19_valid -> cmd_mux_023:sink2_valid
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wire [113:0] cmd_demux_002_src19_data; // cmd_demux_002:src19_data -> cmd_mux_023:sink2_data
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wire cmd_demux_002_src19_ready; // cmd_mux_023:sink2_ready -> cmd_demux_002:src19_ready
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wire [33:0] cmd_demux_002_src19_channel; // cmd_demux_002:src19_channel -> cmd_mux_023:sink2_channel
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wire cmd_demux_002_src19_startofpacket; // cmd_demux_002:src19_startofpacket -> cmd_mux_023:sink2_startofpacket
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wire cmd_demux_002_src19_endofpacket; // cmd_demux_002:src19_endofpacket -> cmd_mux_023:sink2_endofpacket
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wire cmd_demux_002_src20_valid; // cmd_demux_002:src20_valid -> cmd_mux_024:sink2_valid
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wire [113:0] cmd_demux_002_src20_data; // cmd_demux_002:src20_data -> cmd_mux_024:sink2_data
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wire cmd_demux_002_src20_ready; // cmd_mux_024:sink2_ready -> cmd_demux_002:src20_ready
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wire [33:0] cmd_demux_002_src20_channel; // cmd_demux_002:src20_channel -> cmd_mux_024:sink2_channel
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wire cmd_demux_002_src20_startofpacket; // cmd_demux_002:src20_startofpacket -> cmd_mux_024:sink2_startofpacket
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wire cmd_demux_002_src20_endofpacket; // cmd_demux_002:src20_endofpacket -> cmd_mux_024:sink2_endofpacket
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wire cmd_demux_002_src21_valid; // cmd_demux_002:src21_valid -> cmd_mux_026:sink2_valid
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wire [113:0] cmd_demux_002_src21_data; // cmd_demux_002:src21_data -> cmd_mux_026:sink2_data
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wire cmd_demux_002_src21_ready; // cmd_mux_026:sink2_ready -> cmd_demux_002:src21_ready
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wire [33:0] cmd_demux_002_src21_channel; // cmd_demux_002:src21_channel -> cmd_mux_026:sink2_channel
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wire cmd_demux_002_src21_startofpacket; // cmd_demux_002:src21_startofpacket -> cmd_mux_026:sink2_startofpacket
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wire cmd_demux_002_src21_endofpacket; // cmd_demux_002:src21_endofpacket -> cmd_mux_026:sink2_endofpacket
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wire cmd_demux_002_src22_valid; // cmd_demux_002:src22_valid -> cmd_mux_027:sink2_valid
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wire [113:0] cmd_demux_002_src22_data; // cmd_demux_002:src22_data -> cmd_mux_027:sink2_data
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wire cmd_demux_002_src22_ready; // cmd_mux_027:sink2_ready -> cmd_demux_002:src22_ready
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wire [33:0] cmd_demux_002_src22_channel; // cmd_demux_002:src22_channel -> cmd_mux_027:sink2_channel
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wire cmd_demux_002_src22_startofpacket; // cmd_demux_002:src22_startofpacket -> cmd_mux_027:sink2_startofpacket
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wire cmd_demux_002_src22_endofpacket; // cmd_demux_002:src22_endofpacket -> cmd_mux_027:sink2_endofpacket
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wire cmd_demux_002_src23_valid; // cmd_demux_002:src23_valid -> cmd_mux_028:sink2_valid
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wire [113:0] cmd_demux_002_src23_data; // cmd_demux_002:src23_data -> cmd_mux_028:sink2_data
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wire cmd_demux_002_src23_ready; // cmd_mux_028:sink2_ready -> cmd_demux_002:src23_ready
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wire [33:0] cmd_demux_002_src23_channel; // cmd_demux_002:src23_channel -> cmd_mux_028:sink2_channel
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wire cmd_demux_002_src23_startofpacket; // cmd_demux_002:src23_startofpacket -> cmd_mux_028:sink2_startofpacket
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wire cmd_demux_002_src23_endofpacket; // cmd_demux_002:src23_endofpacket -> cmd_mux_028:sink2_endofpacket
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wire cmd_demux_002_src24_valid; // cmd_demux_002:src24_valid -> cmd_mux_029:sink2_valid
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wire [113:0] cmd_demux_002_src24_data; // cmd_demux_002:src24_data -> cmd_mux_029:sink2_data
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wire cmd_demux_002_src24_ready; // cmd_mux_029:sink2_ready -> cmd_demux_002:src24_ready
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wire [33:0] cmd_demux_002_src24_channel; // cmd_demux_002:src24_channel -> cmd_mux_029:sink2_channel
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wire cmd_demux_002_src24_startofpacket; // cmd_demux_002:src24_startofpacket -> cmd_mux_029:sink2_startofpacket
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wire cmd_demux_002_src24_endofpacket; // cmd_demux_002:src24_endofpacket -> cmd_mux_029:sink2_endofpacket
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wire cmd_demux_002_src25_valid; // cmd_demux_002:src25_valid -> cmd_mux_030:sink2_valid
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wire [113:0] cmd_demux_002_src25_data; // cmd_demux_002:src25_data -> cmd_mux_030:sink2_data
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wire cmd_demux_002_src25_ready; // cmd_mux_030:sink2_ready -> cmd_demux_002:src25_ready
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wire [33:0] cmd_demux_002_src25_channel; // cmd_demux_002:src25_channel -> cmd_mux_030:sink2_channel
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wire cmd_demux_002_src25_startofpacket; // cmd_demux_002:src25_startofpacket -> cmd_mux_030:sink2_startofpacket
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wire cmd_demux_002_src25_endofpacket; // cmd_demux_002:src25_endofpacket -> cmd_mux_030:sink2_endofpacket
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wire cmd_demux_002_src26_valid; // cmd_demux_002:src26_valid -> cmd_mux_033:sink2_valid
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wire [113:0] cmd_demux_002_src26_data; // cmd_demux_002:src26_data -> cmd_mux_033:sink2_data
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wire cmd_demux_002_src26_ready; // cmd_mux_033:sink2_ready -> cmd_demux_002:src26_ready
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wire [33:0] cmd_demux_002_src26_channel; // cmd_demux_002:src26_channel -> cmd_mux_033:sink2_channel
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wire cmd_demux_002_src26_startofpacket; // cmd_demux_002:src26_startofpacket -> cmd_mux_033:sink2_startofpacket
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wire cmd_demux_002_src26_endofpacket; // cmd_demux_002:src26_endofpacket -> cmd_mux_033:sink2_endofpacket
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wire cmd_demux_003_src0_valid; // cmd_demux_003:src0_valid -> cmd_mux_005:sink2_valid
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wire [113:0] cmd_demux_003_src0_data; // cmd_demux_003:src0_data -> cmd_mux_005:sink2_data
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wire cmd_demux_003_src0_ready; // cmd_mux_005:sink2_ready -> cmd_demux_003:src0_ready
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wire [33:0] cmd_demux_003_src0_channel; // cmd_demux_003:src0_channel -> cmd_mux_005:sink2_channel
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wire cmd_demux_003_src0_startofpacket; // cmd_demux_003:src0_startofpacket -> cmd_mux_005:sink2_startofpacket
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wire cmd_demux_003_src0_endofpacket; // cmd_demux_003:src0_endofpacket -> cmd_mux_005:sink2_endofpacket
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wire cmd_demux_003_src1_valid; // cmd_demux_003:src1_valid -> cmd_mux_011:sink3_valid
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wire [113:0] cmd_demux_003_src1_data; // cmd_demux_003:src1_data -> cmd_mux_011:sink3_data
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wire cmd_demux_003_src1_ready; // cmd_mux_011:sink3_ready -> cmd_demux_003:src1_ready
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wire [33:0] cmd_demux_003_src1_channel; // cmd_demux_003:src1_channel -> cmd_mux_011:sink3_channel
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wire cmd_demux_003_src1_startofpacket; // cmd_demux_003:src1_startofpacket -> cmd_mux_011:sink3_startofpacket
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wire cmd_demux_003_src1_endofpacket; // cmd_demux_003:src1_endofpacket -> cmd_mux_011:sink3_endofpacket
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wire cmd_demux_003_src2_valid; // cmd_demux_003:src2_valid -> cmd_mux_012:sink3_valid
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wire [113:0] cmd_demux_003_src2_data; // cmd_demux_003:src2_data -> cmd_mux_012:sink3_data
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wire cmd_demux_003_src2_ready; // cmd_mux_012:sink3_ready -> cmd_demux_003:src2_ready
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wire [33:0] cmd_demux_003_src2_channel; // cmd_demux_003:src2_channel -> cmd_mux_012:sink3_channel
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wire cmd_demux_003_src2_startofpacket; // cmd_demux_003:src2_startofpacket -> cmd_mux_012:sink3_startofpacket
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wire cmd_demux_003_src2_endofpacket; // cmd_demux_003:src2_endofpacket -> cmd_mux_012:sink3_endofpacket
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wire cmd_demux_003_src3_valid; // cmd_demux_003:src3_valid -> cmd_mux_013:sink3_valid
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wire [113:0] cmd_demux_003_src3_data; // cmd_demux_003:src3_data -> cmd_mux_013:sink3_data
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wire cmd_demux_003_src3_ready; // cmd_mux_013:sink3_ready -> cmd_demux_003:src3_ready
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wire [33:0] cmd_demux_003_src3_channel; // cmd_demux_003:src3_channel -> cmd_mux_013:sink3_channel
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wire cmd_demux_003_src3_startofpacket; // cmd_demux_003:src3_startofpacket -> cmd_mux_013:sink3_startofpacket
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wire cmd_demux_003_src3_endofpacket; // cmd_demux_003:src3_endofpacket -> cmd_mux_013:sink3_endofpacket
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wire cmd_demux_003_src4_valid; // cmd_demux_003:src4_valid -> cmd_mux_014:sink3_valid
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wire [113:0] cmd_demux_003_src4_data; // cmd_demux_003:src4_data -> cmd_mux_014:sink3_data
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wire cmd_demux_003_src4_ready; // cmd_mux_014:sink3_ready -> cmd_demux_003:src4_ready
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wire [33:0] cmd_demux_003_src4_channel; // cmd_demux_003:src4_channel -> cmd_mux_014:sink3_channel
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wire cmd_demux_003_src4_startofpacket; // cmd_demux_003:src4_startofpacket -> cmd_mux_014:sink3_startofpacket
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wire cmd_demux_003_src4_endofpacket; // cmd_demux_003:src4_endofpacket -> cmd_mux_014:sink3_endofpacket
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wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
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wire [113:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
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wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
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wire [33:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
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wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
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wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
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wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
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wire [113:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
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wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
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wire [33:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
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wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
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wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
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wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
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wire [113:0] rsp_demux_src2_data; // rsp_demux:src2_data -> rsp_mux_002:sink0_data
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wire rsp_demux_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
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wire [33:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
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wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
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wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
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wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
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wire [113:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
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wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
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wire [33:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
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wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
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wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
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wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
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wire [113:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
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wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
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wire [33:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
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wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
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wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
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wire rsp_demux_001_src2_valid; // rsp_demux_001:src2_valid -> rsp_mux_002:sink1_valid
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wire [113:0] rsp_demux_001_src2_data; // rsp_demux_001:src2_data -> rsp_mux_002:sink1_data
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wire rsp_demux_001_src2_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src2_ready
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wire [33:0] rsp_demux_001_src2_channel; // rsp_demux_001:src2_channel -> rsp_mux_002:sink1_channel
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wire rsp_demux_001_src2_startofpacket; // rsp_demux_001:src2_startofpacket -> rsp_mux_002:sink1_startofpacket
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wire rsp_demux_001_src2_endofpacket; // rsp_demux_001:src2_endofpacket -> rsp_mux_002:sink1_endofpacket
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wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
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wire [113:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
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wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
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wire [33:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
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wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
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wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
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wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
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wire [113:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
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wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
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wire [33:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
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wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
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wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
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wire rsp_demux_002_src2_valid; // rsp_demux_002:src2_valid -> rsp_mux_002:sink2_valid
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wire [113:0] rsp_demux_002_src2_data; // rsp_demux_002:src2_data -> rsp_mux_002:sink2_data
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wire rsp_demux_002_src2_ready; // rsp_mux_002:sink2_ready -> rsp_demux_002:src2_ready
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wire [33:0] rsp_demux_002_src2_channel; // rsp_demux_002:src2_channel -> rsp_mux_002:sink2_channel
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wire rsp_demux_002_src2_startofpacket; // rsp_demux_002:src2_startofpacket -> rsp_mux_002:sink2_startofpacket
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wire rsp_demux_002_src2_endofpacket; // rsp_demux_002:src2_endofpacket -> rsp_mux_002:sink2_endofpacket
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wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
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wire [113:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
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wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
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wire [33:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
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wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
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wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
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wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink3_valid
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wire [113:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink3_data
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wire rsp_demux_003_src1_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src1_ready
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wire [33:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink3_channel
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wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink3_startofpacket
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wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink3_endofpacket
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wire rsp_demux_003_src2_valid; // rsp_demux_003:src2_valid -> rsp_mux_002:sink3_valid
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wire [113:0] rsp_demux_003_src2_data; // rsp_demux_003:src2_data -> rsp_mux_002:sink3_data
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wire rsp_demux_003_src2_ready; // rsp_mux_002:sink3_ready -> rsp_demux_003:src2_ready
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wire [33:0] rsp_demux_003_src2_channel; // rsp_demux_003:src2_channel -> rsp_mux_002:sink3_channel
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wire rsp_demux_003_src2_startofpacket; // rsp_demux_003:src2_startofpacket -> rsp_mux_002:sink3_startofpacket
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wire rsp_demux_003_src2_endofpacket; // rsp_demux_003:src2_endofpacket -> rsp_mux_002:sink3_endofpacket
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wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
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wire [113:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
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wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
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wire [33:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
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wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
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wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
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wire rsp_demux_004_src1_valid; // rsp_demux_004:src1_valid -> rsp_mux_001:sink4_valid
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wire [113:0] rsp_demux_004_src1_data; // rsp_demux_004:src1_data -> rsp_mux_001:sink4_data
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wire rsp_demux_004_src1_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src1_ready
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wire [33:0] rsp_demux_004_src1_channel; // rsp_demux_004:src1_channel -> rsp_mux_001:sink4_channel
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wire rsp_demux_004_src1_startofpacket; // rsp_demux_004:src1_startofpacket -> rsp_mux_001:sink4_startofpacket
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wire rsp_demux_004_src1_endofpacket; // rsp_demux_004:src1_endofpacket -> rsp_mux_001:sink4_endofpacket
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wire rsp_demux_004_src2_valid; // rsp_demux_004:src2_valid -> rsp_mux_002:sink4_valid
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wire [113:0] rsp_demux_004_src2_data; // rsp_demux_004:src2_data -> rsp_mux_002:sink4_data
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wire rsp_demux_004_src2_ready; // rsp_mux_002:sink4_ready -> rsp_demux_004:src2_ready
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wire [33:0] rsp_demux_004_src2_channel; // rsp_demux_004:src2_channel -> rsp_mux_002:sink4_channel
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wire rsp_demux_004_src2_startofpacket; // rsp_demux_004:src2_startofpacket -> rsp_mux_002:sink4_startofpacket
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wire rsp_demux_004_src2_endofpacket; // rsp_demux_004:src2_endofpacket -> rsp_mux_002:sink4_endofpacket
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wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
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wire [113:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
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wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
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wire [33:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
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wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
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wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
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wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> rsp_mux_001:sink5_valid
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wire [113:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> rsp_mux_001:sink5_data
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wire rsp_demux_005_src1_ready; // rsp_mux_001:sink5_ready -> rsp_demux_005:src1_ready
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wire [33:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> rsp_mux_001:sink5_channel
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wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> rsp_mux_001:sink5_startofpacket
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wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> rsp_mux_001:sink5_endofpacket
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wire rsp_demux_005_src2_valid; // rsp_demux_005:src2_valid -> rsp_mux_003:sink0_valid
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wire [113:0] rsp_demux_005_src2_data; // rsp_demux_005:src2_data -> rsp_mux_003:sink0_data
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wire rsp_demux_005_src2_ready; // rsp_mux_003:sink0_ready -> rsp_demux_005:src2_ready
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wire [33:0] rsp_demux_005_src2_channel; // rsp_demux_005:src2_channel -> rsp_mux_003:sink0_channel
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wire rsp_demux_005_src2_startofpacket; // rsp_demux_005:src2_startofpacket -> rsp_mux_003:sink0_startofpacket
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wire rsp_demux_005_src2_endofpacket; // rsp_demux_005:src2_endofpacket -> rsp_mux_003:sink0_endofpacket
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wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
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wire [113:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
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wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
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wire [33:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
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wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
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wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
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wire rsp_demux_006_src1_valid; // rsp_demux_006:src1_valid -> rsp_mux_001:sink6_valid
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wire [113:0] rsp_demux_006_src1_data; // rsp_demux_006:src1_data -> rsp_mux_001:sink6_data
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wire rsp_demux_006_src1_ready; // rsp_mux_001:sink6_ready -> rsp_demux_006:src1_ready
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wire [33:0] rsp_demux_006_src1_channel; // rsp_demux_006:src1_channel -> rsp_mux_001:sink6_channel
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wire rsp_demux_006_src1_startofpacket; // rsp_demux_006:src1_startofpacket -> rsp_mux_001:sink6_startofpacket
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wire rsp_demux_006_src1_endofpacket; // rsp_demux_006:src1_endofpacket -> rsp_mux_001:sink6_endofpacket
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wire rsp_demux_006_src2_valid; // rsp_demux_006:src2_valid -> rsp_mux_002:sink5_valid
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wire [113:0] rsp_demux_006_src2_data; // rsp_demux_006:src2_data -> rsp_mux_002:sink5_data
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wire rsp_demux_006_src2_ready; // rsp_mux_002:sink5_ready -> rsp_demux_006:src2_ready
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wire [33:0] rsp_demux_006_src2_channel; // rsp_demux_006:src2_channel -> rsp_mux_002:sink5_channel
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wire rsp_demux_006_src2_startofpacket; // rsp_demux_006:src2_startofpacket -> rsp_mux_002:sink5_startofpacket
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wire rsp_demux_006_src2_endofpacket; // rsp_demux_006:src2_endofpacket -> rsp_mux_002:sink5_endofpacket
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wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
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wire [113:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
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wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
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wire [33:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
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wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
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wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
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wire rsp_demux_007_src1_valid; // rsp_demux_007:src1_valid -> rsp_mux_001:sink7_valid
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wire [113:0] rsp_demux_007_src1_data; // rsp_demux_007:src1_data -> rsp_mux_001:sink7_data
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wire rsp_demux_007_src1_ready; // rsp_mux_001:sink7_ready -> rsp_demux_007:src1_ready
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wire [33:0] rsp_demux_007_src1_channel; // rsp_demux_007:src1_channel -> rsp_mux_001:sink7_channel
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wire rsp_demux_007_src1_startofpacket; // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink7_startofpacket
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wire rsp_demux_007_src1_endofpacket; // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink7_endofpacket
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wire rsp_demux_007_src2_valid; // rsp_demux_007:src2_valid -> rsp_mux_002:sink6_valid
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wire [113:0] rsp_demux_007_src2_data; // rsp_demux_007:src2_data -> rsp_mux_002:sink6_data
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wire rsp_demux_007_src2_ready; // rsp_mux_002:sink6_ready -> rsp_demux_007:src2_ready
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wire [33:0] rsp_demux_007_src2_channel; // rsp_demux_007:src2_channel -> rsp_mux_002:sink6_channel
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wire rsp_demux_007_src2_startofpacket; // rsp_demux_007:src2_startofpacket -> rsp_mux_002:sink6_startofpacket
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wire rsp_demux_007_src2_endofpacket; // rsp_demux_007:src2_endofpacket -> rsp_mux_002:sink6_endofpacket
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wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
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wire [113:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux:sink8_data
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wire rsp_demux_008_src0_ready; // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
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wire [33:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
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wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
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wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
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wire rsp_demux_008_src1_valid; // rsp_demux_008:src1_valid -> rsp_mux_001:sink8_valid
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wire [113:0] rsp_demux_008_src1_data; // rsp_demux_008:src1_data -> rsp_mux_001:sink8_data
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wire rsp_demux_008_src1_ready; // rsp_mux_001:sink8_ready -> rsp_demux_008:src1_ready
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wire [33:0] rsp_demux_008_src1_channel; // rsp_demux_008:src1_channel -> rsp_mux_001:sink8_channel
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wire rsp_demux_008_src1_startofpacket; // rsp_demux_008:src1_startofpacket -> rsp_mux_001:sink8_startofpacket
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wire rsp_demux_008_src1_endofpacket; // rsp_demux_008:src1_endofpacket -> rsp_mux_001:sink8_endofpacket
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wire rsp_demux_008_src2_valid; // rsp_demux_008:src2_valid -> rsp_mux_002:sink7_valid
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wire [113:0] rsp_demux_008_src2_data; // rsp_demux_008:src2_data -> rsp_mux_002:sink7_data
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wire rsp_demux_008_src2_ready; // rsp_mux_002:sink7_ready -> rsp_demux_008:src2_ready
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wire [33:0] rsp_demux_008_src2_channel; // rsp_demux_008:src2_channel -> rsp_mux_002:sink7_channel
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wire rsp_demux_008_src2_startofpacket; // rsp_demux_008:src2_startofpacket -> rsp_mux_002:sink7_startofpacket
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wire rsp_demux_008_src2_endofpacket; // rsp_demux_008:src2_endofpacket -> rsp_mux_002:sink7_endofpacket
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wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
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wire [113:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux:sink9_data
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wire rsp_demux_009_src0_ready; // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
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wire [33:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
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wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
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wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
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wire rsp_demux_009_src1_valid; // rsp_demux_009:src1_valid -> rsp_mux_001:sink9_valid
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wire [113:0] rsp_demux_009_src1_data; // rsp_demux_009:src1_data -> rsp_mux_001:sink9_data
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wire rsp_demux_009_src1_ready; // rsp_mux_001:sink9_ready -> rsp_demux_009:src1_ready
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wire [33:0] rsp_demux_009_src1_channel; // rsp_demux_009:src1_channel -> rsp_mux_001:sink9_channel
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wire rsp_demux_009_src1_startofpacket; // rsp_demux_009:src1_startofpacket -> rsp_mux_001:sink9_startofpacket
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wire rsp_demux_009_src1_endofpacket; // rsp_demux_009:src1_endofpacket -> rsp_mux_001:sink9_endofpacket
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wire rsp_demux_009_src2_valid; // rsp_demux_009:src2_valid -> rsp_mux_002:sink8_valid
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wire [113:0] rsp_demux_009_src2_data; // rsp_demux_009:src2_data -> rsp_mux_002:sink8_data
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wire rsp_demux_009_src2_ready; // rsp_mux_002:sink8_ready -> rsp_demux_009:src2_ready
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wire [33:0] rsp_demux_009_src2_channel; // rsp_demux_009:src2_channel -> rsp_mux_002:sink8_channel
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wire rsp_demux_009_src2_startofpacket; // rsp_demux_009:src2_startofpacket -> rsp_mux_002:sink8_startofpacket
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wire rsp_demux_009_src2_endofpacket; // rsp_demux_009:src2_endofpacket -> rsp_mux_002:sink8_endofpacket
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wire rsp_demux_010_src0_valid; // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
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wire [113:0] rsp_demux_010_src0_data; // rsp_demux_010:src0_data -> rsp_mux:sink10_data
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wire rsp_demux_010_src0_ready; // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
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wire [33:0] rsp_demux_010_src0_channel; // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
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wire rsp_demux_010_src0_startofpacket; // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
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wire rsp_demux_010_src0_endofpacket; // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
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wire rsp_demux_011_src0_valid; // rsp_demux_011:src0_valid -> rsp_mux:sink11_valid
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wire [113:0] rsp_demux_011_src0_data; // rsp_demux_011:src0_data -> rsp_mux:sink11_data
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wire rsp_demux_011_src0_ready; // rsp_mux:sink11_ready -> rsp_demux_011:src0_ready
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wire [33:0] rsp_demux_011_src0_channel; // rsp_demux_011:src0_channel -> rsp_mux:sink11_channel
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wire rsp_demux_011_src0_startofpacket; // rsp_demux_011:src0_startofpacket -> rsp_mux:sink11_startofpacket
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wire rsp_demux_011_src0_endofpacket; // rsp_demux_011:src0_endofpacket -> rsp_mux:sink11_endofpacket
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wire rsp_demux_011_src1_valid; // rsp_demux_011:src1_valid -> rsp_mux_001:sink10_valid
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wire [113:0] rsp_demux_011_src1_data; // rsp_demux_011:src1_data -> rsp_mux_001:sink10_data
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wire rsp_demux_011_src1_ready; // rsp_mux_001:sink10_ready -> rsp_demux_011:src1_ready
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wire [33:0] rsp_demux_011_src1_channel; // rsp_demux_011:src1_channel -> rsp_mux_001:sink10_channel
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wire rsp_demux_011_src1_startofpacket; // rsp_demux_011:src1_startofpacket -> rsp_mux_001:sink10_startofpacket
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wire rsp_demux_011_src1_endofpacket; // rsp_demux_011:src1_endofpacket -> rsp_mux_001:sink10_endofpacket
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wire rsp_demux_011_src2_valid; // rsp_demux_011:src2_valid -> rsp_mux_002:sink9_valid
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wire [113:0] rsp_demux_011_src2_data; // rsp_demux_011:src2_data -> rsp_mux_002:sink9_data
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wire rsp_demux_011_src2_ready; // rsp_mux_002:sink9_ready -> rsp_demux_011:src2_ready
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wire [33:0] rsp_demux_011_src2_channel; // rsp_demux_011:src2_channel -> rsp_mux_002:sink9_channel
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wire rsp_demux_011_src2_startofpacket; // rsp_demux_011:src2_startofpacket -> rsp_mux_002:sink9_startofpacket
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wire rsp_demux_011_src2_endofpacket; // rsp_demux_011:src2_endofpacket -> rsp_mux_002:sink9_endofpacket
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wire rsp_demux_011_src3_valid; // rsp_demux_011:src3_valid -> rsp_mux_003:sink1_valid
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wire [113:0] rsp_demux_011_src3_data; // rsp_demux_011:src3_data -> rsp_mux_003:sink1_data
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wire rsp_demux_011_src3_ready; // rsp_mux_003:sink1_ready -> rsp_demux_011:src3_ready
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wire [33:0] rsp_demux_011_src3_channel; // rsp_demux_011:src3_channel -> rsp_mux_003:sink1_channel
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wire rsp_demux_011_src3_startofpacket; // rsp_demux_011:src3_startofpacket -> rsp_mux_003:sink1_startofpacket
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wire rsp_demux_011_src3_endofpacket; // rsp_demux_011:src3_endofpacket -> rsp_mux_003:sink1_endofpacket
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wire rsp_demux_012_src0_valid; // rsp_demux_012:src0_valid -> rsp_mux:sink12_valid
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wire [113:0] rsp_demux_012_src0_data; // rsp_demux_012:src0_data -> rsp_mux:sink12_data
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wire rsp_demux_012_src0_ready; // rsp_mux:sink12_ready -> rsp_demux_012:src0_ready
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wire [33:0] rsp_demux_012_src0_channel; // rsp_demux_012:src0_channel -> rsp_mux:sink12_channel
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wire rsp_demux_012_src0_startofpacket; // rsp_demux_012:src0_startofpacket -> rsp_mux:sink12_startofpacket
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wire rsp_demux_012_src0_endofpacket; // rsp_demux_012:src0_endofpacket -> rsp_mux:sink12_endofpacket
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wire rsp_demux_012_src1_valid; // rsp_demux_012:src1_valid -> rsp_mux_001:sink11_valid
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wire [113:0] rsp_demux_012_src1_data; // rsp_demux_012:src1_data -> rsp_mux_001:sink11_data
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wire rsp_demux_012_src1_ready; // rsp_mux_001:sink11_ready -> rsp_demux_012:src1_ready
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wire [33:0] rsp_demux_012_src1_channel; // rsp_demux_012:src1_channel -> rsp_mux_001:sink11_channel
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wire rsp_demux_012_src1_startofpacket; // rsp_demux_012:src1_startofpacket -> rsp_mux_001:sink11_startofpacket
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wire rsp_demux_012_src1_endofpacket; // rsp_demux_012:src1_endofpacket -> rsp_mux_001:sink11_endofpacket
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wire rsp_demux_012_src2_valid; // rsp_demux_012:src2_valid -> rsp_mux_002:sink10_valid
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wire [113:0] rsp_demux_012_src2_data; // rsp_demux_012:src2_data -> rsp_mux_002:sink10_data
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wire rsp_demux_012_src2_ready; // rsp_mux_002:sink10_ready -> rsp_demux_012:src2_ready
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wire [33:0] rsp_demux_012_src2_channel; // rsp_demux_012:src2_channel -> rsp_mux_002:sink10_channel
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wire rsp_demux_012_src2_startofpacket; // rsp_demux_012:src2_startofpacket -> rsp_mux_002:sink10_startofpacket
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wire rsp_demux_012_src2_endofpacket; // rsp_demux_012:src2_endofpacket -> rsp_mux_002:sink10_endofpacket
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wire rsp_demux_012_src3_valid; // rsp_demux_012:src3_valid -> rsp_mux_003:sink2_valid
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wire [113:0] rsp_demux_012_src3_data; // rsp_demux_012:src3_data -> rsp_mux_003:sink2_data
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wire rsp_demux_012_src3_ready; // rsp_mux_003:sink2_ready -> rsp_demux_012:src3_ready
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wire [33:0] rsp_demux_012_src3_channel; // rsp_demux_012:src3_channel -> rsp_mux_003:sink2_channel
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wire rsp_demux_012_src3_startofpacket; // rsp_demux_012:src3_startofpacket -> rsp_mux_003:sink2_startofpacket
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wire rsp_demux_012_src3_endofpacket; // rsp_demux_012:src3_endofpacket -> rsp_mux_003:sink2_endofpacket
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wire rsp_demux_013_src0_valid; // rsp_demux_013:src0_valid -> rsp_mux:sink13_valid
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wire [113:0] rsp_demux_013_src0_data; // rsp_demux_013:src0_data -> rsp_mux:sink13_data
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wire rsp_demux_013_src0_ready; // rsp_mux:sink13_ready -> rsp_demux_013:src0_ready
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wire [33:0] rsp_demux_013_src0_channel; // rsp_demux_013:src0_channel -> rsp_mux:sink13_channel
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wire rsp_demux_013_src0_startofpacket; // rsp_demux_013:src0_startofpacket -> rsp_mux:sink13_startofpacket
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wire rsp_demux_013_src0_endofpacket; // rsp_demux_013:src0_endofpacket -> rsp_mux:sink13_endofpacket
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wire rsp_demux_013_src1_valid; // rsp_demux_013:src1_valid -> rsp_mux_001:sink12_valid
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wire [113:0] rsp_demux_013_src1_data; // rsp_demux_013:src1_data -> rsp_mux_001:sink12_data
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wire rsp_demux_013_src1_ready; // rsp_mux_001:sink12_ready -> rsp_demux_013:src1_ready
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wire [33:0] rsp_demux_013_src1_channel; // rsp_demux_013:src1_channel -> rsp_mux_001:sink12_channel
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wire rsp_demux_013_src1_startofpacket; // rsp_demux_013:src1_startofpacket -> rsp_mux_001:sink12_startofpacket
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wire rsp_demux_013_src1_endofpacket; // rsp_demux_013:src1_endofpacket -> rsp_mux_001:sink12_endofpacket
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wire rsp_demux_013_src2_valid; // rsp_demux_013:src2_valid -> rsp_mux_002:sink11_valid
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wire [113:0] rsp_demux_013_src2_data; // rsp_demux_013:src2_data -> rsp_mux_002:sink11_data
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wire rsp_demux_013_src2_ready; // rsp_mux_002:sink11_ready -> rsp_demux_013:src2_ready
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wire [33:0] rsp_demux_013_src2_channel; // rsp_demux_013:src2_channel -> rsp_mux_002:sink11_channel
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wire rsp_demux_013_src2_startofpacket; // rsp_demux_013:src2_startofpacket -> rsp_mux_002:sink11_startofpacket
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wire rsp_demux_013_src2_endofpacket; // rsp_demux_013:src2_endofpacket -> rsp_mux_002:sink11_endofpacket
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wire rsp_demux_013_src3_valid; // rsp_demux_013:src3_valid -> rsp_mux_003:sink3_valid
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wire [113:0] rsp_demux_013_src3_data; // rsp_demux_013:src3_data -> rsp_mux_003:sink3_data
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wire rsp_demux_013_src3_ready; // rsp_mux_003:sink3_ready -> rsp_demux_013:src3_ready
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wire [33:0] rsp_demux_013_src3_channel; // rsp_demux_013:src3_channel -> rsp_mux_003:sink3_channel
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wire rsp_demux_013_src3_startofpacket; // rsp_demux_013:src3_startofpacket -> rsp_mux_003:sink3_startofpacket
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wire rsp_demux_013_src3_endofpacket; // rsp_demux_013:src3_endofpacket -> rsp_mux_003:sink3_endofpacket
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wire rsp_demux_014_src0_valid; // rsp_demux_014:src0_valid -> rsp_mux:sink14_valid
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wire [113:0] rsp_demux_014_src0_data; // rsp_demux_014:src0_data -> rsp_mux:sink14_data
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wire rsp_demux_014_src0_ready; // rsp_mux:sink14_ready -> rsp_demux_014:src0_ready
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wire [33:0] rsp_demux_014_src0_channel; // rsp_demux_014:src0_channel -> rsp_mux:sink14_channel
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wire rsp_demux_014_src0_startofpacket; // rsp_demux_014:src0_startofpacket -> rsp_mux:sink14_startofpacket
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wire rsp_demux_014_src0_endofpacket; // rsp_demux_014:src0_endofpacket -> rsp_mux:sink14_endofpacket
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wire rsp_demux_014_src1_valid; // rsp_demux_014:src1_valid -> rsp_mux_001:sink13_valid
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wire [113:0] rsp_demux_014_src1_data; // rsp_demux_014:src1_data -> rsp_mux_001:sink13_data
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wire rsp_demux_014_src1_ready; // rsp_mux_001:sink13_ready -> rsp_demux_014:src1_ready
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wire [33:0] rsp_demux_014_src1_channel; // rsp_demux_014:src1_channel -> rsp_mux_001:sink13_channel
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wire rsp_demux_014_src1_startofpacket; // rsp_demux_014:src1_startofpacket -> rsp_mux_001:sink13_startofpacket
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wire rsp_demux_014_src1_endofpacket; // rsp_demux_014:src1_endofpacket -> rsp_mux_001:sink13_endofpacket
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wire rsp_demux_014_src2_valid; // rsp_demux_014:src2_valid -> rsp_mux_002:sink12_valid
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wire [113:0] rsp_demux_014_src2_data; // rsp_demux_014:src2_data -> rsp_mux_002:sink12_data
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wire rsp_demux_014_src2_ready; // rsp_mux_002:sink12_ready -> rsp_demux_014:src2_ready
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wire [33:0] rsp_demux_014_src2_channel; // rsp_demux_014:src2_channel -> rsp_mux_002:sink12_channel
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wire rsp_demux_014_src2_startofpacket; // rsp_demux_014:src2_startofpacket -> rsp_mux_002:sink12_startofpacket
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wire rsp_demux_014_src2_endofpacket; // rsp_demux_014:src2_endofpacket -> rsp_mux_002:sink12_endofpacket
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wire rsp_demux_014_src3_valid; // rsp_demux_014:src3_valid -> rsp_mux_003:sink4_valid
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wire [113:0] rsp_demux_014_src3_data; // rsp_demux_014:src3_data -> rsp_mux_003:sink4_data
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wire rsp_demux_014_src3_ready; // rsp_mux_003:sink4_ready -> rsp_demux_014:src3_ready
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wire [33:0] rsp_demux_014_src3_channel; // rsp_demux_014:src3_channel -> rsp_mux_003:sink4_channel
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wire rsp_demux_014_src3_startofpacket; // rsp_demux_014:src3_startofpacket -> rsp_mux_003:sink4_startofpacket
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wire rsp_demux_014_src3_endofpacket; // rsp_demux_014:src3_endofpacket -> rsp_mux_003:sink4_endofpacket
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wire rsp_demux_015_src0_valid; // rsp_demux_015:src0_valid -> rsp_mux:sink15_valid
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wire [113:0] rsp_demux_015_src0_data; // rsp_demux_015:src0_data -> rsp_mux:sink15_data
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wire rsp_demux_015_src0_ready; // rsp_mux:sink15_ready -> rsp_demux_015:src0_ready
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wire [33:0] rsp_demux_015_src0_channel; // rsp_demux_015:src0_channel -> rsp_mux:sink15_channel
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wire rsp_demux_015_src0_startofpacket; // rsp_demux_015:src0_startofpacket -> rsp_mux:sink15_startofpacket
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wire rsp_demux_015_src0_endofpacket; // rsp_demux_015:src0_endofpacket -> rsp_mux:sink15_endofpacket
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wire rsp_demux_015_src1_valid; // rsp_demux_015:src1_valid -> rsp_mux_001:sink14_valid
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wire [113:0] rsp_demux_015_src1_data; // rsp_demux_015:src1_data -> rsp_mux_001:sink14_data
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wire rsp_demux_015_src1_ready; // rsp_mux_001:sink14_ready -> rsp_demux_015:src1_ready
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wire [33:0] rsp_demux_015_src1_channel; // rsp_demux_015:src1_channel -> rsp_mux_001:sink14_channel
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wire rsp_demux_015_src1_startofpacket; // rsp_demux_015:src1_startofpacket -> rsp_mux_001:sink14_startofpacket
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wire rsp_demux_015_src1_endofpacket; // rsp_demux_015:src1_endofpacket -> rsp_mux_001:sink14_endofpacket
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wire rsp_demux_015_src2_valid; // rsp_demux_015:src2_valid -> rsp_mux_002:sink13_valid
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wire [113:0] rsp_demux_015_src2_data; // rsp_demux_015:src2_data -> rsp_mux_002:sink13_data
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wire rsp_demux_015_src2_ready; // rsp_mux_002:sink13_ready -> rsp_demux_015:src2_ready
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wire [33:0] rsp_demux_015_src2_channel; // rsp_demux_015:src2_channel -> rsp_mux_002:sink13_channel
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wire rsp_demux_015_src2_startofpacket; // rsp_demux_015:src2_startofpacket -> rsp_mux_002:sink13_startofpacket
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wire rsp_demux_015_src2_endofpacket; // rsp_demux_015:src2_endofpacket -> rsp_mux_002:sink13_endofpacket
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wire rsp_demux_016_src0_valid; // rsp_demux_016:src0_valid -> rsp_mux:sink16_valid
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wire [113:0] rsp_demux_016_src0_data; // rsp_demux_016:src0_data -> rsp_mux:sink16_data
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wire rsp_demux_016_src0_ready; // rsp_mux:sink16_ready -> rsp_demux_016:src0_ready
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wire [33:0] rsp_demux_016_src0_channel; // rsp_demux_016:src0_channel -> rsp_mux:sink16_channel
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wire rsp_demux_016_src0_startofpacket; // rsp_demux_016:src0_startofpacket -> rsp_mux:sink16_startofpacket
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wire rsp_demux_016_src0_endofpacket; // rsp_demux_016:src0_endofpacket -> rsp_mux:sink16_endofpacket
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wire rsp_demux_016_src1_valid; // rsp_demux_016:src1_valid -> rsp_mux_001:sink15_valid
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wire [113:0] rsp_demux_016_src1_data; // rsp_demux_016:src1_data -> rsp_mux_001:sink15_data
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wire rsp_demux_016_src1_ready; // rsp_mux_001:sink15_ready -> rsp_demux_016:src1_ready
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wire [33:0] rsp_demux_016_src1_channel; // rsp_demux_016:src1_channel -> rsp_mux_001:sink15_channel
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wire rsp_demux_016_src1_startofpacket; // rsp_demux_016:src1_startofpacket -> rsp_mux_001:sink15_startofpacket
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wire rsp_demux_016_src1_endofpacket; // rsp_demux_016:src1_endofpacket -> rsp_mux_001:sink15_endofpacket
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wire rsp_demux_016_src2_valid; // rsp_demux_016:src2_valid -> rsp_mux_002:sink14_valid
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wire [113:0] rsp_demux_016_src2_data; // rsp_demux_016:src2_data -> rsp_mux_002:sink14_data
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wire rsp_demux_016_src2_ready; // rsp_mux_002:sink14_ready -> rsp_demux_016:src2_ready
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wire [33:0] rsp_demux_016_src2_channel; // rsp_demux_016:src2_channel -> rsp_mux_002:sink14_channel
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wire rsp_demux_016_src2_startofpacket; // rsp_demux_016:src2_startofpacket -> rsp_mux_002:sink14_startofpacket
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wire rsp_demux_016_src2_endofpacket; // rsp_demux_016:src2_endofpacket -> rsp_mux_002:sink14_endofpacket
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wire rsp_demux_017_src0_valid; // rsp_demux_017:src0_valid -> rsp_mux:sink17_valid
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wire [113:0] rsp_demux_017_src0_data; // rsp_demux_017:src0_data -> rsp_mux:sink17_data
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wire rsp_demux_017_src0_ready; // rsp_mux:sink17_ready -> rsp_demux_017:src0_ready
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wire [33:0] rsp_demux_017_src0_channel; // rsp_demux_017:src0_channel -> rsp_mux:sink17_channel
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wire rsp_demux_017_src0_startofpacket; // rsp_demux_017:src0_startofpacket -> rsp_mux:sink17_startofpacket
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wire rsp_demux_017_src0_endofpacket; // rsp_demux_017:src0_endofpacket -> rsp_mux:sink17_endofpacket
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wire rsp_demux_017_src1_valid; // rsp_demux_017:src1_valid -> rsp_mux_001:sink16_valid
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wire [113:0] rsp_demux_017_src1_data; // rsp_demux_017:src1_data -> rsp_mux_001:sink16_data
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wire rsp_demux_017_src1_ready; // rsp_mux_001:sink16_ready -> rsp_demux_017:src1_ready
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wire [33:0] rsp_demux_017_src1_channel; // rsp_demux_017:src1_channel -> rsp_mux_001:sink16_channel
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wire rsp_demux_017_src1_startofpacket; // rsp_demux_017:src1_startofpacket -> rsp_mux_001:sink16_startofpacket
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wire rsp_demux_017_src1_endofpacket; // rsp_demux_017:src1_endofpacket -> rsp_mux_001:sink16_endofpacket
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wire rsp_demux_018_src0_valid; // rsp_demux_018:src0_valid -> rsp_mux:sink18_valid
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wire [113:0] rsp_demux_018_src0_data; // rsp_demux_018:src0_data -> rsp_mux:sink18_data
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wire rsp_demux_018_src0_ready; // rsp_mux:sink18_ready -> rsp_demux_018:src0_ready
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wire [33:0] rsp_demux_018_src0_channel; // rsp_demux_018:src0_channel -> rsp_mux:sink18_channel
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wire rsp_demux_018_src0_startofpacket; // rsp_demux_018:src0_startofpacket -> rsp_mux:sink18_startofpacket
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wire rsp_demux_018_src0_endofpacket; // rsp_demux_018:src0_endofpacket -> rsp_mux:sink18_endofpacket
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wire rsp_demux_018_src1_valid; // rsp_demux_018:src1_valid -> rsp_mux_001:sink17_valid
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wire [113:0] rsp_demux_018_src1_data; // rsp_demux_018:src1_data -> rsp_mux_001:sink17_data
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wire rsp_demux_018_src1_ready; // rsp_mux_001:sink17_ready -> rsp_demux_018:src1_ready
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wire [33:0] rsp_demux_018_src1_channel; // rsp_demux_018:src1_channel -> rsp_mux_001:sink17_channel
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wire rsp_demux_018_src1_startofpacket; // rsp_demux_018:src1_startofpacket -> rsp_mux_001:sink17_startofpacket
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wire rsp_demux_018_src1_endofpacket; // rsp_demux_018:src1_endofpacket -> rsp_mux_001:sink17_endofpacket
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wire rsp_demux_019_src0_valid; // rsp_demux_019:src0_valid -> rsp_mux:sink19_valid
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wire [113:0] rsp_demux_019_src0_data; // rsp_demux_019:src0_data -> rsp_mux:sink19_data
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wire rsp_demux_019_src0_ready; // rsp_mux:sink19_ready -> rsp_demux_019:src0_ready
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wire [33:0] rsp_demux_019_src0_channel; // rsp_demux_019:src0_channel -> rsp_mux:sink19_channel
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wire rsp_demux_019_src0_startofpacket; // rsp_demux_019:src0_startofpacket -> rsp_mux:sink19_startofpacket
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wire rsp_demux_019_src0_endofpacket; // rsp_demux_019:src0_endofpacket -> rsp_mux:sink19_endofpacket
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wire rsp_demux_019_src1_valid; // rsp_demux_019:src1_valid -> rsp_mux_001:sink18_valid
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wire [113:0] rsp_demux_019_src1_data; // rsp_demux_019:src1_data -> rsp_mux_001:sink18_data
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wire rsp_demux_019_src1_ready; // rsp_mux_001:sink18_ready -> rsp_demux_019:src1_ready
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wire [33:0] rsp_demux_019_src1_channel; // rsp_demux_019:src1_channel -> rsp_mux_001:sink18_channel
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wire rsp_demux_019_src1_startofpacket; // rsp_demux_019:src1_startofpacket -> rsp_mux_001:sink18_startofpacket
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wire rsp_demux_019_src1_endofpacket; // rsp_demux_019:src1_endofpacket -> rsp_mux_001:sink18_endofpacket
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wire rsp_demux_019_src2_valid; // rsp_demux_019:src2_valid -> rsp_mux_002:sink15_valid
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wire [113:0] rsp_demux_019_src2_data; // rsp_demux_019:src2_data -> rsp_mux_002:sink15_data
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wire rsp_demux_019_src2_ready; // rsp_mux_002:sink15_ready -> rsp_demux_019:src2_ready
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wire [33:0] rsp_demux_019_src2_channel; // rsp_demux_019:src2_channel -> rsp_mux_002:sink15_channel
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wire rsp_demux_019_src2_startofpacket; // rsp_demux_019:src2_startofpacket -> rsp_mux_002:sink15_startofpacket
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wire rsp_demux_019_src2_endofpacket; // rsp_demux_019:src2_endofpacket -> rsp_mux_002:sink15_endofpacket
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wire rsp_demux_020_src0_valid; // rsp_demux_020:src0_valid -> rsp_mux:sink20_valid
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wire [113:0] rsp_demux_020_src0_data; // rsp_demux_020:src0_data -> rsp_mux:sink20_data
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wire rsp_demux_020_src0_ready; // rsp_mux:sink20_ready -> rsp_demux_020:src0_ready
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wire [33:0] rsp_demux_020_src0_channel; // rsp_demux_020:src0_channel -> rsp_mux:sink20_channel
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wire rsp_demux_020_src0_startofpacket; // rsp_demux_020:src0_startofpacket -> rsp_mux:sink20_startofpacket
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wire rsp_demux_020_src0_endofpacket; // rsp_demux_020:src0_endofpacket -> rsp_mux:sink20_endofpacket
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wire rsp_demux_020_src1_valid; // rsp_demux_020:src1_valid -> rsp_mux_001:sink19_valid
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wire [113:0] rsp_demux_020_src1_data; // rsp_demux_020:src1_data -> rsp_mux_001:sink19_data
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wire rsp_demux_020_src1_ready; // rsp_mux_001:sink19_ready -> rsp_demux_020:src1_ready
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wire [33:0] rsp_demux_020_src1_channel; // rsp_demux_020:src1_channel -> rsp_mux_001:sink19_channel
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wire rsp_demux_020_src1_startofpacket; // rsp_demux_020:src1_startofpacket -> rsp_mux_001:sink19_startofpacket
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wire rsp_demux_020_src1_endofpacket; // rsp_demux_020:src1_endofpacket -> rsp_mux_001:sink19_endofpacket
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wire rsp_demux_020_src2_valid; // rsp_demux_020:src2_valid -> rsp_mux_002:sink16_valid
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wire [113:0] rsp_demux_020_src2_data; // rsp_demux_020:src2_data -> rsp_mux_002:sink16_data
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wire rsp_demux_020_src2_ready; // rsp_mux_002:sink16_ready -> rsp_demux_020:src2_ready
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wire [33:0] rsp_demux_020_src2_channel; // rsp_demux_020:src2_channel -> rsp_mux_002:sink16_channel
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wire rsp_demux_020_src2_startofpacket; // rsp_demux_020:src2_startofpacket -> rsp_mux_002:sink16_startofpacket
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wire rsp_demux_020_src2_endofpacket; // rsp_demux_020:src2_endofpacket -> rsp_mux_002:sink16_endofpacket
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wire rsp_demux_021_src0_valid; // rsp_demux_021:src0_valid -> rsp_mux:sink21_valid
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wire [113:0] rsp_demux_021_src0_data; // rsp_demux_021:src0_data -> rsp_mux:sink21_data
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wire rsp_demux_021_src0_ready; // rsp_mux:sink21_ready -> rsp_demux_021:src0_ready
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wire [33:0] rsp_demux_021_src0_channel; // rsp_demux_021:src0_channel -> rsp_mux:sink21_channel
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wire rsp_demux_021_src0_startofpacket; // rsp_demux_021:src0_startofpacket -> rsp_mux:sink21_startofpacket
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wire rsp_demux_021_src0_endofpacket; // rsp_demux_021:src0_endofpacket -> rsp_mux:sink21_endofpacket
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wire rsp_demux_021_src1_valid; // rsp_demux_021:src1_valid -> rsp_mux_001:sink20_valid
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wire [113:0] rsp_demux_021_src1_data; // rsp_demux_021:src1_data -> rsp_mux_001:sink20_data
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wire rsp_demux_021_src1_ready; // rsp_mux_001:sink20_ready -> rsp_demux_021:src1_ready
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wire [33:0] rsp_demux_021_src1_channel; // rsp_demux_021:src1_channel -> rsp_mux_001:sink20_channel
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wire rsp_demux_021_src1_startofpacket; // rsp_demux_021:src1_startofpacket -> rsp_mux_001:sink20_startofpacket
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wire rsp_demux_021_src1_endofpacket; // rsp_demux_021:src1_endofpacket -> rsp_mux_001:sink20_endofpacket
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wire rsp_demux_021_src2_valid; // rsp_demux_021:src2_valid -> rsp_mux_002:sink17_valid
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wire [113:0] rsp_demux_021_src2_data; // rsp_demux_021:src2_data -> rsp_mux_002:sink17_data
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wire rsp_demux_021_src2_ready; // rsp_mux_002:sink17_ready -> rsp_demux_021:src2_ready
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wire [33:0] rsp_demux_021_src2_channel; // rsp_demux_021:src2_channel -> rsp_mux_002:sink17_channel
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wire rsp_demux_021_src2_startofpacket; // rsp_demux_021:src2_startofpacket -> rsp_mux_002:sink17_startofpacket
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wire rsp_demux_021_src2_endofpacket; // rsp_demux_021:src2_endofpacket -> rsp_mux_002:sink17_endofpacket
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wire rsp_demux_022_src0_valid; // rsp_demux_022:src0_valid -> rsp_mux:sink22_valid
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wire [113:0] rsp_demux_022_src0_data; // rsp_demux_022:src0_data -> rsp_mux:sink22_data
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wire rsp_demux_022_src0_ready; // rsp_mux:sink22_ready -> rsp_demux_022:src0_ready
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wire [33:0] rsp_demux_022_src0_channel; // rsp_demux_022:src0_channel -> rsp_mux:sink22_channel
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wire rsp_demux_022_src0_startofpacket; // rsp_demux_022:src0_startofpacket -> rsp_mux:sink22_startofpacket
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wire rsp_demux_022_src0_endofpacket; // rsp_demux_022:src0_endofpacket -> rsp_mux:sink22_endofpacket
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wire rsp_demux_022_src1_valid; // rsp_demux_022:src1_valid -> rsp_mux_001:sink21_valid
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wire [113:0] rsp_demux_022_src1_data; // rsp_demux_022:src1_data -> rsp_mux_001:sink21_data
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wire rsp_demux_022_src1_ready; // rsp_mux_001:sink21_ready -> rsp_demux_022:src1_ready
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wire [33:0] rsp_demux_022_src1_channel; // rsp_demux_022:src1_channel -> rsp_mux_001:sink21_channel
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wire rsp_demux_022_src1_startofpacket; // rsp_demux_022:src1_startofpacket -> rsp_mux_001:sink21_startofpacket
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wire rsp_demux_022_src1_endofpacket; // rsp_demux_022:src1_endofpacket -> rsp_mux_001:sink21_endofpacket
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wire rsp_demux_022_src2_valid; // rsp_demux_022:src2_valid -> rsp_mux_002:sink18_valid
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wire [113:0] rsp_demux_022_src2_data; // rsp_demux_022:src2_data -> rsp_mux_002:sink18_data
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wire rsp_demux_022_src2_ready; // rsp_mux_002:sink18_ready -> rsp_demux_022:src2_ready
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wire [33:0] rsp_demux_022_src2_channel; // rsp_demux_022:src2_channel -> rsp_mux_002:sink18_channel
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wire rsp_demux_022_src2_startofpacket; // rsp_demux_022:src2_startofpacket -> rsp_mux_002:sink18_startofpacket
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wire rsp_demux_022_src2_endofpacket; // rsp_demux_022:src2_endofpacket -> rsp_mux_002:sink18_endofpacket
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wire rsp_demux_023_src0_valid; // rsp_demux_023:src0_valid -> rsp_mux:sink23_valid
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wire [113:0] rsp_demux_023_src0_data; // rsp_demux_023:src0_data -> rsp_mux:sink23_data
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wire rsp_demux_023_src0_ready; // rsp_mux:sink23_ready -> rsp_demux_023:src0_ready
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wire [33:0] rsp_demux_023_src0_channel; // rsp_demux_023:src0_channel -> rsp_mux:sink23_channel
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wire rsp_demux_023_src0_startofpacket; // rsp_demux_023:src0_startofpacket -> rsp_mux:sink23_startofpacket
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wire rsp_demux_023_src0_endofpacket; // rsp_demux_023:src0_endofpacket -> rsp_mux:sink23_endofpacket
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wire rsp_demux_023_src1_valid; // rsp_demux_023:src1_valid -> rsp_mux_001:sink22_valid
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wire [113:0] rsp_demux_023_src1_data; // rsp_demux_023:src1_data -> rsp_mux_001:sink22_data
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wire rsp_demux_023_src1_ready; // rsp_mux_001:sink22_ready -> rsp_demux_023:src1_ready
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wire [33:0] rsp_demux_023_src1_channel; // rsp_demux_023:src1_channel -> rsp_mux_001:sink22_channel
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wire rsp_demux_023_src1_startofpacket; // rsp_demux_023:src1_startofpacket -> rsp_mux_001:sink22_startofpacket
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wire rsp_demux_023_src1_endofpacket; // rsp_demux_023:src1_endofpacket -> rsp_mux_001:sink22_endofpacket
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wire rsp_demux_023_src2_valid; // rsp_demux_023:src2_valid -> rsp_mux_002:sink19_valid
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wire [113:0] rsp_demux_023_src2_data; // rsp_demux_023:src2_data -> rsp_mux_002:sink19_data
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wire rsp_demux_023_src2_ready; // rsp_mux_002:sink19_ready -> rsp_demux_023:src2_ready
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wire [33:0] rsp_demux_023_src2_channel; // rsp_demux_023:src2_channel -> rsp_mux_002:sink19_channel
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wire rsp_demux_023_src2_startofpacket; // rsp_demux_023:src2_startofpacket -> rsp_mux_002:sink19_startofpacket
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wire rsp_demux_023_src2_endofpacket; // rsp_demux_023:src2_endofpacket -> rsp_mux_002:sink19_endofpacket
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wire rsp_demux_024_src0_valid; // rsp_demux_024:src0_valid -> rsp_mux:sink24_valid
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wire [113:0] rsp_demux_024_src0_data; // rsp_demux_024:src0_data -> rsp_mux:sink24_data
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wire rsp_demux_024_src0_ready; // rsp_mux:sink24_ready -> rsp_demux_024:src0_ready
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wire [33:0] rsp_demux_024_src0_channel; // rsp_demux_024:src0_channel -> rsp_mux:sink24_channel
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wire rsp_demux_024_src0_startofpacket; // rsp_demux_024:src0_startofpacket -> rsp_mux:sink24_startofpacket
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wire rsp_demux_024_src0_endofpacket; // rsp_demux_024:src0_endofpacket -> rsp_mux:sink24_endofpacket
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wire rsp_demux_024_src1_valid; // rsp_demux_024:src1_valid -> rsp_mux_001:sink23_valid
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wire [113:0] rsp_demux_024_src1_data; // rsp_demux_024:src1_data -> rsp_mux_001:sink23_data
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wire rsp_demux_024_src1_ready; // rsp_mux_001:sink23_ready -> rsp_demux_024:src1_ready
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wire [33:0] rsp_demux_024_src1_channel; // rsp_demux_024:src1_channel -> rsp_mux_001:sink23_channel
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wire rsp_demux_024_src1_startofpacket; // rsp_demux_024:src1_startofpacket -> rsp_mux_001:sink23_startofpacket
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wire rsp_demux_024_src1_endofpacket; // rsp_demux_024:src1_endofpacket -> rsp_mux_001:sink23_endofpacket
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wire rsp_demux_024_src2_valid; // rsp_demux_024:src2_valid -> rsp_mux_002:sink20_valid
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wire [113:0] rsp_demux_024_src2_data; // rsp_demux_024:src2_data -> rsp_mux_002:sink20_data
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wire rsp_demux_024_src2_ready; // rsp_mux_002:sink20_ready -> rsp_demux_024:src2_ready
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wire [33:0] rsp_demux_024_src2_channel; // rsp_demux_024:src2_channel -> rsp_mux_002:sink20_channel
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wire rsp_demux_024_src2_startofpacket; // rsp_demux_024:src2_startofpacket -> rsp_mux_002:sink20_startofpacket
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wire rsp_demux_024_src2_endofpacket; // rsp_demux_024:src2_endofpacket -> rsp_mux_002:sink20_endofpacket
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wire rsp_demux_025_src0_valid; // rsp_demux_025:src0_valid -> rsp_mux:sink25_valid
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wire [113:0] rsp_demux_025_src0_data; // rsp_demux_025:src0_data -> rsp_mux:sink25_data
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wire rsp_demux_025_src0_ready; // rsp_mux:sink25_ready -> rsp_demux_025:src0_ready
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wire [33:0] rsp_demux_025_src0_channel; // rsp_demux_025:src0_channel -> rsp_mux:sink25_channel
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wire rsp_demux_025_src0_startofpacket; // rsp_demux_025:src0_startofpacket -> rsp_mux:sink25_startofpacket
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wire rsp_demux_025_src0_endofpacket; // rsp_demux_025:src0_endofpacket -> rsp_mux:sink25_endofpacket
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wire rsp_demux_025_src1_valid; // rsp_demux_025:src1_valid -> rsp_mux_001:sink24_valid
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wire [113:0] rsp_demux_025_src1_data; // rsp_demux_025:src1_data -> rsp_mux_001:sink24_data
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wire rsp_demux_025_src1_ready; // rsp_mux_001:sink24_ready -> rsp_demux_025:src1_ready
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wire [33:0] rsp_demux_025_src1_channel; // rsp_demux_025:src1_channel -> rsp_mux_001:sink24_channel
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wire rsp_demux_025_src1_startofpacket; // rsp_demux_025:src1_startofpacket -> rsp_mux_001:sink24_startofpacket
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wire rsp_demux_025_src1_endofpacket; // rsp_demux_025:src1_endofpacket -> rsp_mux_001:sink24_endofpacket
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wire rsp_demux_026_src0_valid; // rsp_demux_026:src0_valid -> rsp_mux:sink26_valid
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wire [113:0] rsp_demux_026_src0_data; // rsp_demux_026:src0_data -> rsp_mux:sink26_data
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wire rsp_demux_026_src0_ready; // rsp_mux:sink26_ready -> rsp_demux_026:src0_ready
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wire [33:0] rsp_demux_026_src0_channel; // rsp_demux_026:src0_channel -> rsp_mux:sink26_channel
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wire rsp_demux_026_src0_startofpacket; // rsp_demux_026:src0_startofpacket -> rsp_mux:sink26_startofpacket
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wire rsp_demux_026_src0_endofpacket; // rsp_demux_026:src0_endofpacket -> rsp_mux:sink26_endofpacket
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wire rsp_demux_026_src1_valid; // rsp_demux_026:src1_valid -> rsp_mux_001:sink25_valid
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wire [113:0] rsp_demux_026_src1_data; // rsp_demux_026:src1_data -> rsp_mux_001:sink25_data
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wire rsp_demux_026_src1_ready; // rsp_mux_001:sink25_ready -> rsp_demux_026:src1_ready
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wire [33:0] rsp_demux_026_src1_channel; // rsp_demux_026:src1_channel -> rsp_mux_001:sink25_channel
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wire rsp_demux_026_src1_startofpacket; // rsp_demux_026:src1_startofpacket -> rsp_mux_001:sink25_startofpacket
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wire rsp_demux_026_src1_endofpacket; // rsp_demux_026:src1_endofpacket -> rsp_mux_001:sink25_endofpacket
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wire rsp_demux_026_src2_valid; // rsp_demux_026:src2_valid -> rsp_mux_002:sink21_valid
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wire [113:0] rsp_demux_026_src2_data; // rsp_demux_026:src2_data -> rsp_mux_002:sink21_data
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wire rsp_demux_026_src2_ready; // rsp_mux_002:sink21_ready -> rsp_demux_026:src2_ready
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wire [33:0] rsp_demux_026_src2_channel; // rsp_demux_026:src2_channel -> rsp_mux_002:sink21_channel
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wire rsp_demux_026_src2_startofpacket; // rsp_demux_026:src2_startofpacket -> rsp_mux_002:sink21_startofpacket
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wire rsp_demux_026_src2_endofpacket; // rsp_demux_026:src2_endofpacket -> rsp_mux_002:sink21_endofpacket
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wire rsp_demux_027_src0_valid; // rsp_demux_027:src0_valid -> rsp_mux:sink27_valid
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wire [113:0] rsp_demux_027_src0_data; // rsp_demux_027:src0_data -> rsp_mux:sink27_data
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wire rsp_demux_027_src0_ready; // rsp_mux:sink27_ready -> rsp_demux_027:src0_ready
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wire [33:0] rsp_demux_027_src0_channel; // rsp_demux_027:src0_channel -> rsp_mux:sink27_channel
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wire rsp_demux_027_src0_startofpacket; // rsp_demux_027:src0_startofpacket -> rsp_mux:sink27_startofpacket
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wire rsp_demux_027_src0_endofpacket; // rsp_demux_027:src0_endofpacket -> rsp_mux:sink27_endofpacket
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wire rsp_demux_027_src1_valid; // rsp_demux_027:src1_valid -> rsp_mux_001:sink26_valid
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wire [113:0] rsp_demux_027_src1_data; // rsp_demux_027:src1_data -> rsp_mux_001:sink26_data
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wire rsp_demux_027_src1_ready; // rsp_mux_001:sink26_ready -> rsp_demux_027:src1_ready
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wire [33:0] rsp_demux_027_src1_channel; // rsp_demux_027:src1_channel -> rsp_mux_001:sink26_channel
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wire rsp_demux_027_src1_startofpacket; // rsp_demux_027:src1_startofpacket -> rsp_mux_001:sink26_startofpacket
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wire rsp_demux_027_src1_endofpacket; // rsp_demux_027:src1_endofpacket -> rsp_mux_001:sink26_endofpacket
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wire rsp_demux_027_src2_valid; // rsp_demux_027:src2_valid -> rsp_mux_002:sink22_valid
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wire [113:0] rsp_demux_027_src2_data; // rsp_demux_027:src2_data -> rsp_mux_002:sink22_data
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wire rsp_demux_027_src2_ready; // rsp_mux_002:sink22_ready -> rsp_demux_027:src2_ready
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wire [33:0] rsp_demux_027_src2_channel; // rsp_demux_027:src2_channel -> rsp_mux_002:sink22_channel
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wire rsp_demux_027_src2_startofpacket; // rsp_demux_027:src2_startofpacket -> rsp_mux_002:sink22_startofpacket
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wire rsp_demux_027_src2_endofpacket; // rsp_demux_027:src2_endofpacket -> rsp_mux_002:sink22_endofpacket
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wire rsp_demux_028_src0_valid; // rsp_demux_028:src0_valid -> rsp_mux:sink28_valid
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wire [113:0] rsp_demux_028_src0_data; // rsp_demux_028:src0_data -> rsp_mux:sink28_data
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wire rsp_demux_028_src0_ready; // rsp_mux:sink28_ready -> rsp_demux_028:src0_ready
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wire [33:0] rsp_demux_028_src0_channel; // rsp_demux_028:src0_channel -> rsp_mux:sink28_channel
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wire rsp_demux_028_src0_startofpacket; // rsp_demux_028:src0_startofpacket -> rsp_mux:sink28_startofpacket
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wire rsp_demux_028_src0_endofpacket; // rsp_demux_028:src0_endofpacket -> rsp_mux:sink28_endofpacket
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wire rsp_demux_028_src1_valid; // rsp_demux_028:src1_valid -> rsp_mux_001:sink27_valid
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wire [113:0] rsp_demux_028_src1_data; // rsp_demux_028:src1_data -> rsp_mux_001:sink27_data
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wire rsp_demux_028_src1_ready; // rsp_mux_001:sink27_ready -> rsp_demux_028:src1_ready
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wire [33:0] rsp_demux_028_src1_channel; // rsp_demux_028:src1_channel -> rsp_mux_001:sink27_channel
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wire rsp_demux_028_src1_startofpacket; // rsp_demux_028:src1_startofpacket -> rsp_mux_001:sink27_startofpacket
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wire rsp_demux_028_src1_endofpacket; // rsp_demux_028:src1_endofpacket -> rsp_mux_001:sink27_endofpacket
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wire rsp_demux_028_src2_valid; // rsp_demux_028:src2_valid -> rsp_mux_002:sink23_valid
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wire [113:0] rsp_demux_028_src2_data; // rsp_demux_028:src2_data -> rsp_mux_002:sink23_data
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wire rsp_demux_028_src2_ready; // rsp_mux_002:sink23_ready -> rsp_demux_028:src2_ready
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wire [33:0] rsp_demux_028_src2_channel; // rsp_demux_028:src2_channel -> rsp_mux_002:sink23_channel
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wire rsp_demux_028_src2_startofpacket; // rsp_demux_028:src2_startofpacket -> rsp_mux_002:sink23_startofpacket
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wire rsp_demux_028_src2_endofpacket; // rsp_demux_028:src2_endofpacket -> rsp_mux_002:sink23_endofpacket
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wire rsp_demux_029_src0_valid; // rsp_demux_029:src0_valid -> rsp_mux:sink29_valid
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wire [113:0] rsp_demux_029_src0_data; // rsp_demux_029:src0_data -> rsp_mux:sink29_data
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wire rsp_demux_029_src0_ready; // rsp_mux:sink29_ready -> rsp_demux_029:src0_ready
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wire [33:0] rsp_demux_029_src0_channel; // rsp_demux_029:src0_channel -> rsp_mux:sink29_channel
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wire rsp_demux_029_src0_startofpacket; // rsp_demux_029:src0_startofpacket -> rsp_mux:sink29_startofpacket
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wire rsp_demux_029_src0_endofpacket; // rsp_demux_029:src0_endofpacket -> rsp_mux:sink29_endofpacket
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wire rsp_demux_029_src1_valid; // rsp_demux_029:src1_valid -> rsp_mux_001:sink28_valid
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wire [113:0] rsp_demux_029_src1_data; // rsp_demux_029:src1_data -> rsp_mux_001:sink28_data
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wire rsp_demux_029_src1_ready; // rsp_mux_001:sink28_ready -> rsp_demux_029:src1_ready
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wire [33:0] rsp_demux_029_src1_channel; // rsp_demux_029:src1_channel -> rsp_mux_001:sink28_channel
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wire rsp_demux_029_src1_startofpacket; // rsp_demux_029:src1_startofpacket -> rsp_mux_001:sink28_startofpacket
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wire rsp_demux_029_src1_endofpacket; // rsp_demux_029:src1_endofpacket -> rsp_mux_001:sink28_endofpacket
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wire rsp_demux_029_src2_valid; // rsp_demux_029:src2_valid -> rsp_mux_002:sink24_valid
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wire [113:0] rsp_demux_029_src2_data; // rsp_demux_029:src2_data -> rsp_mux_002:sink24_data
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wire rsp_demux_029_src2_ready; // rsp_mux_002:sink24_ready -> rsp_demux_029:src2_ready
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wire [33:0] rsp_demux_029_src2_channel; // rsp_demux_029:src2_channel -> rsp_mux_002:sink24_channel
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wire rsp_demux_029_src2_startofpacket; // rsp_demux_029:src2_startofpacket -> rsp_mux_002:sink24_startofpacket
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wire rsp_demux_029_src2_endofpacket; // rsp_demux_029:src2_endofpacket -> rsp_mux_002:sink24_endofpacket
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wire rsp_demux_030_src0_valid; // rsp_demux_030:src0_valid -> rsp_mux:sink30_valid
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wire [113:0] rsp_demux_030_src0_data; // rsp_demux_030:src0_data -> rsp_mux:sink30_data
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wire rsp_demux_030_src0_ready; // rsp_mux:sink30_ready -> rsp_demux_030:src0_ready
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wire [33:0] rsp_demux_030_src0_channel; // rsp_demux_030:src0_channel -> rsp_mux:sink30_channel
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wire rsp_demux_030_src0_startofpacket; // rsp_demux_030:src0_startofpacket -> rsp_mux:sink30_startofpacket
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wire rsp_demux_030_src0_endofpacket; // rsp_demux_030:src0_endofpacket -> rsp_mux:sink30_endofpacket
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wire rsp_demux_030_src1_valid; // rsp_demux_030:src1_valid -> rsp_mux_001:sink29_valid
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wire [113:0] rsp_demux_030_src1_data; // rsp_demux_030:src1_data -> rsp_mux_001:sink29_data
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wire rsp_demux_030_src1_ready; // rsp_mux_001:sink29_ready -> rsp_demux_030:src1_ready
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wire [33:0] rsp_demux_030_src1_channel; // rsp_demux_030:src1_channel -> rsp_mux_001:sink29_channel
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wire rsp_demux_030_src1_startofpacket; // rsp_demux_030:src1_startofpacket -> rsp_mux_001:sink29_startofpacket
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wire rsp_demux_030_src1_endofpacket; // rsp_demux_030:src1_endofpacket -> rsp_mux_001:sink29_endofpacket
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wire rsp_demux_030_src2_valid; // rsp_demux_030:src2_valid -> rsp_mux_002:sink25_valid
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wire [113:0] rsp_demux_030_src2_data; // rsp_demux_030:src2_data -> rsp_mux_002:sink25_data
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wire rsp_demux_030_src2_ready; // rsp_mux_002:sink25_ready -> rsp_demux_030:src2_ready
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wire [33:0] rsp_demux_030_src2_channel; // rsp_demux_030:src2_channel -> rsp_mux_002:sink25_channel
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wire rsp_demux_030_src2_startofpacket; // rsp_demux_030:src2_startofpacket -> rsp_mux_002:sink25_startofpacket
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wire rsp_demux_030_src2_endofpacket; // rsp_demux_030:src2_endofpacket -> rsp_mux_002:sink25_endofpacket
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wire rsp_demux_031_src0_valid; // rsp_demux_031:src0_valid -> rsp_mux:sink31_valid
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wire [113:0] rsp_demux_031_src0_data; // rsp_demux_031:src0_data -> rsp_mux:sink31_data
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wire rsp_demux_031_src0_ready; // rsp_mux:sink31_ready -> rsp_demux_031:src0_ready
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wire [33:0] rsp_demux_031_src0_channel; // rsp_demux_031:src0_channel -> rsp_mux:sink31_channel
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wire rsp_demux_031_src0_startofpacket; // rsp_demux_031:src0_startofpacket -> rsp_mux:sink31_startofpacket
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wire rsp_demux_031_src0_endofpacket; // rsp_demux_031:src0_endofpacket -> rsp_mux:sink31_endofpacket
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wire rsp_demux_032_src0_valid; // rsp_demux_032:src0_valid -> rsp_mux:sink32_valid
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wire [113:0] rsp_demux_032_src0_data; // rsp_demux_032:src0_data -> rsp_mux:sink32_data
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wire rsp_demux_032_src0_ready; // rsp_mux:sink32_ready -> rsp_demux_032:src0_ready
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wire [33:0] rsp_demux_032_src0_channel; // rsp_demux_032:src0_channel -> rsp_mux:sink32_channel
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wire rsp_demux_032_src0_startofpacket; // rsp_demux_032:src0_startofpacket -> rsp_mux:sink32_startofpacket
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wire rsp_demux_032_src0_endofpacket; // rsp_demux_032:src0_endofpacket -> rsp_mux:sink32_endofpacket
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wire rsp_demux_033_src0_valid; // rsp_demux_033:src0_valid -> rsp_mux:sink33_valid
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wire [113:0] rsp_demux_033_src0_data; // rsp_demux_033:src0_data -> rsp_mux:sink33_data
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wire rsp_demux_033_src0_ready; // rsp_mux:sink33_ready -> rsp_demux_033:src0_ready
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wire [33:0] rsp_demux_033_src0_channel; // rsp_demux_033:src0_channel -> rsp_mux:sink33_channel
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wire rsp_demux_033_src0_startofpacket; // rsp_demux_033:src0_startofpacket -> rsp_mux:sink33_startofpacket
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wire rsp_demux_033_src0_endofpacket; // rsp_demux_033:src0_endofpacket -> rsp_mux:sink33_endofpacket
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wire rsp_demux_033_src1_valid; // rsp_demux_033:src1_valid -> rsp_mux_001:sink30_valid
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wire [113:0] rsp_demux_033_src1_data; // rsp_demux_033:src1_data -> rsp_mux_001:sink30_data
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wire rsp_demux_033_src1_ready; // rsp_mux_001:sink30_ready -> rsp_demux_033:src1_ready
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wire [33:0] rsp_demux_033_src1_channel; // rsp_demux_033:src1_channel -> rsp_mux_001:sink30_channel
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wire rsp_demux_033_src1_startofpacket; // rsp_demux_033:src1_startofpacket -> rsp_mux_001:sink30_startofpacket
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wire rsp_demux_033_src1_endofpacket; // rsp_demux_033:src1_endofpacket -> rsp_mux_001:sink30_endofpacket
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wire rsp_demux_033_src2_valid; // rsp_demux_033:src2_valid -> rsp_mux_002:sink26_valid
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wire [113:0] rsp_demux_033_src2_data; // rsp_demux_033:src2_data -> rsp_mux_002:sink26_data
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wire rsp_demux_033_src2_ready; // rsp_mux_002:sink26_ready -> rsp_demux_033:src2_ready
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wire [33:0] rsp_demux_033_src2_channel; // rsp_demux_033:src2_channel -> rsp_mux_002:sink26_channel
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wire rsp_demux_033_src2_startofpacket; // rsp_demux_033:src2_startofpacket -> rsp_mux_002:sink26_startofpacket
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wire rsp_demux_033_src2_endofpacket; // rsp_demux_033:src2_endofpacket -> rsp_mux_002:sink26_endofpacket
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wire router_007_src_valid; // router_007:src_valid -> sram_multiplexer_avl_rsp_width_adapter:in_valid
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wire [95:0] router_007_src_data; // router_007:src_data -> sram_multiplexer_avl_rsp_width_adapter:in_data
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wire router_007_src_ready; // sram_multiplexer_avl_rsp_width_adapter:in_ready -> router_007:src_ready
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wire [33:0] router_007_src_channel; // router_007:src_channel -> sram_multiplexer_avl_rsp_width_adapter:in_channel
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wire router_007_src_startofpacket; // router_007:src_startofpacket -> sram_multiplexer_avl_rsp_width_adapter:in_startofpacket
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wire router_007_src_endofpacket; // router_007:src_endofpacket -> sram_multiplexer_avl_rsp_width_adapter:in_endofpacket
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wire sram_multiplexer_avl_rsp_width_adapter_src_valid; // sram_multiplexer_avl_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
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wire [113:0] sram_multiplexer_avl_rsp_width_adapter_src_data; // sram_multiplexer_avl_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
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wire sram_multiplexer_avl_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> sram_multiplexer_avl_rsp_width_adapter:out_ready
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wire [33:0] sram_multiplexer_avl_rsp_width_adapter_src_channel; // sram_multiplexer_avl_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
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wire sram_multiplexer_avl_rsp_width_adapter_src_startofpacket; // sram_multiplexer_avl_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
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wire sram_multiplexer_avl_rsp_width_adapter_src_endofpacket; // sram_multiplexer_avl_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
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wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sram_multiplexer_avl_cmd_width_adapter:in_valid
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wire [113:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sram_multiplexer_avl_cmd_width_adapter:in_data
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wire cmd_mux_003_src_ready; // sram_multiplexer_avl_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
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wire [33:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sram_multiplexer_avl_cmd_width_adapter:in_channel
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wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sram_multiplexer_avl_cmd_width_adapter:in_startofpacket
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wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sram_multiplexer_avl_cmd_width_adapter:in_endofpacket
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wire sram_multiplexer_avl_cmd_width_adapter_src_valid; // sram_multiplexer_avl_cmd_width_adapter:out_valid -> sram_multiplexer_avl_burst_adapter:sink0_valid
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wire [95:0] sram_multiplexer_avl_cmd_width_adapter_src_data; // sram_multiplexer_avl_cmd_width_adapter:out_data -> sram_multiplexer_avl_burst_adapter:sink0_data
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wire sram_multiplexer_avl_cmd_width_adapter_src_ready; // sram_multiplexer_avl_burst_adapter:sink0_ready -> sram_multiplexer_avl_cmd_width_adapter:out_ready
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wire [33:0] sram_multiplexer_avl_cmd_width_adapter_src_channel; // sram_multiplexer_avl_cmd_width_adapter:out_channel -> sram_multiplexer_avl_burst_adapter:sink0_channel
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wire sram_multiplexer_avl_cmd_width_adapter_src_startofpacket; // sram_multiplexer_avl_cmd_width_adapter:out_startofpacket -> sram_multiplexer_avl_burst_adapter:sink0_startofpacket
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wire sram_multiplexer_avl_cmd_width_adapter_src_endofpacket; // sram_multiplexer_avl_cmd_width_adapter:out_endofpacket -> sram_multiplexer_avl_burst_adapter:sink0_endofpacket
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wire [33:0] nios2_dma_m_read_limiter_cmd_valid_data; // nios2_dma_m_read_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // nios2_jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
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wire [33:0] nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // nios2_jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
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wire nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> nios2_jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> nios2_jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> nios2_jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_out_0_ready; // nios2_jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
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wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> nios2_jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_error
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wire eth1_mdio_avalon_slave_agent_rdata_fifo_src_valid; // eth1_mdio_avalon_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
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wire [33:0] eth1_mdio_avalon_slave_agent_rdata_fifo_src_data; // eth1_mdio_avalon_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
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wire eth1_mdio_avalon_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> eth1_mdio_avalon_slave_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> eth1_mdio_avalon_slave_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> eth1_mdio_avalon_slave_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_001_out_0_ready; // eth1_mdio_avalon_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
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wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> eth1_mdio_avalon_slave_agent:rdata_fifo_sink_error
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wire eth0_mdio_avalon_slave_agent_rdata_fifo_src_valid; // eth0_mdio_avalon_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
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wire [33:0] eth0_mdio_avalon_slave_agent_rdata_fifo_src_data; // eth0_mdio_avalon_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
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wire eth0_mdio_avalon_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> eth0_mdio_avalon_slave_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> eth0_mdio_avalon_slave_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> eth0_mdio_avalon_slave_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_002_out_0_ready; // eth0_mdio_avalon_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
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wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> eth0_mdio_avalon_slave_agent:rdata_fifo_sink_error
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wire sram_multiplexer_avl_agent_rdata_fifo_src_valid; // sram_multiplexer_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
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wire [17:0] sram_multiplexer_avl_agent_rdata_fifo_src_data; // sram_multiplexer_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
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wire sram_multiplexer_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> sram_multiplexer_avl_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sram_multiplexer_avl_agent:rdata_fifo_sink_valid
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wire [17:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sram_multiplexer_avl_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_003_out_0_ready; // sram_multiplexer_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
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wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sram_multiplexer_avl_agent:rdata_fifo_sink_error
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wire vga_sprite_params_avl_agent_rdata_fifo_src_valid; // vga_sprite_params_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
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wire [33:0] vga_sprite_params_avl_agent_rdata_fifo_src_data; // vga_sprite_params_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
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wire vga_sprite_params_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> vga_sprite_params_avl_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> vga_sprite_params_avl_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> vga_sprite_params_avl_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_004_out_0_ready; // vga_sprite_params_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
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wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> vga_sprite_params_avl_agent:rdata_fifo_sink_error
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wire nios2_sysid_control_slave_agent_rdata_fifo_src_valid; // nios2_sysid_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
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wire [33:0] nios2_sysid_control_slave_agent_rdata_fifo_src_data; // nios2_sysid_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
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wire nios2_sysid_control_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> nios2_sysid_control_slave_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> nios2_sysid_control_slave_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> nios2_sysid_control_slave_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_005_out_0_ready; // nios2_sysid_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
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wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> nios2_sysid_control_slave_agent:rdata_fifo_sink_error
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wire eth0_rx_dma_csr_agent_rdata_fifo_src_valid; // eth0_rx_dma_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
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wire [33:0] eth0_rx_dma_csr_agent_rdata_fifo_src_data; // eth0_rx_dma_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
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wire eth0_rx_dma_csr_agent_rdata_fifo_src_ready; // avalon_st_adapter_006:in_0_ready -> eth0_rx_dma_csr_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> eth0_rx_dma_csr_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> eth0_rx_dma_csr_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_006_out_0_ready; // eth0_rx_dma_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
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wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> eth0_rx_dma_csr_agent:rdata_fifo_sink_error
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wire eth0_tx_dma_csr_agent_rdata_fifo_src_valid; // eth0_tx_dma_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
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wire [33:0] eth0_tx_dma_csr_agent_rdata_fifo_src_data; // eth0_tx_dma_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
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wire eth0_tx_dma_csr_agent_rdata_fifo_src_ready; // avalon_st_adapter_007:in_0_ready -> eth0_tx_dma_csr_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> eth0_tx_dma_csr_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> eth0_tx_dma_csr_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_007_out_0_ready; // eth0_tx_dma_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
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wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> eth0_tx_dma_csr_agent:rdata_fifo_sink_error
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wire eth1_rx_dma_csr_agent_rdata_fifo_src_valid; // eth1_rx_dma_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
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wire [33:0] eth1_rx_dma_csr_agent_rdata_fifo_src_data; // eth1_rx_dma_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
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wire eth1_rx_dma_csr_agent_rdata_fifo_src_ready; // avalon_st_adapter_008:in_0_ready -> eth1_rx_dma_csr_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_008_out_0_valid; // avalon_st_adapter_008:out_0_valid -> eth1_rx_dma_csr_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_008_out_0_data; // avalon_st_adapter_008:out_0_data -> eth1_rx_dma_csr_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_008_out_0_ready; // eth1_rx_dma_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
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wire [0:0] avalon_st_adapter_008_out_0_error; // avalon_st_adapter_008:out_0_error -> eth1_rx_dma_csr_agent:rdata_fifo_sink_error
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wire eth1_tx_dma_csr_agent_rdata_fifo_src_valid; // eth1_tx_dma_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
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wire [33:0] eth1_tx_dma_csr_agent_rdata_fifo_src_data; // eth1_tx_dma_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
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wire eth1_tx_dma_csr_agent_rdata_fifo_src_ready; // avalon_st_adapter_009:in_0_ready -> eth1_tx_dma_csr_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_009_out_0_valid; // avalon_st_adapter_009:out_0_valid -> eth1_tx_dma_csr_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_009_out_0_data; // avalon_st_adapter_009:out_0_data -> eth1_tx_dma_csr_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_009_out_0_ready; // eth1_tx_dma_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
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wire [0:0] avalon_st_adapter_009_out_0_error; // avalon_st_adapter_009:out_0_error -> eth1_tx_dma_csr_agent:rdata_fifo_sink_error
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wire nios2_dma_csr_agent_rdata_fifo_src_valid; // nios2_dma_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_010:in_0_valid
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wire [33:0] nios2_dma_csr_agent_rdata_fifo_src_data; // nios2_dma_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_010:in_0_data
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wire nios2_dma_csr_agent_rdata_fifo_src_ready; // avalon_st_adapter_010:in_0_ready -> nios2_dma_csr_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_010_out_0_valid; // avalon_st_adapter_010:out_0_valid -> nios2_dma_csr_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_010_out_0_data; // avalon_st_adapter_010:out_0_data -> nios2_dma_csr_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_010_out_0_ready; // nios2_dma_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_010:out_0_ready
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wire [0:0] avalon_st_adapter_010_out_0_error; // avalon_st_adapter_010:out_0_error -> nios2_dma_csr_agent:rdata_fifo_sink_error
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wire nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_cpu_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_011:in_0_valid
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wire [33:0] nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_cpu_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_011:in_0_data
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wire nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_011:in_0_ready -> nios2_cpu_debug_mem_slave_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_011_out_0_valid; // avalon_st_adapter_011:out_0_valid -> nios2_cpu_debug_mem_slave_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_011_out_0_data; // avalon_st_adapter_011:out_0_data -> nios2_cpu_debug_mem_slave_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_011_out_0_ready; // nios2_cpu_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_011:out_0_ready
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wire [0:0] avalon_st_adapter_011_out_0_error; // avalon_st_adapter_011:out_0_error -> nios2_cpu_debug_mem_slave_agent:rdata_fifo_sink_error
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wire nios2_pll_pll_slave_agent_rdata_fifo_src_valid; // nios2_pll_pll_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_012:in_0_valid
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wire [33:0] nios2_pll_pll_slave_agent_rdata_fifo_src_data; // nios2_pll_pll_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_012:in_0_data
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wire nios2_pll_pll_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_012:in_0_ready -> nios2_pll_pll_slave_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_012_out_0_valid; // avalon_st_adapter_012:out_0_valid -> nios2_pll_pll_slave_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_012_out_0_data; // avalon_st_adapter_012:out_0_data -> nios2_pll_pll_slave_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_012_out_0_ready; // nios2_pll_pll_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_012:out_0_ready
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wire [0:0] avalon_st_adapter_012_out_0_error; // avalon_st_adapter_012:out_0_error -> nios2_pll_pll_slave_agent:rdata_fifo_sink_error
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wire nios2_onchip_mem_s1_agent_rdata_fifo_src_valid; // nios2_onchip_mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_013:in_0_valid
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wire [33:0] nios2_onchip_mem_s1_agent_rdata_fifo_src_data; // nios2_onchip_mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_013:in_0_data
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wire nios2_onchip_mem_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_013:in_0_ready -> nios2_onchip_mem_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_013_out_0_valid; // avalon_st_adapter_013:out_0_valid -> nios2_onchip_mem_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_013_out_0_data; // avalon_st_adapter_013:out_0_data -> nios2_onchip_mem_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_013_out_0_ready; // nios2_onchip_mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_013:out_0_ready
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wire [0:0] avalon_st_adapter_013_out_0_error; // avalon_st_adapter_013:out_0_error -> nios2_onchip_mem_s1_agent:rdata_fifo_sink_error
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wire sdram_s1_agent_rdata_fifo_src_valid; // sdram_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_014:in_0_valid
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wire [33:0] sdram_s1_agent_rdata_fifo_src_data; // sdram_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_014:in_0_data
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wire sdram_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_014:in_0_ready -> sdram_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_014_out_0_valid; // avalon_st_adapter_014:out_0_valid -> sdram_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_014_out_0_data; // avalon_st_adapter_014:out_0_data -> sdram_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_014_out_0_ready; // sdram_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_014:out_0_ready
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wire [0:0] avalon_st_adapter_014_out_0_error; // avalon_st_adapter_014:out_0_error -> sdram_s1_agent:rdata_fifo_sink_error
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wire io_led_red_s1_agent_rdata_fifo_src_valid; // io_led_red_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_015:in_0_valid
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wire [33:0] io_led_red_s1_agent_rdata_fifo_src_data; // io_led_red_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_015:in_0_data
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wire io_led_red_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_015:in_0_ready -> io_led_red_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_015_out_0_valid; // avalon_st_adapter_015:out_0_valid -> io_led_red_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_015_out_0_data; // avalon_st_adapter_015:out_0_data -> io_led_red_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_015_out_0_ready; // io_led_red_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_015:out_0_ready
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wire [0:0] avalon_st_adapter_015_out_0_error; // avalon_st_adapter_015:out_0_error -> io_led_red_s1_agent:rdata_fifo_sink_error
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wire nios2_timer_s1_agent_rdata_fifo_src_valid; // nios2_timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_016:in_0_valid
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wire [33:0] nios2_timer_s1_agent_rdata_fifo_src_data; // nios2_timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_016:in_0_data
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wire nios2_timer_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_016:in_0_ready -> nios2_timer_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_016_out_0_valid; // avalon_st_adapter_016:out_0_valid -> nios2_timer_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_016_out_0_data; // avalon_st_adapter_016:out_0_data -> nios2_timer_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_016_out_0_ready; // nios2_timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_016:out_0_ready
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wire [0:0] avalon_st_adapter_016_out_0_error; // avalon_st_adapter_016:out_0_error -> nios2_timer_s1_agent:rdata_fifo_sink_error
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wire io_keys_s1_agent_rdata_fifo_src_valid; // io_keys_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_017:in_0_valid
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wire [33:0] io_keys_s1_agent_rdata_fifo_src_data; // io_keys_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_017:in_0_data
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wire io_keys_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_017:in_0_ready -> io_keys_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_017_out_0_valid; // avalon_st_adapter_017:out_0_valid -> io_keys_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_017_out_0_data; // avalon_st_adapter_017:out_0_data -> io_keys_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_017_out_0_ready; // io_keys_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_017:out_0_ready
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wire [0:0] avalon_st_adapter_017_out_0_error; // avalon_st_adapter_017:out_0_error -> io_keys_s1_agent:rdata_fifo_sink_error
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wire io_switches_s1_agent_rdata_fifo_src_valid; // io_switches_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_018:in_0_valid
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wire [33:0] io_switches_s1_agent_rdata_fifo_src_data; // io_switches_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_018:in_0_data
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wire io_switches_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_018:in_0_ready -> io_switches_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_018_out_0_valid; // avalon_st_adapter_018:out_0_valid -> io_switches_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_018_out_0_data; // avalon_st_adapter_018:out_0_data -> io_switches_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_018_out_0_ready; // io_switches_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_018:out_0_ready
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wire [0:0] avalon_st_adapter_018_out_0_error; // avalon_st_adapter_018:out_0_error -> io_switches_s1_agent:rdata_fifo_sink_error
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wire io_led_green_s1_agent_rdata_fifo_src_valid; // io_led_green_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_019:in_0_valid
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wire [33:0] io_led_green_s1_agent_rdata_fifo_src_data; // io_led_green_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_019:in_0_data
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wire io_led_green_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_019:in_0_ready -> io_led_green_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_019_out_0_valid; // avalon_st_adapter_019:out_0_valid -> io_led_green_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_019_out_0_data; // avalon_st_adapter_019:out_0_data -> io_led_green_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_019_out_0_ready; // io_led_green_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_019:out_0_ready
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wire [0:0] avalon_st_adapter_019_out_0_error; // avalon_st_adapter_019:out_0_error -> io_led_green_s1_agent:rdata_fifo_sink_error
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wire io_hex_s1_agent_rdata_fifo_src_valid; // io_hex_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_020:in_0_valid
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wire [33:0] io_hex_s1_agent_rdata_fifo_src_data; // io_hex_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_020:in_0_data
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wire io_hex_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_020:in_0_ready -> io_hex_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_020_out_0_valid; // avalon_st_adapter_020:out_0_valid -> io_hex_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_020_out_0_data; // avalon_st_adapter_020:out_0_data -> io_hex_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_020_out_0_ready; // io_hex_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_020:out_0_ready
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wire [0:0] avalon_st_adapter_020_out_0_error; // avalon_st_adapter_020:out_0_error -> io_hex_s1_agent:rdata_fifo_sink_error
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wire vga_sprite_0_s1_agent_rdata_fifo_src_valid; // vga_sprite_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_021:in_0_valid
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wire [33:0] vga_sprite_0_s1_agent_rdata_fifo_src_data; // vga_sprite_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_021:in_0_data
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wire vga_sprite_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_021:in_0_ready -> vga_sprite_0_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_021_out_0_valid; // avalon_st_adapter_021:out_0_valid -> vga_sprite_0_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_021_out_0_data; // avalon_st_adapter_021:out_0_data -> vga_sprite_0_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_021_out_0_ready; // vga_sprite_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_021:out_0_ready
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wire [0:0] avalon_st_adapter_021_out_0_error; // avalon_st_adapter_021:out_0_error -> vga_sprite_0_s1_agent:rdata_fifo_sink_error
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wire vga_sprite_1_s1_agent_rdata_fifo_src_valid; // vga_sprite_1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_022:in_0_valid
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wire [33:0] vga_sprite_1_s1_agent_rdata_fifo_src_data; // vga_sprite_1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_022:in_0_data
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wire vga_sprite_1_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_022:in_0_ready -> vga_sprite_1_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_022_out_0_valid; // avalon_st_adapter_022:out_0_valid -> vga_sprite_1_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_022_out_0_data; // avalon_st_adapter_022:out_0_data -> vga_sprite_1_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_022_out_0_ready; // vga_sprite_1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_022:out_0_ready
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wire [0:0] avalon_st_adapter_022_out_0_error; // avalon_st_adapter_022:out_0_error -> vga_sprite_1_s1_agent:rdata_fifo_sink_error
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wire vga_sprite_2_s1_agent_rdata_fifo_src_valid; // vga_sprite_2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_023:in_0_valid
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wire [33:0] vga_sprite_2_s1_agent_rdata_fifo_src_data; // vga_sprite_2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_023:in_0_data
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wire vga_sprite_2_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_023:in_0_ready -> vga_sprite_2_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_023_out_0_valid; // avalon_st_adapter_023:out_0_valid -> vga_sprite_2_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_023_out_0_data; // avalon_st_adapter_023:out_0_data -> vga_sprite_2_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_023_out_0_ready; // vga_sprite_2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_023:out_0_ready
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wire [0:0] avalon_st_adapter_023_out_0_error; // avalon_st_adapter_023:out_0_error -> vga_sprite_2_s1_agent:rdata_fifo_sink_error
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wire vga_sprite_3_s1_agent_rdata_fifo_src_valid; // vga_sprite_3_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_024:in_0_valid
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wire [33:0] vga_sprite_3_s1_agent_rdata_fifo_src_data; // vga_sprite_3_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_024:in_0_data
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wire vga_sprite_3_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_024:in_0_ready -> vga_sprite_3_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_024_out_0_valid; // avalon_st_adapter_024:out_0_valid -> vga_sprite_3_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_024_out_0_data; // avalon_st_adapter_024:out_0_data -> vga_sprite_3_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_024_out_0_ready; // vga_sprite_3_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_024:out_0_ready
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wire [0:0] avalon_st_adapter_024_out_0_error; // avalon_st_adapter_024:out_0_error -> vga_sprite_3_s1_agent:rdata_fifo_sink_error
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wire io_vga_sync_s1_agent_rdata_fifo_src_valid; // io_vga_sync_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_025:in_0_valid
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wire [33:0] io_vga_sync_s1_agent_rdata_fifo_src_data; // io_vga_sync_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_025:in_0_data
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wire io_vga_sync_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_025:in_0_ready -> io_vga_sync_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_025_out_0_valid; // avalon_st_adapter_025:out_0_valid -> io_vga_sync_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_025_out_0_data; // avalon_st_adapter_025:out_0_data -> io_vga_sync_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_025_out_0_ready; // io_vga_sync_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_025:out_0_ready
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wire [0:0] avalon_st_adapter_025_out_0_error; // avalon_st_adapter_025:out_0_error -> io_vga_sync_s1_agent:rdata_fifo_sink_error
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wire vga_sprite_4_s1_agent_rdata_fifo_src_valid; // vga_sprite_4_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_026:in_0_valid
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wire [33:0] vga_sprite_4_s1_agent_rdata_fifo_src_data; // vga_sprite_4_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_026:in_0_data
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wire vga_sprite_4_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_026:in_0_ready -> vga_sprite_4_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_026_out_0_valid; // avalon_st_adapter_026:out_0_valid -> vga_sprite_4_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_026_out_0_data; // avalon_st_adapter_026:out_0_data -> vga_sprite_4_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_026_out_0_ready; // vga_sprite_4_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_026:out_0_ready
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wire [0:0] avalon_st_adapter_026_out_0_error; // avalon_st_adapter_026:out_0_error -> vga_sprite_4_s1_agent:rdata_fifo_sink_error
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wire vga_sprite_5_s1_agent_rdata_fifo_src_valid; // vga_sprite_5_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_027:in_0_valid
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wire [33:0] vga_sprite_5_s1_agent_rdata_fifo_src_data; // vga_sprite_5_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_027:in_0_data
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wire vga_sprite_5_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_027:in_0_ready -> vga_sprite_5_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_027_out_0_valid; // avalon_st_adapter_027:out_0_valid -> vga_sprite_5_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_027_out_0_data; // avalon_st_adapter_027:out_0_data -> vga_sprite_5_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_027_out_0_ready; // vga_sprite_5_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_027:out_0_ready
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wire [0:0] avalon_st_adapter_027_out_0_error; // avalon_st_adapter_027:out_0_error -> vga_sprite_5_s1_agent:rdata_fifo_sink_error
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wire vga_sprite_6_s1_agent_rdata_fifo_src_valid; // vga_sprite_6_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_028:in_0_valid
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wire [33:0] vga_sprite_6_s1_agent_rdata_fifo_src_data; // vga_sprite_6_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_028:in_0_data
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wire vga_sprite_6_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_028:in_0_ready -> vga_sprite_6_s1_agent:rdata_fifo_src_ready
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wire avalon_st_adapter_028_out_0_valid; // avalon_st_adapter_028:out_0_valid -> vga_sprite_6_s1_agent:rdata_fifo_sink_valid
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wire [33:0] avalon_st_adapter_028_out_0_data; // avalon_st_adapter_028:out_0_data -> vga_sprite_6_s1_agent:rdata_fifo_sink_data
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wire avalon_st_adapter_028_out_0_ready; // vga_sprite_6_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_028:out_0_ready
|
|
wire [0:0] avalon_st_adapter_028_out_0_error; // avalon_st_adapter_028:out_0_error -> vga_sprite_6_s1_agent:rdata_fifo_sink_error
|
|
wire vga_sprite_7_s1_agent_rdata_fifo_src_valid; // vga_sprite_7_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_029:in_0_valid
|
|
wire [33:0] vga_sprite_7_s1_agent_rdata_fifo_src_data; // vga_sprite_7_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_029:in_0_data
|
|
wire vga_sprite_7_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_029:in_0_ready -> vga_sprite_7_s1_agent:rdata_fifo_src_ready
|
|
wire avalon_st_adapter_029_out_0_valid; // avalon_st_adapter_029:out_0_valid -> vga_sprite_7_s1_agent:rdata_fifo_sink_valid
|
|
wire [33:0] avalon_st_adapter_029_out_0_data; // avalon_st_adapter_029:out_0_data -> vga_sprite_7_s1_agent:rdata_fifo_sink_data
|
|
wire avalon_st_adapter_029_out_0_ready; // vga_sprite_7_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_029:out_0_ready
|
|
wire [0:0] avalon_st_adapter_029_out_0_error; // avalon_st_adapter_029:out_0_error -> vga_sprite_7_s1_agent:rdata_fifo_sink_error
|
|
wire vga_background_offset_s1_agent_rdata_fifo_src_valid; // vga_background_offset_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_030:in_0_valid
|
|
wire [33:0] vga_background_offset_s1_agent_rdata_fifo_src_data; // vga_background_offset_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_030:in_0_data
|
|
wire vga_background_offset_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_030:in_0_ready -> vga_background_offset_s1_agent:rdata_fifo_src_ready
|
|
wire avalon_st_adapter_030_out_0_valid; // avalon_st_adapter_030:out_0_valid -> vga_background_offset_s1_agent:rdata_fifo_sink_valid
|
|
wire [33:0] avalon_st_adapter_030_out_0_data; // avalon_st_adapter_030:out_0_data -> vga_background_offset_s1_agent:rdata_fifo_sink_data
|
|
wire avalon_st_adapter_030_out_0_ready; // vga_background_offset_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_030:out_0_ready
|
|
wire [0:0] avalon_st_adapter_030_out_0_error; // avalon_st_adapter_030:out_0_error -> vga_background_offset_s1_agent:rdata_fifo_sink_error
|
|
wire audio_pio_s1_agent_rdata_fifo_src_valid; // audio_pio_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_031:in_0_valid
|
|
wire [33:0] audio_pio_s1_agent_rdata_fifo_src_data; // audio_pio_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_031:in_0_data
|
|
wire audio_pio_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_031:in_0_ready -> audio_pio_s1_agent:rdata_fifo_src_ready
|
|
wire avalon_st_adapter_031_out_0_valid; // avalon_st_adapter_031:out_0_valid -> audio_pio_s1_agent:rdata_fifo_sink_valid
|
|
wire [33:0] avalon_st_adapter_031_out_0_data; // avalon_st_adapter_031:out_0_data -> audio_pio_s1_agent:rdata_fifo_sink_data
|
|
wire avalon_st_adapter_031_out_0_ready; // audio_pio_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_031:out_0_ready
|
|
wire [0:0] avalon_st_adapter_031_out_0_error; // avalon_st_adapter_031:out_0_error -> audio_pio_s1_agent:rdata_fifo_sink_error
|
|
wire audio_timer_s1_agent_rdata_fifo_src_valid; // audio_timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_032:in_0_valid
|
|
wire [33:0] audio_timer_s1_agent_rdata_fifo_src_data; // audio_timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_032:in_0_data
|
|
wire audio_timer_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_032:in_0_ready -> audio_timer_s1_agent:rdata_fifo_src_ready
|
|
wire avalon_st_adapter_032_out_0_valid; // avalon_st_adapter_032:out_0_valid -> audio_timer_s1_agent:rdata_fifo_sink_valid
|
|
wire [33:0] avalon_st_adapter_032_out_0_data; // avalon_st_adapter_032:out_0_data -> audio_timer_s1_agent:rdata_fifo_sink_data
|
|
wire avalon_st_adapter_032_out_0_ready; // audio_timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_032:out_0_ready
|
|
wire [0:0] avalon_st_adapter_032_out_0_error; // avalon_st_adapter_032:out_0_error -> audio_timer_s1_agent:rdata_fifo_sink_error
|
|
wire usb_keycode_s2_agent_rdata_fifo_src_valid; // usb_keycode_s2_agent:rdata_fifo_src_valid -> avalon_st_adapter_033:in_0_valid
|
|
wire [33:0] usb_keycode_s2_agent_rdata_fifo_src_data; // usb_keycode_s2_agent:rdata_fifo_src_data -> avalon_st_adapter_033:in_0_data
|
|
wire usb_keycode_s2_agent_rdata_fifo_src_ready; // avalon_st_adapter_033:in_0_ready -> usb_keycode_s2_agent:rdata_fifo_src_ready
|
|
wire avalon_st_adapter_033_out_0_valid; // avalon_st_adapter_033:out_0_valid -> usb_keycode_s2_agent:rdata_fifo_sink_valid
|
|
wire [33:0] avalon_st_adapter_033_out_0_data; // avalon_st_adapter_033:out_0_data -> usb_keycode_s2_agent:rdata_fifo_sink_data
|
|
wire avalon_st_adapter_033_out_0_ready; // usb_keycode_s2_agent:rdata_fifo_sink_ready -> avalon_st_adapter_033:out_0_ready
|
|
wire [0:0] avalon_st_adapter_033_out_0_error; // avalon_st_adapter_033:out_0_error -> usb_keycode_s2_agent:rdata_fifo_sink_error
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (28),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (1)
|
|
) nios2_cpu_data_master_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (nios2_cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (nios2_cpu_data_master_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (nios2_cpu_data_master_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (nios2_cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (nios2_cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (nios2_cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (nios2_cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (nios2_cpu_data_master_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (nios2_cpu_data_master_waitrequest), // .waitrequest
|
|
.av_byteenable (nios2_cpu_data_master_byteenable), // .byteenable
|
|
.av_read (nios2_cpu_data_master_read), // .read
|
|
.av_readdata (nios2_cpu_data_master_readdata), // .readdata
|
|
.av_write (nios2_cpu_data_master_write), // .write
|
|
.av_writedata (nios2_cpu_data_master_writedata), // .writedata
|
|
.av_debugaccess (nios2_cpu_data_master_debugaccess), // .debugaccess
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) nios2_dma_m_read_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_dma_m_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (nios2_dma_m_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (nios2_dma_m_read_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (nios2_dma_m_read_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (nios2_dma_m_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_dma_m_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_dma_m_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_dma_m_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (nios2_dma_m_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (nios2_dma_m_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (nios2_dma_m_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (nios2_dma_m_read_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (nios2_dma_m_read_waitrequest), // .waitrequest
|
|
.av_read (nios2_dma_m_read_read), // .read
|
|
.av_readdata (nios2_dma_m_read_readdata), // .readdata
|
|
.av_readdatavalid (nios2_dma_m_read_readdatavalid), // .readdatavalid
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (32),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (0),
|
|
.USE_WRITE (1),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (0),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) nios2_dma_m_write_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_dma_m_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (nios2_dma_m_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (nios2_dma_m_write_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (nios2_dma_m_write_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (nios2_dma_m_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_dma_m_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_dma_m_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_dma_m_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (nios2_dma_m_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (nios2_dma_m_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (nios2_dma_m_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (nios2_dma_m_write_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (nios2_dma_m_write_waitrequest), // .waitrequest
|
|
.av_byteenable (nios2_dma_m_write_byteenable), // .byteenable
|
|
.av_write (nios2_dma_m_write_write), // .write
|
|
.av_writedata (nios2_dma_m_write_writedata), // .writedata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_read (1'b0), // (terminated)
|
|
.av_readdata (), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_translator #(
|
|
.AV_ADDRESS_W (28),
|
|
.AV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.USE_READ (1),
|
|
.USE_WRITE (0),
|
|
.USE_BEGINBURSTTRANSFER (0),
|
|
.USE_BEGINTRANSFER (0),
|
|
.USE_CHIPSELECT (0),
|
|
.USE_BURSTCOUNT (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (1),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_LINEWRAPBURSTS (1),
|
|
.AV_REGISTERINCOMINGSIGNALS (0)
|
|
) nios2_cpu_instruction_master_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
|
|
.uav_burstcount (nios2_cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.uav_read (nios2_cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
|
|
.uav_write (nios2_cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
|
|
.uav_waitrequest (nios2_cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.uav_writedata (nios2_cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.uav_lock (nios2_cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
|
|
.uav_debugaccess (nios2_cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_address (nios2_cpu_instruction_master_address), // avalon_anti_master_0.address
|
|
.av_waitrequest (nios2_cpu_instruction_master_waitrequest), // .waitrequest
|
|
.av_read (nios2_cpu_instruction_master_read), // .read
|
|
.av_readdata (nios2_cpu_instruction_master_readdata), // .readdata
|
|
.av_burstcount (1'b1), // (terminated)
|
|
.av_byteenable (4'b1111), // (terminated)
|
|
.av_beginbursttransfer (1'b0), // (terminated)
|
|
.av_begintransfer (1'b0), // (terminated)
|
|
.av_chipselect (1'b0), // (terminated)
|
|
.av_readdatavalid (), // (terminated)
|
|
.av_write (1'b0), // (terminated)
|
|
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.av_lock (1'b0), // (terminated)
|
|
.av_debugaccess (1'b0), // (terminated)
|
|
.uav_clken (), // (terminated)
|
|
.av_clken (1'b1), // (terminated)
|
|
.uav_response (2'b00), // (terminated)
|
|
.av_response (), // (terminated)
|
|
.uav_writeresponsevalid (1'b0), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (1),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) nios2_jtag_uart_avalon_jtag_slave_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (nios2_jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
|
|
.uav_read (nios2_jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
|
|
.uav_write (nios2_jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
|
|
.uav_waitrequest (nios2_jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
|
|
.uav_writedata (nios2_jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
|
|
.uav_lock (nios2_jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
|
|
.uav_debugaccess (nios2_jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (nios2_jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
|
|
.av_write (nios2_jtag_uart_avalon_jtag_slave_write), // .write
|
|
.av_read (nios2_jtag_uart_avalon_jtag_slave_read), // .read
|
|
.av_readdata (nios2_jtag_uart_avalon_jtag_slave_readdata), // .readdata
|
|
.av_writedata (nios2_jtag_uart_avalon_jtag_slave_writedata), // .writedata
|
|
.av_waitrequest (nios2_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
|
|
.av_chipselect (nios2_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (5),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) eth1_mdio_avalon_slave_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_mdio_avalon_slave_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (eth1_mdio_avalon_slave_agent_m0_burstcount), // .burstcount
|
|
.uav_read (eth1_mdio_avalon_slave_agent_m0_read), // .read
|
|
.uav_write (eth1_mdio_avalon_slave_agent_m0_write), // .write
|
|
.uav_waitrequest (eth1_mdio_avalon_slave_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_mdio_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_mdio_avalon_slave_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_mdio_avalon_slave_agent_m0_readdata), // .readdata
|
|
.uav_writedata (eth1_mdio_avalon_slave_agent_m0_writedata), // .writedata
|
|
.uav_lock (eth1_mdio_avalon_slave_agent_m0_lock), // .lock
|
|
.uav_debugaccess (eth1_mdio_avalon_slave_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (eth1_mdio_avalon_slave_address), // avalon_anti_slave_0.address
|
|
.av_write (eth1_mdio_avalon_slave_write), // .write
|
|
.av_read (eth1_mdio_avalon_slave_read), // .read
|
|
.av_readdata (eth1_mdio_avalon_slave_readdata), // .readdata
|
|
.av_writedata (eth1_mdio_avalon_slave_writedata), // .writedata
|
|
.av_waitrequest (eth1_mdio_avalon_slave_waitrequest), // .waitrequest
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (5),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) eth0_mdio_avalon_slave_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_mdio_avalon_slave_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (eth0_mdio_avalon_slave_agent_m0_burstcount), // .burstcount
|
|
.uav_read (eth0_mdio_avalon_slave_agent_m0_read), // .read
|
|
.uav_write (eth0_mdio_avalon_slave_agent_m0_write), // .write
|
|
.uav_waitrequest (eth0_mdio_avalon_slave_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_mdio_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_mdio_avalon_slave_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_mdio_avalon_slave_agent_m0_readdata), // .readdata
|
|
.uav_writedata (eth0_mdio_avalon_slave_agent_m0_writedata), // .writedata
|
|
.uav_lock (eth0_mdio_avalon_slave_agent_m0_lock), // .lock
|
|
.uav_debugaccess (eth0_mdio_avalon_slave_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (eth0_mdio_avalon_slave_address), // avalon_anti_slave_0.address
|
|
.av_write (eth0_mdio_avalon_slave_write), // .write
|
|
.av_read (eth0_mdio_avalon_slave_read), // .read
|
|
.av_readdata (eth0_mdio_avalon_slave_readdata), // .readdata
|
|
.av_writedata (eth0_mdio_avalon_slave_writedata), // .writedata
|
|
.av_waitrequest (eth0_mdio_avalon_slave_waitrequest), // .waitrequest
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (20),
|
|
.AV_DATA_W (16),
|
|
.UAV_DATA_W (16),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (2),
|
|
.UAV_BYTEENABLE_W (2),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (2),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (2),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) sram_multiplexer_avl_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (sram_multiplexer_avl_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (sram_multiplexer_avl_agent_m0_burstcount), // .burstcount
|
|
.uav_read (sram_multiplexer_avl_agent_m0_read), // .read
|
|
.uav_write (sram_multiplexer_avl_agent_m0_write), // .write
|
|
.uav_waitrequest (sram_multiplexer_avl_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (sram_multiplexer_avl_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (sram_multiplexer_avl_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (sram_multiplexer_avl_agent_m0_readdata), // .readdata
|
|
.uav_writedata (sram_multiplexer_avl_agent_m0_writedata), // .writedata
|
|
.uav_lock (sram_multiplexer_avl_agent_m0_lock), // .lock
|
|
.uav_debugaccess (sram_multiplexer_avl_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (sram_multiplexer_avl_address), // avalon_anti_slave_0.address
|
|
.av_write (sram_multiplexer_avl_write), // .write
|
|
.av_read (sram_multiplexer_avl_read), // .read
|
|
.av_readdata (sram_multiplexer_avl_readdata), // .readdata
|
|
.av_writedata (sram_multiplexer_avl_writedata), // .writedata
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (8),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_params_avl_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_params_avl_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_params_avl_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_params_avl_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_params_avl_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_params_avl_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_params_avl_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_params_avl_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_params_avl_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_params_avl_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_params_avl_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_params_avl_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_params_avl_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_params_avl_write), // .write
|
|
.av_read (vga_sprite_params_avl_read), // .read
|
|
.av_readdata (vga_sprite_params_avl_readdata), // .readdata
|
|
.av_writedata (vga_sprite_params_avl_writedata), // .writedata
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (1),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) nios2_sysid_control_slave_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_sysid_control_slave_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (nios2_sysid_control_slave_agent_m0_burstcount), // .burstcount
|
|
.uav_read (nios2_sysid_control_slave_agent_m0_read), // .read
|
|
.uav_write (nios2_sysid_control_slave_agent_m0_write), // .write
|
|
.uav_waitrequest (nios2_sysid_control_slave_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_sysid_control_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_sysid_control_slave_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_sysid_control_slave_agent_m0_readdata), // .readdata
|
|
.uav_writedata (nios2_sysid_control_slave_agent_m0_writedata), // .writedata
|
|
.uav_lock (nios2_sysid_control_slave_agent_m0_lock), // .lock
|
|
.uav_debugaccess (nios2_sysid_control_slave_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (nios2_sysid_control_slave_address), // avalon_anti_slave_0.address
|
|
.av_readdata (nios2_sysid_control_slave_readdata), // .readdata
|
|
.av_write (), // (terminated)
|
|
.av_read (), // (terminated)
|
|
.av_writedata (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (4),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) eth0_rx_dma_csr_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_rx_dma_csr_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (eth0_rx_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.uav_read (eth0_rx_dma_csr_agent_m0_read), // .read
|
|
.uav_write (eth0_rx_dma_csr_agent_m0_write), // .write
|
|
.uav_waitrequest (eth0_rx_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_rx_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_rx_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_rx_dma_csr_agent_m0_readdata), // .readdata
|
|
.uav_writedata (eth0_rx_dma_csr_agent_m0_writedata), // .writedata
|
|
.uav_lock (eth0_rx_dma_csr_agent_m0_lock), // .lock
|
|
.uav_debugaccess (eth0_rx_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (eth0_rx_dma_csr_address), // avalon_anti_slave_0.address
|
|
.av_write (eth0_rx_dma_csr_write), // .write
|
|
.av_read (eth0_rx_dma_csr_read), // .read
|
|
.av_readdata (eth0_rx_dma_csr_readdata), // .readdata
|
|
.av_writedata (eth0_rx_dma_csr_writedata), // .writedata
|
|
.av_chipselect (eth0_rx_dma_csr_chipselect), // .chipselect
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (4),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) eth0_tx_dma_csr_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth0_tx_dma_csr_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (eth0_tx_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.uav_read (eth0_tx_dma_csr_agent_m0_read), // .read
|
|
.uav_write (eth0_tx_dma_csr_agent_m0_write), // .write
|
|
.uav_waitrequest (eth0_tx_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth0_tx_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth0_tx_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (eth0_tx_dma_csr_agent_m0_readdata), // .readdata
|
|
.uav_writedata (eth0_tx_dma_csr_agent_m0_writedata), // .writedata
|
|
.uav_lock (eth0_tx_dma_csr_agent_m0_lock), // .lock
|
|
.uav_debugaccess (eth0_tx_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (eth0_tx_dma_csr_address), // avalon_anti_slave_0.address
|
|
.av_write (eth0_tx_dma_csr_write), // .write
|
|
.av_read (eth0_tx_dma_csr_read), // .read
|
|
.av_readdata (eth0_tx_dma_csr_readdata), // .readdata
|
|
.av_writedata (eth0_tx_dma_csr_writedata), // .writedata
|
|
.av_chipselect (eth0_tx_dma_csr_chipselect), // .chipselect
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (4),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) eth1_rx_dma_csr_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_rx_dma_csr_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (eth1_rx_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.uav_read (eth1_rx_dma_csr_agent_m0_read), // .read
|
|
.uav_write (eth1_rx_dma_csr_agent_m0_write), // .write
|
|
.uav_waitrequest (eth1_rx_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_rx_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_rx_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_rx_dma_csr_agent_m0_readdata), // .readdata
|
|
.uav_writedata (eth1_rx_dma_csr_agent_m0_writedata), // .writedata
|
|
.uav_lock (eth1_rx_dma_csr_agent_m0_lock), // .lock
|
|
.uav_debugaccess (eth1_rx_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (eth1_rx_dma_csr_address), // avalon_anti_slave_0.address
|
|
.av_write (eth1_rx_dma_csr_write), // .write
|
|
.av_read (eth1_rx_dma_csr_read), // .read
|
|
.av_readdata (eth1_rx_dma_csr_readdata), // .readdata
|
|
.av_writedata (eth1_rx_dma_csr_writedata), // .writedata
|
|
.av_chipselect (eth1_rx_dma_csr_chipselect), // .chipselect
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (4),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) eth1_tx_dma_csr_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (eth1_tx_dma_csr_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (eth1_tx_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.uav_read (eth1_tx_dma_csr_agent_m0_read), // .read
|
|
.uav_write (eth1_tx_dma_csr_agent_m0_write), // .write
|
|
.uav_waitrequest (eth1_tx_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (eth1_tx_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (eth1_tx_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (eth1_tx_dma_csr_agent_m0_readdata), // .readdata
|
|
.uav_writedata (eth1_tx_dma_csr_agent_m0_writedata), // .writedata
|
|
.uav_lock (eth1_tx_dma_csr_agent_m0_lock), // .lock
|
|
.uav_debugaccess (eth1_tx_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (eth1_tx_dma_csr_address), // avalon_anti_slave_0.address
|
|
.av_write (eth1_tx_dma_csr_write), // .write
|
|
.av_read (eth1_tx_dma_csr_read), // .read
|
|
.av_readdata (eth1_tx_dma_csr_readdata), // .readdata
|
|
.av_writedata (eth1_tx_dma_csr_writedata), // .writedata
|
|
.av_chipselect (eth1_tx_dma_csr_chipselect), // .chipselect
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (4),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) nios2_dma_csr_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_dma_csr_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (nios2_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.uav_read (nios2_dma_csr_agent_m0_read), // .read
|
|
.uav_write (nios2_dma_csr_agent_m0_write), // .write
|
|
.uav_waitrequest (nios2_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_dma_csr_agent_m0_readdata), // .readdata
|
|
.uav_writedata (nios2_dma_csr_agent_m0_writedata), // .writedata
|
|
.uav_lock (nios2_dma_csr_agent_m0_lock), // .lock
|
|
.uav_debugaccess (nios2_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (nios2_dma_csr_address), // avalon_anti_slave_0.address
|
|
.av_write (nios2_dma_csr_write), // .write
|
|
.av_read (nios2_dma_csr_read), // .read
|
|
.av_readdata (nios2_dma_csr_readdata), // .readdata
|
|
.av_writedata (nios2_dma_csr_writedata), // .writedata
|
|
.av_chipselect (nios2_dma_csr_chipselect), // .chipselect
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (9),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) nios2_cpu_debug_mem_slave_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_cpu_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (nios2_cpu_debug_mem_slave_agent_m0_burstcount), // .burstcount
|
|
.uav_read (nios2_cpu_debug_mem_slave_agent_m0_read), // .read
|
|
.uav_write (nios2_cpu_debug_mem_slave_agent_m0_write), // .write
|
|
.uav_waitrequest (nios2_cpu_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_cpu_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_cpu_debug_mem_slave_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_cpu_debug_mem_slave_agent_m0_readdata), // .readdata
|
|
.uav_writedata (nios2_cpu_debug_mem_slave_agent_m0_writedata), // .writedata
|
|
.uav_lock (nios2_cpu_debug_mem_slave_agent_m0_lock), // .lock
|
|
.uav_debugaccess (nios2_cpu_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (nios2_cpu_debug_mem_slave_address), // avalon_anti_slave_0.address
|
|
.av_write (nios2_cpu_debug_mem_slave_write), // .write
|
|
.av_read (nios2_cpu_debug_mem_slave_read), // .read
|
|
.av_readdata (nios2_cpu_debug_mem_slave_readdata), // .readdata
|
|
.av_writedata (nios2_cpu_debug_mem_slave_writedata), // .writedata
|
|
.av_byteenable (nios2_cpu_debug_mem_slave_byteenable), // .byteenable
|
|
.av_waitrequest (nios2_cpu_debug_mem_slave_waitrequest), // .waitrequest
|
|
.av_debugaccess (nios2_cpu_debug_mem_slave_debugaccess), // .debugaccess
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (2),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) nios2_pll_pll_slave_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_pll_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (nios2_pll_pll_slave_agent_m0_burstcount), // .burstcount
|
|
.uav_read (nios2_pll_pll_slave_agent_m0_read), // .read
|
|
.uav_write (nios2_pll_pll_slave_agent_m0_write), // .write
|
|
.uav_waitrequest (nios2_pll_pll_slave_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_pll_pll_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_pll_pll_slave_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_pll_pll_slave_agent_m0_readdata), // .readdata
|
|
.uav_writedata (nios2_pll_pll_slave_agent_m0_writedata), // .writedata
|
|
.uav_lock (nios2_pll_pll_slave_agent_m0_lock), // .lock
|
|
.uav_debugaccess (nios2_pll_pll_slave_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (nios2_pll_pll_slave_address), // avalon_anti_slave_0.address
|
|
.av_write (nios2_pll_pll_slave_write), // .write
|
|
.av_read (nios2_pll_pll_slave_read), // .read
|
|
.av_readdata (nios2_pll_pll_slave_readdata), // .readdata
|
|
.av_writedata (nios2_pll_pll_slave_writedata), // .writedata
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (16),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) nios2_onchip_mem_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_onchip_mem_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (nios2_onchip_mem_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (nios2_onchip_mem_s1_agent_m0_read), // .read
|
|
.uav_write (nios2_onchip_mem_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (nios2_onchip_mem_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_onchip_mem_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_onchip_mem_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_onchip_mem_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (nios2_onchip_mem_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (nios2_onchip_mem_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (nios2_onchip_mem_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (nios2_onchip_mem_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (nios2_onchip_mem_s1_write), // .write
|
|
.av_readdata (nios2_onchip_mem_s1_readdata), // .readdata
|
|
.av_writedata (nios2_onchip_mem_s1_writedata), // .writedata
|
|
.av_byteenable (nios2_onchip_mem_s1_byteenable), // .byteenable
|
|
.av_chipselect (nios2_onchip_mem_s1_chipselect), // .chipselect
|
|
.av_clken (nios2_onchip_mem_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (25),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (1),
|
|
.USE_WAITREQUEST (1),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) sdram_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (sdram_s1_agent_m0_read), // .read
|
|
.uav_write (sdram_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (sdram_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (sdram_s1_write), // .write
|
|
.av_read (sdram_s1_read), // .read
|
|
.av_readdata (sdram_s1_readdata), // .readdata
|
|
.av_writedata (sdram_s1_writedata), // .writedata
|
|
.av_byteenable (sdram_s1_byteenable), // .byteenable
|
|
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
|
|
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
|
|
.av_chipselect (sdram_s1_chipselect), // .chipselect
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (3),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) io_led_red_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (io_led_red_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (io_led_red_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (io_led_red_s1_agent_m0_read), // .read
|
|
.uav_write (io_led_red_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (io_led_red_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (io_led_red_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (io_led_red_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (io_led_red_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (io_led_red_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (io_led_red_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (io_led_red_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (io_led_red_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (io_led_red_s1_write), // .write
|
|
.av_readdata (io_led_red_s1_readdata), // .readdata
|
|
.av_writedata (io_led_red_s1_writedata), // .writedata
|
|
.av_chipselect (io_led_red_s1_chipselect), // .chipselect
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (3),
|
|
.AV_DATA_W (16),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) nios2_timer_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (nios2_timer_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (nios2_timer_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (nios2_timer_s1_agent_m0_read), // .read
|
|
.uav_write (nios2_timer_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (nios2_timer_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (nios2_timer_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (nios2_timer_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (nios2_timer_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (nios2_timer_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (nios2_timer_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (nios2_timer_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (nios2_timer_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (nios2_timer_s1_write), // .write
|
|
.av_readdata (nios2_timer_s1_readdata), // .readdata
|
|
.av_writedata (nios2_timer_s1_writedata), // .writedata
|
|
.av_chipselect (nios2_timer_s1_chipselect), // .chipselect
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (2),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) io_keys_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (io_keys_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (io_keys_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (io_keys_s1_agent_m0_read), // .read
|
|
.uav_write (io_keys_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (io_keys_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (io_keys_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (io_keys_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (io_keys_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (io_keys_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (io_keys_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (io_keys_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (io_keys_s1_address), // avalon_anti_slave_0.address
|
|
.av_readdata (io_keys_s1_readdata), // .readdata
|
|
.av_write (), // (terminated)
|
|
.av_read (), // (terminated)
|
|
.av_writedata (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (2),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) io_switches_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (io_switches_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (io_switches_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (io_switches_s1_agent_m0_read), // .read
|
|
.uav_write (io_switches_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (io_switches_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (io_switches_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (io_switches_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (io_switches_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (io_switches_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (io_switches_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (io_switches_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (io_switches_s1_address), // avalon_anti_slave_0.address
|
|
.av_readdata (io_switches_s1_readdata), // .readdata
|
|
.av_write (), // (terminated)
|
|
.av_read (), // (terminated)
|
|
.av_writedata (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (3),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) io_led_green_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (io_led_green_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (io_led_green_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (io_led_green_s1_agent_m0_read), // .read
|
|
.uav_write (io_led_green_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (io_led_green_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (io_led_green_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (io_led_green_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (io_led_green_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (io_led_green_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (io_led_green_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (io_led_green_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (io_led_green_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (io_led_green_s1_write), // .write
|
|
.av_readdata (io_led_green_s1_readdata), // .readdata
|
|
.av_writedata (io_led_green_s1_writedata), // .writedata
|
|
.av_chipselect (io_led_green_s1_chipselect), // .chipselect
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (3),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) io_hex_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (io_hex_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (io_hex_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (io_hex_s1_agent_m0_read), // .read
|
|
.uav_write (io_hex_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (io_hex_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (io_hex_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (io_hex_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (io_hex_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (io_hex_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (io_hex_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (io_hex_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (io_hex_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (io_hex_s1_write), // .write
|
|
.av_readdata (io_hex_s1_readdata), // .readdata
|
|
.av_writedata (io_hex_s1_writedata), // .writedata
|
|
.av_chipselect (io_hex_s1_chipselect), // .chipselect
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (10),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_0_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_0_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_0_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_0_s1_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_0_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_0_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_0_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_0_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_0_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_0_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_0_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_0_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_0_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_0_s1_write), // .write
|
|
.av_readdata (vga_sprite_0_s1_readdata), // .readdata
|
|
.av_writedata (vga_sprite_0_s1_writedata), // .writedata
|
|
.av_byteenable (vga_sprite_0_s1_byteenable), // .byteenable
|
|
.av_chipselect (vga_sprite_0_s1_chipselect), // .chipselect
|
|
.av_clken (vga_sprite_0_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (10),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_1_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_1_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_1_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_1_s1_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_1_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_1_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_1_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_1_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_1_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_1_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_1_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_1_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_1_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_1_s1_write), // .write
|
|
.av_readdata (vga_sprite_1_s1_readdata), // .readdata
|
|
.av_writedata (vga_sprite_1_s1_writedata), // .writedata
|
|
.av_byteenable (vga_sprite_1_s1_byteenable), // .byteenable
|
|
.av_chipselect (vga_sprite_1_s1_chipselect), // .chipselect
|
|
.av_clken (vga_sprite_1_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (10),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_2_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_2_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_2_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_2_s1_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_2_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_2_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_2_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_2_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_2_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_2_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_2_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_2_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_2_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_2_s1_write), // .write
|
|
.av_readdata (vga_sprite_2_s1_readdata), // .readdata
|
|
.av_writedata (vga_sprite_2_s1_writedata), // .writedata
|
|
.av_byteenable (vga_sprite_2_s1_byteenable), // .byteenable
|
|
.av_chipselect (vga_sprite_2_s1_chipselect), // .chipselect
|
|
.av_clken (vga_sprite_2_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (10),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_3_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_3_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_3_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_3_s1_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_3_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_3_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_3_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_3_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_3_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_3_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_3_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_3_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_3_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_3_s1_write), // .write
|
|
.av_readdata (vga_sprite_3_s1_readdata), // .readdata
|
|
.av_writedata (vga_sprite_3_s1_writedata), // .writedata
|
|
.av_byteenable (vga_sprite_3_s1_byteenable), // .byteenable
|
|
.av_chipselect (vga_sprite_3_s1_chipselect), // .chipselect
|
|
.av_clken (vga_sprite_3_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (2),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) io_vga_sync_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (io_vga_sync_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (io_vga_sync_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (io_vga_sync_s1_agent_m0_read), // .read
|
|
.uav_write (io_vga_sync_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (io_vga_sync_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (io_vga_sync_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (io_vga_sync_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (io_vga_sync_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (io_vga_sync_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (io_vga_sync_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (io_vga_sync_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (io_vga_sync_s1_address), // avalon_anti_slave_0.address
|
|
.av_readdata (io_vga_sync_s1_readdata), // .readdata
|
|
.av_write (), // (terminated)
|
|
.av_read (), // (terminated)
|
|
.av_writedata (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_chipselect (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (10),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_4_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_4_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_4_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_4_s1_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_4_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_4_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_4_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_4_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_4_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_4_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_4_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_4_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_4_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_4_s1_write), // .write
|
|
.av_readdata (vga_sprite_4_s1_readdata), // .readdata
|
|
.av_writedata (vga_sprite_4_s1_writedata), // .writedata
|
|
.av_byteenable (vga_sprite_4_s1_byteenable), // .byteenable
|
|
.av_chipselect (vga_sprite_4_s1_chipselect), // .chipselect
|
|
.av_clken (vga_sprite_4_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (10),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_5_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_5_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_5_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_5_s1_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_5_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_5_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_5_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_5_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_5_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_5_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_5_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_5_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_5_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_5_s1_write), // .write
|
|
.av_readdata (vga_sprite_5_s1_readdata), // .readdata
|
|
.av_writedata (vga_sprite_5_s1_writedata), // .writedata
|
|
.av_byteenable (vga_sprite_5_s1_byteenable), // .byteenable
|
|
.av_chipselect (vga_sprite_5_s1_chipselect), // .chipselect
|
|
.av_clken (vga_sprite_5_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (10),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_6_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_6_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_6_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_6_s1_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_6_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_6_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_6_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_6_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_6_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_6_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_6_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_6_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_6_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_6_s1_write), // .write
|
|
.av_readdata (vga_sprite_6_s1_readdata), // .readdata
|
|
.av_writedata (vga_sprite_6_s1_writedata), // .writedata
|
|
.av_byteenable (vga_sprite_6_s1_byteenable), // .byteenable
|
|
.av_chipselect (vga_sprite_6_s1_chipselect), // .chipselect
|
|
.av_clken (vga_sprite_6_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (10),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_sprite_7_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_sprite_7_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_sprite_7_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_sprite_7_s1_agent_m0_read), // .read
|
|
.uav_write (vga_sprite_7_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_sprite_7_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_sprite_7_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_sprite_7_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_sprite_7_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_sprite_7_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_sprite_7_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_sprite_7_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_sprite_7_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_sprite_7_s1_write), // .write
|
|
.av_readdata (vga_sprite_7_s1_readdata), // .readdata
|
|
.av_writedata (vga_sprite_7_s1_writedata), // .writedata
|
|
.av_byteenable (vga_sprite_7_s1_byteenable), // .byteenable
|
|
.av_chipselect (vga_sprite_7_s1_chipselect), // .chipselect
|
|
.av_clken (vga_sprite_7_s1_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (2),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) vga_background_offset_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (vga_background_offset_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (vga_background_offset_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (vga_background_offset_s1_agent_m0_read), // .read
|
|
.uav_write (vga_background_offset_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (vga_background_offset_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (vga_background_offset_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (vga_background_offset_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (vga_background_offset_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (vga_background_offset_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (vga_background_offset_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (vga_background_offset_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (vga_background_offset_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (vga_background_offset_s1_write), // .write
|
|
.av_readdata (vga_background_offset_s1_readdata), // .readdata
|
|
.av_writedata (vga_background_offset_s1_writedata), // .writedata
|
|
.av_chipselect (vga_background_offset_s1_chipselect), // .chipselect
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (2),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) audio_pio_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (audio_pio_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (audio_pio_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (audio_pio_s1_agent_m0_read), // .read
|
|
.uav_write (audio_pio_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (audio_pio_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (audio_pio_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (audio_pio_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (audio_pio_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (audio_pio_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (audio_pio_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (audio_pio_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (audio_pio_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (audio_pio_s1_write), // .write
|
|
.av_readdata (audio_pio_s1_readdata), // .readdata
|
|
.av_writedata (audio_pio_s1_writedata), // .writedata
|
|
.av_chipselect (audio_pio_s1_chipselect), // .chipselect
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (3),
|
|
.AV_DATA_W (16),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (1),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (0),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (1),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) audio_timer_s1_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (audio_timer_s1_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (audio_timer_s1_agent_m0_burstcount), // .burstcount
|
|
.uav_read (audio_timer_s1_agent_m0_read), // .read
|
|
.uav_write (audio_timer_s1_agent_m0_write), // .write
|
|
.uav_waitrequest (audio_timer_s1_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (audio_timer_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (audio_timer_s1_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (audio_timer_s1_agent_m0_readdata), // .readdata
|
|
.uav_writedata (audio_timer_s1_agent_m0_writedata), // .writedata
|
|
.uav_lock (audio_timer_s1_agent_m0_lock), // .lock
|
|
.uav_debugaccess (audio_timer_s1_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (audio_timer_s1_address), // avalon_anti_slave_0.address
|
|
.av_write (audio_timer_s1_write), // .write
|
|
.av_readdata (audio_timer_s1_readdata), // .readdata
|
|
.av_writedata (audio_timer_s1_writedata), // .writedata
|
|
.av_chipselect (audio_timer_s1_chipselect), // .chipselect
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_byteenable (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.av_clken (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_translator #(
|
|
.AV_ADDRESS_W (8),
|
|
.AV_DATA_W (32),
|
|
.UAV_DATA_W (32),
|
|
.AV_BURSTCOUNT_W (1),
|
|
.AV_BYTEENABLE_W (4),
|
|
.UAV_BYTEENABLE_W (4),
|
|
.UAV_ADDRESS_W (32),
|
|
.UAV_BURSTCOUNT_W (3),
|
|
.AV_READLATENCY (1),
|
|
.USE_READDATAVALID (0),
|
|
.USE_WAITREQUEST (0),
|
|
.USE_UAV_CLKEN (0),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.AV_SYMBOLS_PER_WORD (4),
|
|
.AV_ADDRESS_SYMBOLS (0),
|
|
.AV_BURSTCOUNT_SYMBOLS (0),
|
|
.AV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.UAV_CONSTANT_BURST_BEHAVIOR (0),
|
|
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
|
|
.CHIPSELECT_THROUGH_READLATENCY (0),
|
|
.AV_READ_WAIT_CYCLES (0),
|
|
.AV_WRITE_WAIT_CYCLES (0),
|
|
.AV_SETUP_WAIT_CYCLES (0),
|
|
.AV_DATA_HOLD_CYCLES (0)
|
|
) usb_keycode_s2_translator (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // reset.reset
|
|
.uav_address (usb_keycode_s2_agent_m0_address), // avalon_universal_slave_0.address
|
|
.uav_burstcount (usb_keycode_s2_agent_m0_burstcount), // .burstcount
|
|
.uav_read (usb_keycode_s2_agent_m0_read), // .read
|
|
.uav_write (usb_keycode_s2_agent_m0_write), // .write
|
|
.uav_waitrequest (usb_keycode_s2_agent_m0_waitrequest), // .waitrequest
|
|
.uav_readdatavalid (usb_keycode_s2_agent_m0_readdatavalid), // .readdatavalid
|
|
.uav_byteenable (usb_keycode_s2_agent_m0_byteenable), // .byteenable
|
|
.uav_readdata (usb_keycode_s2_agent_m0_readdata), // .readdata
|
|
.uav_writedata (usb_keycode_s2_agent_m0_writedata), // .writedata
|
|
.uav_lock (usb_keycode_s2_agent_m0_lock), // .lock
|
|
.uav_debugaccess (usb_keycode_s2_agent_m0_debugaccess), // .debugaccess
|
|
.av_address (usb_keycode_s2_address), // avalon_anti_slave_0.address
|
|
.av_write (usb_keycode_s2_write), // .write
|
|
.av_readdata (usb_keycode_s2_readdata), // .readdata
|
|
.av_writedata (usb_keycode_s2_writedata), // .writedata
|
|
.av_byteenable (usb_keycode_s2_byteenable), // .byteenable
|
|
.av_chipselect (usb_keycode_s2_chipselect), // .chipselect
|
|
.av_clken (usb_keycode_s2_clken), // .clken
|
|
.av_read (), // (terminated)
|
|
.av_begintransfer (), // (terminated)
|
|
.av_beginbursttransfer (), // (terminated)
|
|
.av_burstcount (), // (terminated)
|
|
.av_readdatavalid (1'b0), // (terminated)
|
|
.av_waitrequest (1'b0), // (terminated)
|
|
.av_writebyteenable (), // (terminated)
|
|
.av_lock (), // (terminated)
|
|
.uav_clken (1'b0), // (terminated)
|
|
.av_debugaccess (), // (terminated)
|
|
.av_outputenable (), // (terminated)
|
|
.uav_response (), // (terminated)
|
|
.av_response (2'b00), // (terminated)
|
|
.uav_writeresponsevalid (), // (terminated)
|
|
.av_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_QOS_H (88),
|
|
.PKT_QOS_L (88),
|
|
.PKT_DATA_SIDEBAND_H (86),
|
|
.PKT_DATA_SIDEBAND_L (86),
|
|
.PKT_ADDR_SIDEBAND_H (85),
|
|
.PKT_ADDR_SIDEBAND_L (85),
|
|
.PKT_BURST_TYPE_H (84),
|
|
.PKT_BURST_TYPE_L (83),
|
|
.PKT_CACHE_H (108),
|
|
.PKT_CACHE_L (105),
|
|
.PKT_THREAD_ID_H (101),
|
|
.PKT_THREAD_ID_L (101),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.ST_DATA_W (114),
|
|
.ST_CHANNEL_W (34),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (0),
|
|
.BURSTWRAP_VALUE (7),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) nios2_cpu_data_master_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (nios2_cpu_data_master_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (nios2_cpu_data_master_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (nios2_cpu_data_master_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (nios2_cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (nios2_cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (nios2_cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (nios2_cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (nios2_cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (nios2_cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (nios2_cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (nios2_cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (nios2_cpu_data_master_agent_cp_valid), // cp.valid
|
|
.cp_data (nios2_cpu_data_master_agent_cp_data), // .data
|
|
.cp_startofpacket (nios2_cpu_data_master_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (nios2_cpu_data_master_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (nios2_cpu_data_master_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_src_data), // .data
|
|
.rp_channel (rsp_mux_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_QOS_H (88),
|
|
.PKT_QOS_L (88),
|
|
.PKT_DATA_SIDEBAND_H (86),
|
|
.PKT_DATA_SIDEBAND_L (86),
|
|
.PKT_ADDR_SIDEBAND_H (85),
|
|
.PKT_ADDR_SIDEBAND_L (85),
|
|
.PKT_BURST_TYPE_H (84),
|
|
.PKT_BURST_TYPE_L (83),
|
|
.PKT_CACHE_H (108),
|
|
.PKT_CACHE_L (105),
|
|
.PKT_THREAD_ID_H (101),
|
|
.PKT_THREAD_ID_L (101),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.ST_DATA_W (114),
|
|
.ST_CHANNEL_W (34),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (2),
|
|
.BURSTWRAP_VALUE (7),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) nios2_dma_m_read_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (nios2_dma_m_read_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (nios2_dma_m_read_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (nios2_dma_m_read_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (nios2_dma_m_read_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (nios2_dma_m_read_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (nios2_dma_m_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (nios2_dma_m_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (nios2_dma_m_read_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (nios2_dma_m_read_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (nios2_dma_m_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (nios2_dma_m_read_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (nios2_dma_m_read_agent_cp_valid), // cp.valid
|
|
.cp_data (nios2_dma_m_read_agent_cp_data), // .data
|
|
.cp_startofpacket (nios2_dma_m_read_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (nios2_dma_m_read_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (nios2_dma_m_read_agent_cp_ready), // .ready
|
|
.rp_valid (nios2_dma_m_read_limiter_rsp_src_valid), // rp.valid
|
|
.rp_data (nios2_dma_m_read_limiter_rsp_src_data), // .data
|
|
.rp_channel (nios2_dma_m_read_limiter_rsp_src_channel), // .channel
|
|
.rp_startofpacket (nios2_dma_m_read_limiter_rsp_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (nios2_dma_m_read_limiter_rsp_src_endofpacket), // .endofpacket
|
|
.rp_ready (nios2_dma_m_read_limiter_rsp_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_QOS_H (88),
|
|
.PKT_QOS_L (88),
|
|
.PKT_DATA_SIDEBAND_H (86),
|
|
.PKT_DATA_SIDEBAND_L (86),
|
|
.PKT_ADDR_SIDEBAND_H (85),
|
|
.PKT_ADDR_SIDEBAND_L (85),
|
|
.PKT_BURST_TYPE_H (84),
|
|
.PKT_BURST_TYPE_L (83),
|
|
.PKT_CACHE_H (108),
|
|
.PKT_CACHE_L (105),
|
|
.PKT_THREAD_ID_H (101),
|
|
.PKT_THREAD_ID_L (101),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.ST_DATA_W (114),
|
|
.ST_CHANNEL_W (34),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (3),
|
|
.BURSTWRAP_VALUE (7),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) nios2_dma_m_write_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (nios2_dma_m_write_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (nios2_dma_m_write_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (nios2_dma_m_write_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (nios2_dma_m_write_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (nios2_dma_m_write_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (nios2_dma_m_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (nios2_dma_m_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (nios2_dma_m_write_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (nios2_dma_m_write_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (nios2_dma_m_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (nios2_dma_m_write_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (nios2_dma_m_write_agent_cp_valid), // cp.valid
|
|
.cp_data (nios2_dma_m_write_agent_cp_data), // .data
|
|
.cp_startofpacket (nios2_dma_m_write_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (nios2_dma_m_write_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (nios2_dma_m_write_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_002_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_002_src_data), // .data
|
|
.rp_channel (rsp_mux_002_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_002_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_master_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_QOS_H (88),
|
|
.PKT_QOS_L (88),
|
|
.PKT_DATA_SIDEBAND_H (86),
|
|
.PKT_DATA_SIDEBAND_L (86),
|
|
.PKT_ADDR_SIDEBAND_H (85),
|
|
.PKT_ADDR_SIDEBAND_L (85),
|
|
.PKT_BURST_TYPE_H (84),
|
|
.PKT_BURST_TYPE_L (83),
|
|
.PKT_CACHE_H (108),
|
|
.PKT_CACHE_L (105),
|
|
.PKT_THREAD_ID_H (101),
|
|
.PKT_THREAD_ID_L (101),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_EXCLUSIVE (73),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.ST_DATA_W (114),
|
|
.ST_CHANNEL_W (34),
|
|
.AV_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_RSP (0),
|
|
.ID (1),
|
|
.BURSTWRAP_VALUE (3),
|
|
.CACHE_VALUE (0),
|
|
.SECURE_ACCESS_BIT (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0)
|
|
) nios2_cpu_instruction_master_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.av_address (nios2_cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
|
|
.av_write (nios2_cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
|
|
.av_read (nios2_cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
|
|
.av_writedata (nios2_cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
|
|
.av_readdata (nios2_cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
|
|
.av_waitrequest (nios2_cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
|
|
.av_readdatavalid (nios2_cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
|
|
.av_byteenable (nios2_cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
|
|
.av_burstcount (nios2_cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
|
|
.av_debugaccess (nios2_cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
|
|
.av_lock (nios2_cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
|
|
.cp_valid (nios2_cpu_instruction_master_agent_cp_valid), // cp.valid
|
|
.cp_data (nios2_cpu_instruction_master_agent_cp_data), // .data
|
|
.cp_startofpacket (nios2_cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
|
|
.cp_endofpacket (nios2_cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
|
|
.cp_ready (nios2_cpu_instruction_master_agent_cp_ready), // .ready
|
|
.rp_valid (rsp_mux_003_src_valid), // rp.valid
|
|
.rp_data (rsp_mux_003_src_data), // .data
|
|
.rp_channel (rsp_mux_003_src_channel), // .channel
|
|
.rp_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
|
|
.rp_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
|
|
.rp_ready (rsp_mux_003_src_ready), // .ready
|
|
.av_response (), // (terminated)
|
|
.av_writeresponsevalid () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) nios2_jtag_uart_avalon_jtag_slave_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (nios2_jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
|
|
.m0_burstcount (nios2_jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (nios2_jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (nios2_jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (nios2_jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
|
|
.m0_readdata (nios2_jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (nios2_jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (nios2_jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
|
|
.m0_waitrequest (nios2_jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (nios2_jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
|
|
.m0_write (nios2_jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
|
|
.rp_endofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (nios2_jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
|
|
.rp_valid (nios2_jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
|
|
.rp_data (nios2_jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
|
|
.rp_startofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_src_valid), // .valid
|
|
.cp_data (cmd_mux_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_src_channel), // .channel
|
|
.rf_sink_ready (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
|
|
.rdata_fifo_src_ready (nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
|
|
.in_valid (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
|
|
.in_ready (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) eth1_mdio_avalon_slave_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (eth1_mdio_avalon_slave_agent_m0_address), // m0.address
|
|
.m0_burstcount (eth1_mdio_avalon_slave_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (eth1_mdio_avalon_slave_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (eth1_mdio_avalon_slave_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (eth1_mdio_avalon_slave_agent_m0_lock), // .lock
|
|
.m0_readdata (eth1_mdio_avalon_slave_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (eth1_mdio_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (eth1_mdio_avalon_slave_agent_m0_read), // .read
|
|
.m0_waitrequest (eth1_mdio_avalon_slave_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (eth1_mdio_avalon_slave_agent_m0_writedata), // .writedata
|
|
.m0_write (eth1_mdio_avalon_slave_agent_m0_write), // .write
|
|
.rp_endofpacket (eth1_mdio_avalon_slave_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (eth1_mdio_avalon_slave_agent_rp_ready), // .ready
|
|
.rp_valid (eth1_mdio_avalon_slave_agent_rp_valid), // .valid
|
|
.rp_data (eth1_mdio_avalon_slave_agent_rp_data), // .data
|
|
.rp_startofpacket (eth1_mdio_avalon_slave_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_001_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_001_src_valid), // .valid
|
|
.cp_data (cmd_mux_001_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_001_src_channel), // .channel
|
|
.rf_sink_ready (eth1_mdio_avalon_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (eth1_mdio_avalon_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (eth1_mdio_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (eth1_mdio_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (eth1_mdio_avalon_slave_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (eth1_mdio_avalon_slave_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (eth1_mdio_avalon_slave_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (eth1_mdio_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (eth1_mdio_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (eth1_mdio_avalon_slave_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
|
|
.rdata_fifo_src_ready (eth1_mdio_avalon_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (eth1_mdio_avalon_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (eth1_mdio_avalon_slave_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) eth1_mdio_avalon_slave_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (eth1_mdio_avalon_slave_agent_rf_source_data), // in.data
|
|
.in_valid (eth1_mdio_avalon_slave_agent_rf_source_valid), // .valid
|
|
.in_ready (eth1_mdio_avalon_slave_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (eth1_mdio_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (eth1_mdio_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (eth1_mdio_avalon_slave_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (eth1_mdio_avalon_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (eth1_mdio_avalon_slave_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (eth1_mdio_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (eth1_mdio_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) eth0_mdio_avalon_slave_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (eth0_mdio_avalon_slave_agent_m0_address), // m0.address
|
|
.m0_burstcount (eth0_mdio_avalon_slave_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (eth0_mdio_avalon_slave_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (eth0_mdio_avalon_slave_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (eth0_mdio_avalon_slave_agent_m0_lock), // .lock
|
|
.m0_readdata (eth0_mdio_avalon_slave_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (eth0_mdio_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (eth0_mdio_avalon_slave_agent_m0_read), // .read
|
|
.m0_waitrequest (eth0_mdio_avalon_slave_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (eth0_mdio_avalon_slave_agent_m0_writedata), // .writedata
|
|
.m0_write (eth0_mdio_avalon_slave_agent_m0_write), // .write
|
|
.rp_endofpacket (eth0_mdio_avalon_slave_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (eth0_mdio_avalon_slave_agent_rp_ready), // .ready
|
|
.rp_valid (eth0_mdio_avalon_slave_agent_rp_valid), // .valid
|
|
.rp_data (eth0_mdio_avalon_slave_agent_rp_data), // .data
|
|
.rp_startofpacket (eth0_mdio_avalon_slave_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_002_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_002_src_valid), // .valid
|
|
.cp_data (cmd_mux_002_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_002_src_channel), // .channel
|
|
.rf_sink_ready (eth0_mdio_avalon_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (eth0_mdio_avalon_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (eth0_mdio_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (eth0_mdio_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (eth0_mdio_avalon_slave_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (eth0_mdio_avalon_slave_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (eth0_mdio_avalon_slave_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (eth0_mdio_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (eth0_mdio_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (eth0_mdio_avalon_slave_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
|
|
.rdata_fifo_src_ready (eth0_mdio_avalon_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (eth0_mdio_avalon_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (eth0_mdio_avalon_slave_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) eth0_mdio_avalon_slave_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (eth0_mdio_avalon_slave_agent_rf_source_data), // in.data
|
|
.in_valid (eth0_mdio_avalon_slave_agent_rf_source_valid), // .valid
|
|
.in_ready (eth0_mdio_avalon_slave_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (eth0_mdio_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (eth0_mdio_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (eth0_mdio_avalon_slave_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (eth0_mdio_avalon_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (eth0_mdio_avalon_slave_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (eth0_mdio_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (eth0_mdio_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (95),
|
|
.PKT_ORI_BURST_SIZE_L (93),
|
|
.PKT_RESPONSE_STATUS_H (92),
|
|
.PKT_RESPONSE_STATUS_L (91),
|
|
.PKT_BURST_SIZE_H (64),
|
|
.PKT_BURST_SIZE_L (62),
|
|
.PKT_TRANS_LOCK (54),
|
|
.PKT_BEGIN_BURST (69),
|
|
.PKT_PROTECTION_H (86),
|
|
.PKT_PROTECTION_L (84),
|
|
.PKT_BURSTWRAP_H (61),
|
|
.PKT_BURSTWRAP_L (59),
|
|
.PKT_BYTE_CNT_H (58),
|
|
.PKT_BYTE_CNT_L (56),
|
|
.PKT_ADDR_H (49),
|
|
.PKT_ADDR_L (18),
|
|
.PKT_TRANS_COMPRESSED_READ (50),
|
|
.PKT_TRANS_POSTED (51),
|
|
.PKT_TRANS_WRITE (52),
|
|
.PKT_TRANS_READ (53),
|
|
.PKT_DATA_H (15),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (17),
|
|
.PKT_BYTEEN_L (16),
|
|
.PKT_SRC_ID_H (76),
|
|
.PKT_SRC_ID_L (71),
|
|
.PKT_DEST_ID_H (82),
|
|
.PKT_DEST_ID_L (77),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (96),
|
|
.AVS_BURSTCOUNT_W (2),
|
|
.SUPPRESS_0_BYTEEN_CMD (1),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) sram_multiplexer_avl_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (sram_multiplexer_avl_agent_m0_address), // m0.address
|
|
.m0_burstcount (sram_multiplexer_avl_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (sram_multiplexer_avl_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (sram_multiplexer_avl_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (sram_multiplexer_avl_agent_m0_lock), // .lock
|
|
.m0_readdata (sram_multiplexer_avl_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (sram_multiplexer_avl_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (sram_multiplexer_avl_agent_m0_read), // .read
|
|
.m0_waitrequest (sram_multiplexer_avl_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (sram_multiplexer_avl_agent_m0_writedata), // .writedata
|
|
.m0_write (sram_multiplexer_avl_agent_m0_write), // .write
|
|
.rp_endofpacket (sram_multiplexer_avl_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (sram_multiplexer_avl_agent_rp_ready), // .ready
|
|
.rp_valid (sram_multiplexer_avl_agent_rp_valid), // .valid
|
|
.rp_data (sram_multiplexer_avl_agent_rp_data), // .data
|
|
.rp_startofpacket (sram_multiplexer_avl_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (sram_multiplexer_avl_burst_adapter_source0_ready), // cp.ready
|
|
.cp_valid (sram_multiplexer_avl_burst_adapter_source0_valid), // .valid
|
|
.cp_data (sram_multiplexer_avl_burst_adapter_source0_data), // .data
|
|
.cp_startofpacket (sram_multiplexer_avl_burst_adapter_source0_startofpacket), // .startofpacket
|
|
.cp_endofpacket (sram_multiplexer_avl_burst_adapter_source0_endofpacket), // .endofpacket
|
|
.cp_channel (sram_multiplexer_avl_burst_adapter_source0_channel), // .channel
|
|
.rf_sink_ready (sram_multiplexer_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (sram_multiplexer_avl_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (sram_multiplexer_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (sram_multiplexer_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (sram_multiplexer_avl_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (sram_multiplexer_avl_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (sram_multiplexer_avl_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (sram_multiplexer_avl_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (sram_multiplexer_avl_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (sram_multiplexer_avl_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
|
|
.rdata_fifo_src_ready (sram_multiplexer_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (sram_multiplexer_avl_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (sram_multiplexer_avl_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (97),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) sram_multiplexer_avl_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (sram_multiplexer_avl_agent_rf_source_data), // in.data
|
|
.in_valid (sram_multiplexer_avl_agent_rf_source_valid), // .valid
|
|
.in_ready (sram_multiplexer_avl_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (sram_multiplexer_avl_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (sram_multiplexer_avl_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (sram_multiplexer_avl_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (sram_multiplexer_avl_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (sram_multiplexer_avl_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (sram_multiplexer_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (sram_multiplexer_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_params_avl_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_params_avl_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_params_avl_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_params_avl_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_params_avl_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_params_avl_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_params_avl_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_params_avl_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_params_avl_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_params_avl_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_params_avl_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_params_avl_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_params_avl_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_params_avl_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_params_avl_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_params_avl_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_params_avl_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_004_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_004_src_valid), // .valid
|
|
.cp_data (cmd_mux_004_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_004_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_params_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_params_avl_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_params_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_params_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_params_avl_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_params_avl_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_params_avl_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_params_avl_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_params_avl_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_params_avl_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_params_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_params_avl_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_params_avl_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_params_avl_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_params_avl_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_params_avl_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_params_avl_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_params_avl_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_params_avl_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_params_avl_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_params_avl_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_params_avl_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_params_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_params_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) nios2_sysid_control_slave_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (nios2_sysid_control_slave_agent_m0_address), // m0.address
|
|
.m0_burstcount (nios2_sysid_control_slave_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (nios2_sysid_control_slave_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (nios2_sysid_control_slave_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (nios2_sysid_control_slave_agent_m0_lock), // .lock
|
|
.m0_readdata (nios2_sysid_control_slave_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (nios2_sysid_control_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (nios2_sysid_control_slave_agent_m0_read), // .read
|
|
.m0_waitrequest (nios2_sysid_control_slave_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (nios2_sysid_control_slave_agent_m0_writedata), // .writedata
|
|
.m0_write (nios2_sysid_control_slave_agent_m0_write), // .write
|
|
.rp_endofpacket (nios2_sysid_control_slave_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (nios2_sysid_control_slave_agent_rp_ready), // .ready
|
|
.rp_valid (nios2_sysid_control_slave_agent_rp_valid), // .valid
|
|
.rp_data (nios2_sysid_control_slave_agent_rp_data), // .data
|
|
.rp_startofpacket (nios2_sysid_control_slave_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_005_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_005_src_valid), // .valid
|
|
.cp_data (cmd_mux_005_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_005_src_channel), // .channel
|
|
.rf_sink_ready (nios2_sysid_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (nios2_sysid_control_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (nios2_sysid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (nios2_sysid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (nios2_sysid_control_slave_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (nios2_sysid_control_slave_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (nios2_sysid_control_slave_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (nios2_sysid_control_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (nios2_sysid_control_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (nios2_sysid_control_slave_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
|
|
.rdata_fifo_src_ready (nios2_sysid_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (nios2_sysid_control_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (nios2_sysid_control_slave_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) nios2_sysid_control_slave_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (nios2_sysid_control_slave_agent_rf_source_data), // in.data
|
|
.in_valid (nios2_sysid_control_slave_agent_rf_source_valid), // .valid
|
|
.in_ready (nios2_sysid_control_slave_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (nios2_sysid_control_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (nios2_sysid_control_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (nios2_sysid_control_slave_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (nios2_sysid_control_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (nios2_sysid_control_slave_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (nios2_sysid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (nios2_sysid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) eth0_rx_dma_csr_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (eth0_rx_dma_csr_agent_m0_address), // m0.address
|
|
.m0_burstcount (eth0_rx_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (eth0_rx_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (eth0_rx_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (eth0_rx_dma_csr_agent_m0_lock), // .lock
|
|
.m0_readdata (eth0_rx_dma_csr_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (eth0_rx_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (eth0_rx_dma_csr_agent_m0_read), // .read
|
|
.m0_waitrequest (eth0_rx_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (eth0_rx_dma_csr_agent_m0_writedata), // .writedata
|
|
.m0_write (eth0_rx_dma_csr_agent_m0_write), // .write
|
|
.rp_endofpacket (eth0_rx_dma_csr_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (eth0_rx_dma_csr_agent_rp_ready), // .ready
|
|
.rp_valid (eth0_rx_dma_csr_agent_rp_valid), // .valid
|
|
.rp_data (eth0_rx_dma_csr_agent_rp_data), // .data
|
|
.rp_startofpacket (eth0_rx_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_006_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_006_src_valid), // .valid
|
|
.cp_data (cmd_mux_006_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_006_src_channel), // .channel
|
|
.rf_sink_ready (eth0_rx_dma_csr_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (eth0_rx_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (eth0_rx_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (eth0_rx_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (eth0_rx_dma_csr_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (eth0_rx_dma_csr_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (eth0_rx_dma_csr_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (eth0_rx_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (eth0_rx_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (eth0_rx_dma_csr_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
|
|
.rdata_fifo_src_ready (eth0_rx_dma_csr_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (eth0_rx_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (eth0_rx_dma_csr_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) eth0_rx_dma_csr_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (eth0_rx_dma_csr_agent_rf_source_data), // in.data
|
|
.in_valid (eth0_rx_dma_csr_agent_rf_source_valid), // .valid
|
|
.in_ready (eth0_rx_dma_csr_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (eth0_rx_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (eth0_rx_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (eth0_rx_dma_csr_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (eth0_rx_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (eth0_rx_dma_csr_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (eth0_rx_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (eth0_rx_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) eth0_tx_dma_csr_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (eth0_tx_dma_csr_agent_m0_address), // m0.address
|
|
.m0_burstcount (eth0_tx_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (eth0_tx_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (eth0_tx_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (eth0_tx_dma_csr_agent_m0_lock), // .lock
|
|
.m0_readdata (eth0_tx_dma_csr_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (eth0_tx_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (eth0_tx_dma_csr_agent_m0_read), // .read
|
|
.m0_waitrequest (eth0_tx_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (eth0_tx_dma_csr_agent_m0_writedata), // .writedata
|
|
.m0_write (eth0_tx_dma_csr_agent_m0_write), // .write
|
|
.rp_endofpacket (eth0_tx_dma_csr_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (eth0_tx_dma_csr_agent_rp_ready), // .ready
|
|
.rp_valid (eth0_tx_dma_csr_agent_rp_valid), // .valid
|
|
.rp_data (eth0_tx_dma_csr_agent_rp_data), // .data
|
|
.rp_startofpacket (eth0_tx_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_007_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_007_src_valid), // .valid
|
|
.cp_data (cmd_mux_007_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_007_src_channel), // .channel
|
|
.rf_sink_ready (eth0_tx_dma_csr_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (eth0_tx_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (eth0_tx_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (eth0_tx_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (eth0_tx_dma_csr_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (eth0_tx_dma_csr_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (eth0_tx_dma_csr_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (eth0_tx_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (eth0_tx_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (eth0_tx_dma_csr_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error
|
|
.rdata_fifo_src_ready (eth0_tx_dma_csr_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (eth0_tx_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (eth0_tx_dma_csr_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) eth0_tx_dma_csr_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (eth0_tx_dma_csr_agent_rf_source_data), // in.data
|
|
.in_valid (eth0_tx_dma_csr_agent_rf_source_valid), // .valid
|
|
.in_ready (eth0_tx_dma_csr_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (eth0_tx_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (eth0_tx_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (eth0_tx_dma_csr_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (eth0_tx_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (eth0_tx_dma_csr_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (eth0_tx_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (eth0_tx_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) eth1_rx_dma_csr_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (eth1_rx_dma_csr_agent_m0_address), // m0.address
|
|
.m0_burstcount (eth1_rx_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (eth1_rx_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (eth1_rx_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (eth1_rx_dma_csr_agent_m0_lock), // .lock
|
|
.m0_readdata (eth1_rx_dma_csr_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (eth1_rx_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (eth1_rx_dma_csr_agent_m0_read), // .read
|
|
.m0_waitrequest (eth1_rx_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (eth1_rx_dma_csr_agent_m0_writedata), // .writedata
|
|
.m0_write (eth1_rx_dma_csr_agent_m0_write), // .write
|
|
.rp_endofpacket (eth1_rx_dma_csr_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (eth1_rx_dma_csr_agent_rp_ready), // .ready
|
|
.rp_valid (eth1_rx_dma_csr_agent_rp_valid), // .valid
|
|
.rp_data (eth1_rx_dma_csr_agent_rp_data), // .data
|
|
.rp_startofpacket (eth1_rx_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_008_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_008_src_valid), // .valid
|
|
.cp_data (cmd_mux_008_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_008_src_channel), // .channel
|
|
.rf_sink_ready (eth1_rx_dma_csr_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (eth1_rx_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (eth1_rx_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (eth1_rx_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (eth1_rx_dma_csr_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (eth1_rx_dma_csr_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (eth1_rx_dma_csr_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (eth1_rx_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (eth1_rx_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (eth1_rx_dma_csr_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_008_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_008_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_008_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_008_out_0_error), // .error
|
|
.rdata_fifo_src_ready (eth1_rx_dma_csr_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (eth1_rx_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (eth1_rx_dma_csr_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) eth1_rx_dma_csr_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (eth1_rx_dma_csr_agent_rf_source_data), // in.data
|
|
.in_valid (eth1_rx_dma_csr_agent_rf_source_valid), // .valid
|
|
.in_ready (eth1_rx_dma_csr_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (eth1_rx_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (eth1_rx_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (eth1_rx_dma_csr_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (eth1_rx_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (eth1_rx_dma_csr_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (eth1_rx_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (eth1_rx_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) eth1_tx_dma_csr_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (eth1_tx_dma_csr_agent_m0_address), // m0.address
|
|
.m0_burstcount (eth1_tx_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (eth1_tx_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (eth1_tx_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (eth1_tx_dma_csr_agent_m0_lock), // .lock
|
|
.m0_readdata (eth1_tx_dma_csr_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (eth1_tx_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (eth1_tx_dma_csr_agent_m0_read), // .read
|
|
.m0_waitrequest (eth1_tx_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (eth1_tx_dma_csr_agent_m0_writedata), // .writedata
|
|
.m0_write (eth1_tx_dma_csr_agent_m0_write), // .write
|
|
.rp_endofpacket (eth1_tx_dma_csr_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (eth1_tx_dma_csr_agent_rp_ready), // .ready
|
|
.rp_valid (eth1_tx_dma_csr_agent_rp_valid), // .valid
|
|
.rp_data (eth1_tx_dma_csr_agent_rp_data), // .data
|
|
.rp_startofpacket (eth1_tx_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_009_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_009_src_valid), // .valid
|
|
.cp_data (cmd_mux_009_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_009_src_channel), // .channel
|
|
.rf_sink_ready (eth1_tx_dma_csr_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (eth1_tx_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (eth1_tx_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (eth1_tx_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (eth1_tx_dma_csr_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (eth1_tx_dma_csr_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (eth1_tx_dma_csr_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (eth1_tx_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (eth1_tx_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (eth1_tx_dma_csr_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_009_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_009_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_009_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_009_out_0_error), // .error
|
|
.rdata_fifo_src_ready (eth1_tx_dma_csr_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (eth1_tx_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (eth1_tx_dma_csr_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) eth1_tx_dma_csr_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (eth1_tx_dma_csr_agent_rf_source_data), // in.data
|
|
.in_valid (eth1_tx_dma_csr_agent_rf_source_valid), // .valid
|
|
.in_ready (eth1_tx_dma_csr_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (eth1_tx_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (eth1_tx_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (eth1_tx_dma_csr_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (eth1_tx_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (eth1_tx_dma_csr_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (eth1_tx_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (eth1_tx_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) nios2_dma_csr_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (nios2_dma_csr_agent_m0_address), // m0.address
|
|
.m0_burstcount (nios2_dma_csr_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (nios2_dma_csr_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (nios2_dma_csr_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (nios2_dma_csr_agent_m0_lock), // .lock
|
|
.m0_readdata (nios2_dma_csr_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (nios2_dma_csr_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (nios2_dma_csr_agent_m0_read), // .read
|
|
.m0_waitrequest (nios2_dma_csr_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (nios2_dma_csr_agent_m0_writedata), // .writedata
|
|
.m0_write (nios2_dma_csr_agent_m0_write), // .write
|
|
.rp_endofpacket (nios2_dma_csr_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (nios2_dma_csr_agent_rp_ready), // .ready
|
|
.rp_valid (nios2_dma_csr_agent_rp_valid), // .valid
|
|
.rp_data (nios2_dma_csr_agent_rp_data), // .data
|
|
.rp_startofpacket (nios2_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_010_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_010_src_valid), // .valid
|
|
.cp_data (cmd_mux_010_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_010_src_channel), // .channel
|
|
.rf_sink_ready (nios2_dma_csr_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (nios2_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (nios2_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (nios2_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (nios2_dma_csr_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (nios2_dma_csr_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (nios2_dma_csr_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (nios2_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (nios2_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (nios2_dma_csr_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_010_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_010_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_010_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_010_out_0_error), // .error
|
|
.rdata_fifo_src_ready (nios2_dma_csr_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (nios2_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (nios2_dma_csr_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) nios2_dma_csr_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (nios2_dma_csr_agent_rf_source_data), // in.data
|
|
.in_valid (nios2_dma_csr_agent_rf_source_valid), // .valid
|
|
.in_ready (nios2_dma_csr_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (nios2_dma_csr_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (nios2_dma_csr_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (nios2_dma_csr_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (nios2_dma_csr_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (nios2_dma_csr_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (nios2_dma_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (nios2_dma_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) nios2_cpu_debug_mem_slave_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (nios2_cpu_debug_mem_slave_agent_m0_address), // m0.address
|
|
.m0_burstcount (nios2_cpu_debug_mem_slave_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (nios2_cpu_debug_mem_slave_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (nios2_cpu_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (nios2_cpu_debug_mem_slave_agent_m0_lock), // .lock
|
|
.m0_readdata (nios2_cpu_debug_mem_slave_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (nios2_cpu_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (nios2_cpu_debug_mem_slave_agent_m0_read), // .read
|
|
.m0_waitrequest (nios2_cpu_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (nios2_cpu_debug_mem_slave_agent_m0_writedata), // .writedata
|
|
.m0_write (nios2_cpu_debug_mem_slave_agent_m0_write), // .write
|
|
.rp_endofpacket (nios2_cpu_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (nios2_cpu_debug_mem_slave_agent_rp_ready), // .ready
|
|
.rp_valid (nios2_cpu_debug_mem_slave_agent_rp_valid), // .valid
|
|
.rp_data (nios2_cpu_debug_mem_slave_agent_rp_data), // .data
|
|
.rp_startofpacket (nios2_cpu_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_011_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_011_src_valid), // .valid
|
|
.cp_data (cmd_mux_011_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_011_src_channel), // .channel
|
|
.rf_sink_ready (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (nios2_cpu_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (nios2_cpu_debug_mem_slave_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (nios2_cpu_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (nios2_cpu_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (nios2_cpu_debug_mem_slave_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_011_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_011_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_011_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_011_out_0_error), // .error
|
|
.rdata_fifo_src_ready (nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) nios2_cpu_debug_mem_slave_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (nios2_cpu_debug_mem_slave_agent_rf_source_data), // in.data
|
|
.in_valid (nios2_cpu_debug_mem_slave_agent_rf_source_valid), // .valid
|
|
.in_ready (nios2_cpu_debug_mem_slave_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (nios2_cpu_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (nios2_cpu_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (nios2_cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) nios2_pll_pll_slave_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (nios2_pll_pll_slave_agent_m0_address), // m0.address
|
|
.m0_burstcount (nios2_pll_pll_slave_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (nios2_pll_pll_slave_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (nios2_pll_pll_slave_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (nios2_pll_pll_slave_agent_m0_lock), // .lock
|
|
.m0_readdata (nios2_pll_pll_slave_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (nios2_pll_pll_slave_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (nios2_pll_pll_slave_agent_m0_read), // .read
|
|
.m0_waitrequest (nios2_pll_pll_slave_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (nios2_pll_pll_slave_agent_m0_writedata), // .writedata
|
|
.m0_write (nios2_pll_pll_slave_agent_m0_write), // .write
|
|
.rp_endofpacket (nios2_pll_pll_slave_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (nios2_pll_pll_slave_agent_rp_ready), // .ready
|
|
.rp_valid (nios2_pll_pll_slave_agent_rp_valid), // .valid
|
|
.rp_data (nios2_pll_pll_slave_agent_rp_data), // .data
|
|
.rp_startofpacket (nios2_pll_pll_slave_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_012_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_012_src_valid), // .valid
|
|
.cp_data (cmd_mux_012_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_012_src_channel), // .channel
|
|
.rf_sink_ready (nios2_pll_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (nios2_pll_pll_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (nios2_pll_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (nios2_pll_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (nios2_pll_pll_slave_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (nios2_pll_pll_slave_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (nios2_pll_pll_slave_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (nios2_pll_pll_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (nios2_pll_pll_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (nios2_pll_pll_slave_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_012_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_012_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_012_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_012_out_0_error), // .error
|
|
.rdata_fifo_src_ready (nios2_pll_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (nios2_pll_pll_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (nios2_pll_pll_slave_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) nios2_pll_pll_slave_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (nios2_pll_pll_slave_agent_rf_source_data), // in.data
|
|
.in_valid (nios2_pll_pll_slave_agent_rf_source_valid), // .valid
|
|
.in_ready (nios2_pll_pll_slave_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (nios2_pll_pll_slave_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (nios2_pll_pll_slave_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (nios2_pll_pll_slave_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (nios2_pll_pll_slave_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (nios2_pll_pll_slave_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (nios2_pll_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (nios2_pll_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) nios2_onchip_mem_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (nios2_onchip_mem_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (nios2_onchip_mem_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (nios2_onchip_mem_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (nios2_onchip_mem_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (nios2_onchip_mem_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (nios2_onchip_mem_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (nios2_onchip_mem_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (nios2_onchip_mem_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (nios2_onchip_mem_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (nios2_onchip_mem_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (nios2_onchip_mem_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (nios2_onchip_mem_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (nios2_onchip_mem_s1_agent_rp_ready), // .ready
|
|
.rp_valid (nios2_onchip_mem_s1_agent_rp_valid), // .valid
|
|
.rp_data (nios2_onchip_mem_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (nios2_onchip_mem_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_013_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_013_src_valid), // .valid
|
|
.cp_data (cmd_mux_013_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_013_src_channel), // .channel
|
|
.rf_sink_ready (nios2_onchip_mem_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (nios2_onchip_mem_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (nios2_onchip_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (nios2_onchip_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (nios2_onchip_mem_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (nios2_onchip_mem_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (nios2_onchip_mem_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (nios2_onchip_mem_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (nios2_onchip_mem_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (nios2_onchip_mem_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_013_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_013_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_013_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_013_out_0_error), // .error
|
|
.rdata_fifo_src_ready (nios2_onchip_mem_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (nios2_onchip_mem_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (nios2_onchip_mem_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) nios2_onchip_mem_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (nios2_onchip_mem_s1_agent_rf_source_data), // in.data
|
|
.in_valid (nios2_onchip_mem_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (nios2_onchip_mem_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (nios2_onchip_mem_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (nios2_onchip_mem_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (nios2_onchip_mem_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (nios2_onchip_mem_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (nios2_onchip_mem_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (nios2_onchip_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (nios2_onchip_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) sdram_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (sdram_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (sdram_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (sdram_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (sdram_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (sdram_s1_agent_rp_ready), // .ready
|
|
.rp_valid (sdram_s1_agent_rp_valid), // .valid
|
|
.rp_data (sdram_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_014_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_014_src_valid), // .valid
|
|
.cp_data (cmd_mux_014_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_014_src_channel), // .channel
|
|
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_014_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_014_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_014_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_014_out_0_error), // .error
|
|
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (8),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) sdram_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (sdram_s1_agent_rf_source_data), // in.data
|
|
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) io_led_red_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (io_led_red_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (io_led_red_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (io_led_red_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (io_led_red_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (io_led_red_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (io_led_red_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (io_led_red_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (io_led_red_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (io_led_red_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (io_led_red_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (io_led_red_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (io_led_red_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (io_led_red_s1_agent_rp_ready), // .ready
|
|
.rp_valid (io_led_red_s1_agent_rp_valid), // .valid
|
|
.rp_data (io_led_red_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (io_led_red_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_015_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_015_src_valid), // .valid
|
|
.cp_data (cmd_mux_015_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_015_src_channel), // .channel
|
|
.rf_sink_ready (io_led_red_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (io_led_red_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (io_led_red_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (io_led_red_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (io_led_red_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (io_led_red_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (io_led_red_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (io_led_red_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (io_led_red_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (io_led_red_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_015_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_015_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_015_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_015_out_0_error), // .error
|
|
.rdata_fifo_src_ready (io_led_red_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (io_led_red_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (io_led_red_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) io_led_red_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (io_led_red_s1_agent_rf_source_data), // in.data
|
|
.in_valid (io_led_red_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (io_led_red_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (io_led_red_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (io_led_red_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (io_led_red_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (io_led_red_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (io_led_red_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (io_led_red_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (io_led_red_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) nios2_timer_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (nios2_timer_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (nios2_timer_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (nios2_timer_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (nios2_timer_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (nios2_timer_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (nios2_timer_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (nios2_timer_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (nios2_timer_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (nios2_timer_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (nios2_timer_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (nios2_timer_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (nios2_timer_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (nios2_timer_s1_agent_rp_ready), // .ready
|
|
.rp_valid (nios2_timer_s1_agent_rp_valid), // .valid
|
|
.rp_data (nios2_timer_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (nios2_timer_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_016_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_016_src_valid), // .valid
|
|
.cp_data (cmd_mux_016_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_016_src_channel), // .channel
|
|
.rf_sink_ready (nios2_timer_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (nios2_timer_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (nios2_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (nios2_timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (nios2_timer_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (nios2_timer_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (nios2_timer_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (nios2_timer_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (nios2_timer_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (nios2_timer_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_016_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_016_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_016_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_016_out_0_error), // .error
|
|
.rdata_fifo_src_ready (nios2_timer_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (nios2_timer_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (nios2_timer_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) nios2_timer_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (nios2_timer_s1_agent_rf_source_data), // in.data
|
|
.in_valid (nios2_timer_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (nios2_timer_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (nios2_timer_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (nios2_timer_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (nios2_timer_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (nios2_timer_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (nios2_timer_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (nios2_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (nios2_timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) io_keys_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (io_keys_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (io_keys_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (io_keys_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (io_keys_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (io_keys_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (io_keys_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (io_keys_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (io_keys_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (io_keys_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (io_keys_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (io_keys_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (io_keys_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (io_keys_s1_agent_rp_ready), // .ready
|
|
.rp_valid (io_keys_s1_agent_rp_valid), // .valid
|
|
.rp_data (io_keys_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (io_keys_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_017_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_017_src_valid), // .valid
|
|
.cp_data (cmd_mux_017_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_017_src_channel), // .channel
|
|
.rf_sink_ready (io_keys_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (io_keys_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (io_keys_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (io_keys_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (io_keys_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (io_keys_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (io_keys_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (io_keys_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (io_keys_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (io_keys_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_017_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_017_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_017_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_017_out_0_error), // .error
|
|
.rdata_fifo_src_ready (io_keys_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (io_keys_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (io_keys_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) io_keys_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (io_keys_s1_agent_rf_source_data), // in.data
|
|
.in_valid (io_keys_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (io_keys_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (io_keys_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (io_keys_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (io_keys_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (io_keys_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (io_keys_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (io_keys_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (io_keys_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) io_switches_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (io_switches_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (io_switches_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (io_switches_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (io_switches_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (io_switches_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (io_switches_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (io_switches_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (io_switches_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (io_switches_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (io_switches_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (io_switches_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (io_switches_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (io_switches_s1_agent_rp_ready), // .ready
|
|
.rp_valid (io_switches_s1_agent_rp_valid), // .valid
|
|
.rp_data (io_switches_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (io_switches_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_018_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_018_src_valid), // .valid
|
|
.cp_data (cmd_mux_018_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_018_src_channel), // .channel
|
|
.rf_sink_ready (io_switches_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (io_switches_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (io_switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (io_switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (io_switches_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (io_switches_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (io_switches_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (io_switches_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (io_switches_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (io_switches_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_018_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_018_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_018_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_018_out_0_error), // .error
|
|
.rdata_fifo_src_ready (io_switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (io_switches_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (io_switches_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) io_switches_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (io_switches_s1_agent_rf_source_data), // in.data
|
|
.in_valid (io_switches_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (io_switches_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (io_switches_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (io_switches_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (io_switches_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (io_switches_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (io_switches_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (io_switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (io_switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) io_led_green_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (io_led_green_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (io_led_green_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (io_led_green_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (io_led_green_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (io_led_green_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (io_led_green_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (io_led_green_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (io_led_green_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (io_led_green_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (io_led_green_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (io_led_green_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (io_led_green_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (io_led_green_s1_agent_rp_ready), // .ready
|
|
.rp_valid (io_led_green_s1_agent_rp_valid), // .valid
|
|
.rp_data (io_led_green_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (io_led_green_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_019_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_019_src_valid), // .valid
|
|
.cp_data (cmd_mux_019_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_019_src_channel), // .channel
|
|
.rf_sink_ready (io_led_green_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (io_led_green_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (io_led_green_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (io_led_green_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (io_led_green_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (io_led_green_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (io_led_green_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (io_led_green_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (io_led_green_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (io_led_green_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_019_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_019_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_019_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_019_out_0_error), // .error
|
|
.rdata_fifo_src_ready (io_led_green_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (io_led_green_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (io_led_green_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) io_led_green_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (io_led_green_s1_agent_rf_source_data), // in.data
|
|
.in_valid (io_led_green_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (io_led_green_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (io_led_green_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (io_led_green_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (io_led_green_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (io_led_green_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (io_led_green_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (io_led_green_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (io_led_green_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) io_hex_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (io_hex_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (io_hex_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (io_hex_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (io_hex_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (io_hex_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (io_hex_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (io_hex_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (io_hex_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (io_hex_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (io_hex_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (io_hex_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (io_hex_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (io_hex_s1_agent_rp_ready), // .ready
|
|
.rp_valid (io_hex_s1_agent_rp_valid), // .valid
|
|
.rp_data (io_hex_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (io_hex_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_020_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_020_src_valid), // .valid
|
|
.cp_data (cmd_mux_020_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_020_src_channel), // .channel
|
|
.rf_sink_ready (io_hex_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (io_hex_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (io_hex_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (io_hex_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (io_hex_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (io_hex_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (io_hex_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (io_hex_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (io_hex_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (io_hex_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_020_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_020_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_020_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_020_out_0_error), // .error
|
|
.rdata_fifo_src_ready (io_hex_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (io_hex_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (io_hex_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) io_hex_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (io_hex_s1_agent_rf_source_data), // in.data
|
|
.in_valid (io_hex_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (io_hex_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (io_hex_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (io_hex_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (io_hex_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (io_hex_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (io_hex_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (io_hex_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (io_hex_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_0_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_0_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_0_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_0_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_0_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_0_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_0_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_0_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_0_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_0_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_0_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_0_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_0_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_0_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_0_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_0_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_0_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_021_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_021_src_valid), // .valid
|
|
.cp_data (cmd_mux_021_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_021_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_0_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_0_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_0_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_0_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_0_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_0_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_0_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_021_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_021_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_021_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_021_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_0_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_0_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_0_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_0_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_0_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_0_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_0_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_0_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_0_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_0_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_0_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_1_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_1_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_1_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_1_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_1_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_1_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_1_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_1_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_1_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_1_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_1_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_1_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_1_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_1_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_1_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_1_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_1_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_022_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_022_src_valid), // .valid
|
|
.cp_data (cmd_mux_022_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_022_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_1_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_1_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_1_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_1_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_1_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_1_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_1_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_022_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_022_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_022_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_022_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_1_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_1_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_1_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_1_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_1_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_1_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_1_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_1_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_1_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_1_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_1_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_2_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_2_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_2_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_2_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_2_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_2_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_2_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_2_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_2_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_2_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_2_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_2_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_2_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_2_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_2_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_2_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_2_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_023_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_023_src_valid), // .valid
|
|
.cp_data (cmd_mux_023_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_023_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_023_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_023_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_2_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_2_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_2_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_2_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_2_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_2_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_2_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_023_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_023_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_023_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_023_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_2_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_2_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_2_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_2_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_2_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_2_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_2_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_2_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_2_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_2_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_2_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_3_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_3_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_3_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_3_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_3_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_3_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_3_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_3_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_3_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_3_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_3_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_3_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_3_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_3_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_3_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_3_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_3_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_024_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_024_src_valid), // .valid
|
|
.cp_data (cmd_mux_024_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_024_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_024_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_024_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_3_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_3_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_3_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_3_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_3_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_3_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_3_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_3_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_024_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_024_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_024_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_024_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_3_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_3_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_3_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_3_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_3_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_3_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_3_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_3_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_3_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_3_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_3_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) io_vga_sync_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (io_vga_sync_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (io_vga_sync_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (io_vga_sync_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (io_vga_sync_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (io_vga_sync_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (io_vga_sync_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (io_vga_sync_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (io_vga_sync_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (io_vga_sync_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (io_vga_sync_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (io_vga_sync_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (io_vga_sync_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (io_vga_sync_s1_agent_rp_ready), // .ready
|
|
.rp_valid (io_vga_sync_s1_agent_rp_valid), // .valid
|
|
.rp_data (io_vga_sync_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (io_vga_sync_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_025_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_025_src_valid), // .valid
|
|
.cp_data (cmd_mux_025_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_025_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_025_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_025_src_channel), // .channel
|
|
.rf_sink_ready (io_vga_sync_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (io_vga_sync_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (io_vga_sync_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (io_vga_sync_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (io_vga_sync_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (io_vga_sync_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (io_vga_sync_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (io_vga_sync_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (io_vga_sync_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (io_vga_sync_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_025_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_025_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_025_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_025_out_0_error), // .error
|
|
.rdata_fifo_src_ready (io_vga_sync_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (io_vga_sync_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (io_vga_sync_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) io_vga_sync_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (io_vga_sync_s1_agent_rf_source_data), // in.data
|
|
.in_valid (io_vga_sync_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (io_vga_sync_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (io_vga_sync_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (io_vga_sync_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (io_vga_sync_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (io_vga_sync_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (io_vga_sync_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (io_vga_sync_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (io_vga_sync_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_4_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_4_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_4_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_4_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_4_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_4_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_4_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_4_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_4_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_4_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_4_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_4_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_4_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_4_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_4_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_4_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_4_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_026_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_026_src_valid), // .valid
|
|
.cp_data (cmd_mux_026_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_026_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_026_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_026_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_4_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_4_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_4_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_4_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_4_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_4_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_4_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_4_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_026_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_026_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_026_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_026_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_4_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_4_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_4_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_4_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_4_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_4_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_4_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_4_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_4_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_4_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_4_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_4_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_5_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_5_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_5_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_5_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_5_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_5_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_5_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_5_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_5_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_5_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_5_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_5_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_5_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_5_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_5_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_5_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_5_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_027_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_027_src_valid), // .valid
|
|
.cp_data (cmd_mux_027_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_027_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_027_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_027_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_5_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_5_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_5_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_5_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_5_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_5_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_5_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_5_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_027_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_027_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_027_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_027_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_5_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_5_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_5_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_5_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_5_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_5_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_5_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_5_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_5_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_5_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_5_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_5_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_6_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_6_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_6_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_6_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_6_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_6_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_6_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_6_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_6_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_6_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_6_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_6_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_6_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_6_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_6_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_6_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_6_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_028_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_028_src_valid), // .valid
|
|
.cp_data (cmd_mux_028_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_028_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_028_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_028_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_6_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_6_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_6_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_6_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_6_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_6_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_6_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_6_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_6_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_6_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_028_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_028_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_028_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_028_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_6_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_6_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_6_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_6_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_6_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_6_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_6_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_6_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_6_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_6_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_6_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_6_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_6_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_6_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_sprite_7_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_sprite_7_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_sprite_7_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_sprite_7_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_sprite_7_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_sprite_7_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_sprite_7_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_sprite_7_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_sprite_7_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_sprite_7_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_sprite_7_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_sprite_7_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_sprite_7_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_sprite_7_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_sprite_7_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_sprite_7_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_sprite_7_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_029_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_029_src_valid), // .valid
|
|
.cp_data (cmd_mux_029_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_029_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_029_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_029_src_channel), // .channel
|
|
.rf_sink_ready (vga_sprite_7_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_sprite_7_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_sprite_7_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_sprite_7_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_sprite_7_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_sprite_7_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_sprite_7_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_sprite_7_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_sprite_7_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_sprite_7_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_029_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_029_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_029_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_029_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_sprite_7_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_sprite_7_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_sprite_7_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_sprite_7_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_sprite_7_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_sprite_7_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_sprite_7_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_sprite_7_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_sprite_7_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_sprite_7_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_sprite_7_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_sprite_7_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_sprite_7_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_sprite_7_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) vga_background_offset_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (vga_background_offset_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (vga_background_offset_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (vga_background_offset_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (vga_background_offset_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (vga_background_offset_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (vga_background_offset_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (vga_background_offset_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (vga_background_offset_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (vga_background_offset_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (vga_background_offset_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (vga_background_offset_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (vga_background_offset_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (vga_background_offset_s1_agent_rp_ready), // .ready
|
|
.rp_valid (vga_background_offset_s1_agent_rp_valid), // .valid
|
|
.rp_data (vga_background_offset_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (vga_background_offset_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_030_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_030_src_valid), // .valid
|
|
.cp_data (cmd_mux_030_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_030_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_030_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_030_src_channel), // .channel
|
|
.rf_sink_ready (vga_background_offset_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (vga_background_offset_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (vga_background_offset_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (vga_background_offset_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (vga_background_offset_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (vga_background_offset_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (vga_background_offset_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (vga_background_offset_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (vga_background_offset_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (vga_background_offset_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_030_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_030_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_030_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_030_out_0_error), // .error
|
|
.rdata_fifo_src_ready (vga_background_offset_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (vga_background_offset_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (vga_background_offset_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) vga_background_offset_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (vga_background_offset_s1_agent_rf_source_data), // in.data
|
|
.in_valid (vga_background_offset_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (vga_background_offset_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (vga_background_offset_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (vga_background_offset_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (vga_background_offset_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (vga_background_offset_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (vga_background_offset_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (vga_background_offset_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (vga_background_offset_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) audio_pio_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (audio_pio_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (audio_pio_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (audio_pio_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (audio_pio_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (audio_pio_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (audio_pio_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (audio_pio_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (audio_pio_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (audio_pio_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (audio_pio_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (audio_pio_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (audio_pio_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (audio_pio_s1_agent_rp_ready), // .ready
|
|
.rp_valid (audio_pio_s1_agent_rp_valid), // .valid
|
|
.rp_data (audio_pio_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (audio_pio_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_031_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_031_src_valid), // .valid
|
|
.cp_data (cmd_mux_031_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_031_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_031_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_031_src_channel), // .channel
|
|
.rf_sink_ready (audio_pio_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (audio_pio_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (audio_pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (audio_pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (audio_pio_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (audio_pio_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (audio_pio_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (audio_pio_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (audio_pio_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (audio_pio_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_031_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_031_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_031_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_031_out_0_error), // .error
|
|
.rdata_fifo_src_ready (audio_pio_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (audio_pio_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (audio_pio_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) audio_pio_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (audio_pio_s1_agent_rf_source_data), // in.data
|
|
.in_valid (audio_pio_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (audio_pio_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (audio_pio_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (audio_pio_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (audio_pio_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (audio_pio_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (audio_pio_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (audio_pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (audio_pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) audio_timer_s1_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (audio_timer_s1_agent_m0_address), // m0.address
|
|
.m0_burstcount (audio_timer_s1_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (audio_timer_s1_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (audio_timer_s1_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (audio_timer_s1_agent_m0_lock), // .lock
|
|
.m0_readdata (audio_timer_s1_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (audio_timer_s1_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (audio_timer_s1_agent_m0_read), // .read
|
|
.m0_waitrequest (audio_timer_s1_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (audio_timer_s1_agent_m0_writedata), // .writedata
|
|
.m0_write (audio_timer_s1_agent_m0_write), // .write
|
|
.rp_endofpacket (audio_timer_s1_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (audio_timer_s1_agent_rp_ready), // .ready
|
|
.rp_valid (audio_timer_s1_agent_rp_valid), // .valid
|
|
.rp_data (audio_timer_s1_agent_rp_data), // .data
|
|
.rp_startofpacket (audio_timer_s1_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_032_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_032_src_valid), // .valid
|
|
.cp_data (cmd_mux_032_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_032_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_032_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_032_src_channel), // .channel
|
|
.rf_sink_ready (audio_timer_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (audio_timer_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (audio_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (audio_timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (audio_timer_s1_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (audio_timer_s1_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (audio_timer_s1_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (audio_timer_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (audio_timer_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (audio_timer_s1_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_032_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_032_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_032_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_032_out_0_error), // .error
|
|
.rdata_fifo_src_ready (audio_timer_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (audio_timer_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (audio_timer_s1_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) audio_timer_s1_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (audio_timer_s1_agent_rf_source_data), // in.data
|
|
.in_valid (audio_timer_s1_agent_rf_source_valid), // .valid
|
|
.in_ready (audio_timer_s1_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (audio_timer_s1_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (audio_timer_s1_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (audio_timer_s1_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (audio_timer_s1_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (audio_timer_s1_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (audio_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (audio_timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
altera_merlin_slave_agent #(
|
|
.PKT_ORI_BURST_SIZE_H (113),
|
|
.PKT_ORI_BURST_SIZE_L (111),
|
|
.PKT_RESPONSE_STATUS_H (110),
|
|
.PKT_RESPONSE_STATUS_L (109),
|
|
.PKT_BURST_SIZE_H (82),
|
|
.PKT_BURST_SIZE_L (80),
|
|
.PKT_TRANS_LOCK (72),
|
|
.PKT_BEGIN_BURST (87),
|
|
.PKT_PROTECTION_H (104),
|
|
.PKT_PROTECTION_L (102),
|
|
.PKT_BURSTWRAP_H (79),
|
|
.PKT_BURSTWRAP_L (77),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_ADDR_H (67),
|
|
.PKT_ADDR_L (36),
|
|
.PKT_TRANS_COMPRESSED_READ (68),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.PKT_TRANS_READ (71),
|
|
.PKT_DATA_H (31),
|
|
.PKT_DATA_L (0),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SYMBOL_W (8),
|
|
.ST_CHANNEL_W (34),
|
|
.ST_DATA_W (114),
|
|
.AVS_BURSTCOUNT_W (3),
|
|
.SUPPRESS_0_BYTEEN_CMD (0),
|
|
.PREVENT_FIFO_OVERFLOW (1),
|
|
.USE_READRESPONSE (0),
|
|
.USE_WRITERESPONSE (0),
|
|
.ECC_ENABLE (0)
|
|
) usb_keycode_s2_agent (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.m0_address (usb_keycode_s2_agent_m0_address), // m0.address
|
|
.m0_burstcount (usb_keycode_s2_agent_m0_burstcount), // .burstcount
|
|
.m0_byteenable (usb_keycode_s2_agent_m0_byteenable), // .byteenable
|
|
.m0_debugaccess (usb_keycode_s2_agent_m0_debugaccess), // .debugaccess
|
|
.m0_lock (usb_keycode_s2_agent_m0_lock), // .lock
|
|
.m0_readdata (usb_keycode_s2_agent_m0_readdata), // .readdata
|
|
.m0_readdatavalid (usb_keycode_s2_agent_m0_readdatavalid), // .readdatavalid
|
|
.m0_read (usb_keycode_s2_agent_m0_read), // .read
|
|
.m0_waitrequest (usb_keycode_s2_agent_m0_waitrequest), // .waitrequest
|
|
.m0_writedata (usb_keycode_s2_agent_m0_writedata), // .writedata
|
|
.m0_write (usb_keycode_s2_agent_m0_write), // .write
|
|
.rp_endofpacket (usb_keycode_s2_agent_rp_endofpacket), // rp.endofpacket
|
|
.rp_ready (usb_keycode_s2_agent_rp_ready), // .ready
|
|
.rp_valid (usb_keycode_s2_agent_rp_valid), // .valid
|
|
.rp_data (usb_keycode_s2_agent_rp_data), // .data
|
|
.rp_startofpacket (usb_keycode_s2_agent_rp_startofpacket), // .startofpacket
|
|
.cp_ready (cmd_mux_033_src_ready), // cp.ready
|
|
.cp_valid (cmd_mux_033_src_valid), // .valid
|
|
.cp_data (cmd_mux_033_src_data), // .data
|
|
.cp_startofpacket (cmd_mux_033_src_startofpacket), // .startofpacket
|
|
.cp_endofpacket (cmd_mux_033_src_endofpacket), // .endofpacket
|
|
.cp_channel (cmd_mux_033_src_channel), // .channel
|
|
.rf_sink_ready (usb_keycode_s2_agent_rsp_fifo_out_ready), // rf_sink.ready
|
|
.rf_sink_valid (usb_keycode_s2_agent_rsp_fifo_out_valid), // .valid
|
|
.rf_sink_startofpacket (usb_keycode_s2_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.rf_sink_endofpacket (usb_keycode_s2_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.rf_sink_data (usb_keycode_s2_agent_rsp_fifo_out_data), // .data
|
|
.rf_source_ready (usb_keycode_s2_agent_rf_source_ready), // rf_source.ready
|
|
.rf_source_valid (usb_keycode_s2_agent_rf_source_valid), // .valid
|
|
.rf_source_startofpacket (usb_keycode_s2_agent_rf_source_startofpacket), // .startofpacket
|
|
.rf_source_endofpacket (usb_keycode_s2_agent_rf_source_endofpacket), // .endofpacket
|
|
.rf_source_data (usb_keycode_s2_agent_rf_source_data), // .data
|
|
.rdata_fifo_sink_ready (avalon_st_adapter_033_out_0_ready), // rdata_fifo_sink.ready
|
|
.rdata_fifo_sink_valid (avalon_st_adapter_033_out_0_valid), // .valid
|
|
.rdata_fifo_sink_data (avalon_st_adapter_033_out_0_data), // .data
|
|
.rdata_fifo_sink_error (avalon_st_adapter_033_out_0_error), // .error
|
|
.rdata_fifo_src_ready (usb_keycode_s2_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
|
|
.rdata_fifo_src_valid (usb_keycode_s2_agent_rdata_fifo_src_valid), // .valid
|
|
.rdata_fifo_src_data (usb_keycode_s2_agent_rdata_fifo_src_data), // .data
|
|
.m0_response (2'b00), // (terminated)
|
|
.m0_writeresponsevalid (1'b0) // (terminated)
|
|
);
|
|
|
|
altera_avalon_sc_fifo #(
|
|
.SYMBOLS_PER_BEAT (1),
|
|
.BITS_PER_SYMBOL (115),
|
|
.FIFO_DEPTH (2),
|
|
.CHANNEL_WIDTH (0),
|
|
.ERROR_WIDTH (0),
|
|
.USE_PACKETS (1),
|
|
.USE_FILL_LEVEL (0),
|
|
.EMPTY_LATENCY (1),
|
|
.USE_MEMORY_BLOCKS (0),
|
|
.USE_STORE_FORWARD (0),
|
|
.USE_ALMOST_FULL_IF (0),
|
|
.USE_ALMOST_EMPTY_IF (0)
|
|
) usb_keycode_s2_agent_rsp_fifo (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_data (usb_keycode_s2_agent_rf_source_data), // in.data
|
|
.in_valid (usb_keycode_s2_agent_rf_source_valid), // .valid
|
|
.in_ready (usb_keycode_s2_agent_rf_source_ready), // .ready
|
|
.in_startofpacket (usb_keycode_s2_agent_rf_source_startofpacket), // .startofpacket
|
|
.in_endofpacket (usb_keycode_s2_agent_rf_source_endofpacket), // .endofpacket
|
|
.out_data (usb_keycode_s2_agent_rsp_fifo_out_data), // out.data
|
|
.out_valid (usb_keycode_s2_agent_rsp_fifo_out_valid), // .valid
|
|
.out_ready (usb_keycode_s2_agent_rsp_fifo_out_ready), // .ready
|
|
.out_startofpacket (usb_keycode_s2_agent_rsp_fifo_out_startofpacket), // .startofpacket
|
|
.out_endofpacket (usb_keycode_s2_agent_rsp_fifo_out_endofpacket), // .endofpacket
|
|
.csr_address (2'b00), // (terminated)
|
|
.csr_read (1'b0), // (terminated)
|
|
.csr_write (1'b0), // (terminated)
|
|
.csr_readdata (), // (terminated)
|
|
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
|
.almost_full_data (), // (terminated)
|
|
.almost_empty_data (), // (terminated)
|
|
.in_empty (1'b0), // (terminated)
|
|
.out_empty (), // (terminated)
|
|
.in_error (1'b0), // (terminated)
|
|
.out_error (), // (terminated)
|
|
.in_channel (1'b0), // (terminated)
|
|
.out_channel () // (terminated)
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router router (
|
|
.sink_ready (nios2_cpu_data_master_agent_cp_ready), // sink.ready
|
|
.sink_valid (nios2_cpu_data_master_agent_cp_valid), // .valid
|
|
.sink_data (nios2_cpu_data_master_agent_cp_data), // .data
|
|
.sink_startofpacket (nios2_cpu_data_master_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_cpu_data_master_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_src_ready), // src.ready
|
|
.src_valid (router_src_valid), // .valid
|
|
.src_data (router_src_data), // .data
|
|
.src_channel (router_src_channel), // .channel
|
|
.src_startofpacket (router_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_001 router_001 (
|
|
.sink_ready (nios2_dma_m_read_agent_cp_ready), // sink.ready
|
|
.sink_valid (nios2_dma_m_read_agent_cp_valid), // .valid
|
|
.sink_data (nios2_dma_m_read_agent_cp_data), // .data
|
|
.sink_startofpacket (nios2_dma_m_read_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_dma_m_read_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_001_src_ready), // src.ready
|
|
.src_valid (router_001_src_valid), // .valid
|
|
.src_data (router_001_src_data), // .data
|
|
.src_channel (router_001_src_channel), // .channel
|
|
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_002 router_002 (
|
|
.sink_ready (nios2_dma_m_write_agent_cp_ready), // sink.ready
|
|
.sink_valid (nios2_dma_m_write_agent_cp_valid), // .valid
|
|
.sink_data (nios2_dma_m_write_agent_cp_data), // .data
|
|
.sink_startofpacket (nios2_dma_m_write_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_dma_m_write_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_002_src_ready), // src.ready
|
|
.src_valid (router_002_src_valid), // .valid
|
|
.src_data (router_002_src_data), // .data
|
|
.src_channel (router_002_src_channel), // .channel
|
|
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_003 router_003 (
|
|
.sink_ready (nios2_cpu_instruction_master_agent_cp_ready), // sink.ready
|
|
.sink_valid (nios2_cpu_instruction_master_agent_cp_valid), // .valid
|
|
.sink_data (nios2_cpu_instruction_master_agent_cp_data), // .data
|
|
.sink_startofpacket (nios2_cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_003_src_ready), // src.ready
|
|
.src_valid (router_003_src_valid), // .valid
|
|
.src_data (router_003_src_data), // .data
|
|
.src_channel (router_003_src_channel), // .channel
|
|
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_004 (
|
|
.sink_ready (nios2_jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
|
|
.sink_valid (nios2_jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
|
|
.sink_data (nios2_jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
|
|
.sink_startofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_004_src_ready), // src.ready
|
|
.src_valid (router_004_src_valid), // .valid
|
|
.src_data (router_004_src_data), // .data
|
|
.src_channel (router_004_src_channel), // .channel
|
|
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_005 (
|
|
.sink_ready (eth1_mdio_avalon_slave_agent_rp_ready), // sink.ready
|
|
.sink_valid (eth1_mdio_avalon_slave_agent_rp_valid), // .valid
|
|
.sink_data (eth1_mdio_avalon_slave_agent_rp_data), // .data
|
|
.sink_startofpacket (eth1_mdio_avalon_slave_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_mdio_avalon_slave_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_005_src_ready), // src.ready
|
|
.src_valid (router_005_src_valid), // .valid
|
|
.src_data (router_005_src_data), // .data
|
|
.src_channel (router_005_src_channel), // .channel
|
|
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_006 (
|
|
.sink_ready (eth0_mdio_avalon_slave_agent_rp_ready), // sink.ready
|
|
.sink_valid (eth0_mdio_avalon_slave_agent_rp_valid), // .valid
|
|
.sink_data (eth0_mdio_avalon_slave_agent_rp_data), // .data
|
|
.sink_startofpacket (eth0_mdio_avalon_slave_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_mdio_avalon_slave_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_006_src_ready), // src.ready
|
|
.src_valid (router_006_src_valid), // .valid
|
|
.src_data (router_006_src_data), // .data
|
|
.src_channel (router_006_src_channel), // .channel
|
|
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_007 router_007 (
|
|
.sink_ready (sram_multiplexer_avl_agent_rp_ready), // sink.ready
|
|
.sink_valid (sram_multiplexer_avl_agent_rp_valid), // .valid
|
|
.sink_data (sram_multiplexer_avl_agent_rp_data), // .data
|
|
.sink_startofpacket (sram_multiplexer_avl_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (sram_multiplexer_avl_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_007_src_ready), // src.ready
|
|
.src_valid (router_007_src_valid), // .valid
|
|
.src_data (router_007_src_data), // .data
|
|
.src_channel (router_007_src_channel), // .channel
|
|
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_008 (
|
|
.sink_ready (vga_sprite_params_avl_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_params_avl_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_params_avl_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_params_avl_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_params_avl_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_008_src_ready), // src.ready
|
|
.src_valid (router_008_src_valid), // .valid
|
|
.src_data (router_008_src_data), // .data
|
|
.src_channel (router_008_src_channel), // .channel
|
|
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_009 router_009 (
|
|
.sink_ready (nios2_sysid_control_slave_agent_rp_ready), // sink.ready
|
|
.sink_valid (nios2_sysid_control_slave_agent_rp_valid), // .valid
|
|
.sink_data (nios2_sysid_control_slave_agent_rp_data), // .data
|
|
.sink_startofpacket (nios2_sysid_control_slave_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_sysid_control_slave_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_009_src_ready), // src.ready
|
|
.src_valid (router_009_src_valid), // .valid
|
|
.src_data (router_009_src_data), // .data
|
|
.src_channel (router_009_src_channel), // .channel
|
|
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_010 (
|
|
.sink_ready (eth0_rx_dma_csr_agent_rp_ready), // sink.ready
|
|
.sink_valid (eth0_rx_dma_csr_agent_rp_valid), // .valid
|
|
.sink_data (eth0_rx_dma_csr_agent_rp_data), // .data
|
|
.sink_startofpacket (eth0_rx_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_rx_dma_csr_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_010_src_ready), // src.ready
|
|
.src_valid (router_010_src_valid), // .valid
|
|
.src_data (router_010_src_data), // .data
|
|
.src_channel (router_010_src_channel), // .channel
|
|
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_011 (
|
|
.sink_ready (eth0_tx_dma_csr_agent_rp_ready), // sink.ready
|
|
.sink_valid (eth0_tx_dma_csr_agent_rp_valid), // .valid
|
|
.sink_data (eth0_tx_dma_csr_agent_rp_data), // .data
|
|
.sink_startofpacket (eth0_tx_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth0_tx_dma_csr_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_011_src_ready), // src.ready
|
|
.src_valid (router_011_src_valid), // .valid
|
|
.src_data (router_011_src_data), // .data
|
|
.src_channel (router_011_src_channel), // .channel
|
|
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_012 (
|
|
.sink_ready (eth1_rx_dma_csr_agent_rp_ready), // sink.ready
|
|
.sink_valid (eth1_rx_dma_csr_agent_rp_valid), // .valid
|
|
.sink_data (eth1_rx_dma_csr_agent_rp_data), // .data
|
|
.sink_startofpacket (eth1_rx_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_rx_dma_csr_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_012_src_ready), // src.ready
|
|
.src_valid (router_012_src_valid), // .valid
|
|
.src_data (router_012_src_data), // .data
|
|
.src_channel (router_012_src_channel), // .channel
|
|
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_013 (
|
|
.sink_ready (eth1_tx_dma_csr_agent_rp_ready), // sink.ready
|
|
.sink_valid (eth1_tx_dma_csr_agent_rp_valid), // .valid
|
|
.sink_data (eth1_tx_dma_csr_agent_rp_data), // .data
|
|
.sink_startofpacket (eth1_tx_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (eth1_tx_dma_csr_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_013_src_ready), // src.ready
|
|
.src_valid (router_013_src_valid), // .valid
|
|
.src_data (router_013_src_data), // .data
|
|
.src_channel (router_013_src_channel), // .channel
|
|
.src_startofpacket (router_013_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_013_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_014 router_014 (
|
|
.sink_ready (nios2_dma_csr_agent_rp_ready), // sink.ready
|
|
.sink_valid (nios2_dma_csr_agent_rp_valid), // .valid
|
|
.sink_data (nios2_dma_csr_agent_rp_data), // .data
|
|
.sink_startofpacket (nios2_dma_csr_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_dma_csr_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_014_src_ready), // src.ready
|
|
.src_valid (router_014_src_valid), // .valid
|
|
.src_data (router_014_src_data), // .data
|
|
.src_channel (router_014_src_channel), // .channel
|
|
.src_startofpacket (router_014_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_014_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_015 router_015 (
|
|
.sink_ready (nios2_cpu_debug_mem_slave_agent_rp_ready), // sink.ready
|
|
.sink_valid (nios2_cpu_debug_mem_slave_agent_rp_valid), // .valid
|
|
.sink_data (nios2_cpu_debug_mem_slave_agent_rp_data), // .data
|
|
.sink_startofpacket (nios2_cpu_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_cpu_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_015_src_ready), // src.ready
|
|
.src_valid (router_015_src_valid), // .valid
|
|
.src_data (router_015_src_data), // .data
|
|
.src_channel (router_015_src_channel), // .channel
|
|
.src_startofpacket (router_015_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_015_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_015 router_016 (
|
|
.sink_ready (nios2_pll_pll_slave_agent_rp_ready), // sink.ready
|
|
.sink_valid (nios2_pll_pll_slave_agent_rp_valid), // .valid
|
|
.sink_data (nios2_pll_pll_slave_agent_rp_data), // .data
|
|
.sink_startofpacket (nios2_pll_pll_slave_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_pll_pll_slave_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_016_src_ready), // src.ready
|
|
.src_valid (router_016_src_valid), // .valid
|
|
.src_data (router_016_src_data), // .data
|
|
.src_channel (router_016_src_channel), // .channel
|
|
.src_startofpacket (router_016_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_016_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_015 router_017 (
|
|
.sink_ready (nios2_onchip_mem_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (nios2_onchip_mem_s1_agent_rp_valid), // .valid
|
|
.sink_data (nios2_onchip_mem_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (nios2_onchip_mem_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_onchip_mem_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_017_src_ready), // src.ready
|
|
.src_valid (router_017_src_valid), // .valid
|
|
.src_data (router_017_src_data), // .data
|
|
.src_channel (router_017_src_channel), // .channel
|
|
.src_startofpacket (router_017_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_017_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_015 router_018 (
|
|
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (sdram_s1_agent_rp_valid), // .valid
|
|
.sink_data (sdram_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_018_src_ready), // src.ready
|
|
.src_valid (router_018_src_valid), // .valid
|
|
.src_data (router_018_src_data), // .data
|
|
.src_channel (router_018_src_channel), // .channel
|
|
.src_startofpacket (router_018_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_018_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_019 (
|
|
.sink_ready (io_led_red_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (io_led_red_s1_agent_rp_valid), // .valid
|
|
.sink_data (io_led_red_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (io_led_red_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (io_led_red_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_019_src_ready), // src.ready
|
|
.src_valid (router_019_src_valid), // .valid
|
|
.src_data (router_019_src_data), // .data
|
|
.src_channel (router_019_src_channel), // .channel
|
|
.src_startofpacket (router_019_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_019_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_020 (
|
|
.sink_ready (nios2_timer_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (nios2_timer_s1_agent_rp_valid), // .valid
|
|
.sink_data (nios2_timer_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (nios2_timer_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_timer_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_020_src_ready), // src.ready
|
|
.src_valid (router_020_src_valid), // .valid
|
|
.src_data (router_020_src_data), // .data
|
|
.src_channel (router_020_src_channel), // .channel
|
|
.src_startofpacket (router_020_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_020_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_021 router_021 (
|
|
.sink_ready (io_keys_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (io_keys_s1_agent_rp_valid), // .valid
|
|
.sink_data (io_keys_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (io_keys_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (io_keys_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_021_src_ready), // src.ready
|
|
.src_valid (router_021_src_valid), // .valid
|
|
.src_data (router_021_src_data), // .data
|
|
.src_channel (router_021_src_channel), // .channel
|
|
.src_startofpacket (router_021_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_021_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_021 router_022 (
|
|
.sink_ready (io_switches_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (io_switches_s1_agent_rp_valid), // .valid
|
|
.sink_data (io_switches_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (io_switches_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (io_switches_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_022_src_ready), // src.ready
|
|
.src_valid (router_022_src_valid), // .valid
|
|
.src_data (router_022_src_data), // .data
|
|
.src_channel (router_022_src_channel), // .channel
|
|
.src_startofpacket (router_022_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_022_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_023 (
|
|
.sink_ready (io_led_green_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (io_led_green_s1_agent_rp_valid), // .valid
|
|
.sink_data (io_led_green_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (io_led_green_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (io_led_green_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_023_src_ready), // src.ready
|
|
.src_valid (router_023_src_valid), // .valid
|
|
.src_data (router_023_src_data), // .data
|
|
.src_channel (router_023_src_channel), // .channel
|
|
.src_startofpacket (router_023_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_023_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_024 (
|
|
.sink_ready (io_hex_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (io_hex_s1_agent_rp_valid), // .valid
|
|
.sink_data (io_hex_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (io_hex_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (io_hex_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_024_src_ready), // src.ready
|
|
.src_valid (router_024_src_valid), // .valid
|
|
.src_data (router_024_src_data), // .data
|
|
.src_channel (router_024_src_channel), // .channel
|
|
.src_startofpacket (router_024_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_024_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_025 (
|
|
.sink_ready (vga_sprite_0_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_0_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_0_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_0_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_0_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_025_src_ready), // src.ready
|
|
.src_valid (router_025_src_valid), // .valid
|
|
.src_data (router_025_src_data), // .data
|
|
.src_channel (router_025_src_channel), // .channel
|
|
.src_startofpacket (router_025_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_025_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_026 (
|
|
.sink_ready (vga_sprite_1_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_1_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_1_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_1_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_1_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_026_src_ready), // src.ready
|
|
.src_valid (router_026_src_valid), // .valid
|
|
.src_data (router_026_src_data), // .data
|
|
.src_channel (router_026_src_channel), // .channel
|
|
.src_startofpacket (router_026_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_026_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_027 (
|
|
.sink_ready (vga_sprite_2_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_2_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_2_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_2_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_2_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_027_src_ready), // src.ready
|
|
.src_valid (router_027_src_valid), // .valid
|
|
.src_data (router_027_src_data), // .data
|
|
.src_channel (router_027_src_channel), // .channel
|
|
.src_startofpacket (router_027_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_027_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_028 (
|
|
.sink_ready (vga_sprite_3_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_3_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_3_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_3_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_3_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_028_src_ready), // src.ready
|
|
.src_valid (router_028_src_valid), // .valid
|
|
.src_data (router_028_src_data), // .data
|
|
.src_channel (router_028_src_channel), // .channel
|
|
.src_startofpacket (router_028_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_028_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_021 router_029 (
|
|
.sink_ready (io_vga_sync_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (io_vga_sync_s1_agent_rp_valid), // .valid
|
|
.sink_data (io_vga_sync_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (io_vga_sync_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (io_vga_sync_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_029_src_ready), // src.ready
|
|
.src_valid (router_029_src_valid), // .valid
|
|
.src_data (router_029_src_data), // .data
|
|
.src_channel (router_029_src_channel), // .channel
|
|
.src_startofpacket (router_029_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_029_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_030 (
|
|
.sink_ready (vga_sprite_4_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_4_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_4_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_4_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_4_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_030_src_ready), // src.ready
|
|
.src_valid (router_030_src_valid), // .valid
|
|
.src_data (router_030_src_data), // .data
|
|
.src_channel (router_030_src_channel), // .channel
|
|
.src_startofpacket (router_030_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_030_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_031 (
|
|
.sink_ready (vga_sprite_5_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_5_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_5_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_5_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_5_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_031_src_ready), // src.ready
|
|
.src_valid (router_031_src_valid), // .valid
|
|
.src_data (router_031_src_data), // .data
|
|
.src_channel (router_031_src_channel), // .channel
|
|
.src_startofpacket (router_031_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_031_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_032 (
|
|
.sink_ready (vga_sprite_6_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_6_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_6_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_6_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_6_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_032_src_ready), // src.ready
|
|
.src_valid (router_032_src_valid), // .valid
|
|
.src_data (router_032_src_data), // .data
|
|
.src_channel (router_032_src_channel), // .channel
|
|
.src_startofpacket (router_032_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_032_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_033 (
|
|
.sink_ready (vga_sprite_7_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_sprite_7_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_sprite_7_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_sprite_7_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_sprite_7_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_033_src_ready), // src.ready
|
|
.src_valid (router_033_src_valid), // .valid
|
|
.src_data (router_033_src_data), // .data
|
|
.src_channel (router_033_src_channel), // .channel
|
|
.src_startofpacket (router_033_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_033_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_034 (
|
|
.sink_ready (vga_background_offset_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (vga_background_offset_s1_agent_rp_valid), // .valid
|
|
.sink_data (vga_background_offset_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (vga_background_offset_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (vga_background_offset_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_034_src_ready), // src.ready
|
|
.src_valid (router_034_src_valid), // .valid
|
|
.src_data (router_034_src_data), // .data
|
|
.src_channel (router_034_src_channel), // .channel
|
|
.src_startofpacket (router_034_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_034_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_014 router_035 (
|
|
.sink_ready (audio_pio_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (audio_pio_s1_agent_rp_valid), // .valid
|
|
.sink_data (audio_pio_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (audio_pio_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (audio_pio_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_035_src_ready), // src.ready
|
|
.src_valid (router_035_src_valid), // .valid
|
|
.src_data (router_035_src_data), // .data
|
|
.src_channel (router_035_src_channel), // .channel
|
|
.src_startofpacket (router_035_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_035_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_014 router_036 (
|
|
.sink_ready (audio_timer_s1_agent_rp_ready), // sink.ready
|
|
.sink_valid (audio_timer_s1_agent_rp_valid), // .valid
|
|
.sink_data (audio_timer_s1_agent_rp_data), // .data
|
|
.sink_startofpacket (audio_timer_s1_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (audio_timer_s1_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_036_src_ready), // src.ready
|
|
.src_valid (router_036_src_valid), // .valid
|
|
.src_data (router_036_src_data), // .data
|
|
.src_channel (router_036_src_channel), // .channel
|
|
.src_startofpacket (router_036_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_036_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_router_004 router_037 (
|
|
.sink_ready (usb_keycode_s2_agent_rp_ready), // sink.ready
|
|
.sink_valid (usb_keycode_s2_agent_rp_valid), // .valid
|
|
.sink_data (usb_keycode_s2_agent_rp_data), // .data
|
|
.sink_startofpacket (usb_keycode_s2_agent_rp_startofpacket), // .startofpacket
|
|
.sink_endofpacket (usb_keycode_s2_agent_rp_endofpacket), // .endofpacket
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (router_037_src_ready), // src.ready
|
|
.src_valid (router_037_src_valid), // .valid
|
|
.src_data (router_037_src_data), // .data
|
|
.src_channel (router_037_src_channel), // .channel
|
|
.src_startofpacket (router_037_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (router_037_src_endofpacket) // .endofpacket
|
|
);
|
|
|
|
altera_merlin_traffic_limiter #(
|
|
.PKT_DEST_ID_H (100),
|
|
.PKT_DEST_ID_L (95),
|
|
.PKT_SRC_ID_H (94),
|
|
.PKT_SRC_ID_L (89),
|
|
.PKT_BYTE_CNT_H (76),
|
|
.PKT_BYTE_CNT_L (74),
|
|
.PKT_BYTEEN_H (35),
|
|
.PKT_BYTEEN_L (32),
|
|
.PKT_TRANS_POSTED (69),
|
|
.PKT_TRANS_WRITE (70),
|
|
.MAX_OUTSTANDING_RESPONSES (7),
|
|
.PIPELINED (0),
|
|
.ST_DATA_W (114),
|
|
.ST_CHANNEL_W (34),
|
|
.VALID_WIDTH (34),
|
|
.ENFORCE_ORDER (1),
|
|
.PREVENT_HAZARDS (0),
|
|
.SUPPORTS_POSTED_WRITES (1),
|
|
.SUPPORTS_NONPOSTED_WRITES (0),
|
|
.REORDER (0)
|
|
) nios2_dma_m_read_limiter (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
|
|
.cmd_sink_valid (router_001_src_valid), // .valid
|
|
.cmd_sink_data (router_001_src_data), // .data
|
|
.cmd_sink_channel (router_001_src_channel), // .channel
|
|
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
|
|
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
|
|
.cmd_src_ready (nios2_dma_m_read_limiter_cmd_src_ready), // cmd_src.ready
|
|
.cmd_src_data (nios2_dma_m_read_limiter_cmd_src_data), // .data
|
|
.cmd_src_channel (nios2_dma_m_read_limiter_cmd_src_channel), // .channel
|
|
.cmd_src_startofpacket (nios2_dma_m_read_limiter_cmd_src_startofpacket), // .startofpacket
|
|
.cmd_src_endofpacket (nios2_dma_m_read_limiter_cmd_src_endofpacket), // .endofpacket
|
|
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
|
|
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
|
|
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
|
|
.rsp_sink_data (rsp_mux_001_src_data), // .data
|
|
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
|
|
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
|
|
.rsp_src_ready (nios2_dma_m_read_limiter_rsp_src_ready), // rsp_src.ready
|
|
.rsp_src_valid (nios2_dma_m_read_limiter_rsp_src_valid), // .valid
|
|
.rsp_src_data (nios2_dma_m_read_limiter_rsp_src_data), // .data
|
|
.rsp_src_channel (nios2_dma_m_read_limiter_rsp_src_channel), // .channel
|
|
.rsp_src_startofpacket (nios2_dma_m_read_limiter_rsp_src_startofpacket), // .startofpacket
|
|
.rsp_src_endofpacket (nios2_dma_m_read_limiter_rsp_src_endofpacket), // .endofpacket
|
|
.cmd_src_valid (nios2_dma_m_read_limiter_cmd_valid_data) // cmd_valid.data
|
|
);
|
|
|
|
altera_merlin_burst_adapter #(
|
|
.PKT_ADDR_H (49),
|
|
.PKT_ADDR_L (18),
|
|
.PKT_BEGIN_BURST (69),
|
|
.PKT_BYTE_CNT_H (58),
|
|
.PKT_BYTE_CNT_L (56),
|
|
.PKT_BYTEEN_H (17),
|
|
.PKT_BYTEEN_L (16),
|
|
.PKT_BURST_SIZE_H (64),
|
|
.PKT_BURST_SIZE_L (62),
|
|
.PKT_BURST_TYPE_H (66),
|
|
.PKT_BURST_TYPE_L (65),
|
|
.PKT_BURSTWRAP_H (61),
|
|
.PKT_BURSTWRAP_L (59),
|
|
.PKT_TRANS_COMPRESSED_READ (50),
|
|
.PKT_TRANS_WRITE (52),
|
|
.PKT_TRANS_READ (53),
|
|
.OUT_NARROW_SIZE (0),
|
|
.IN_NARROW_SIZE (0),
|
|
.OUT_FIXED (0),
|
|
.OUT_COMPLETE_WRAP (0),
|
|
.ST_DATA_W (96),
|
|
.ST_CHANNEL_W (34),
|
|
.OUT_BYTE_CNT_H (57),
|
|
.OUT_BURSTWRAP_H (61),
|
|
.COMPRESSED_READ_SUPPORT (0),
|
|
.BYTEENABLE_SYNTHESIS (1),
|
|
.PIPE_INPUTS (0),
|
|
.NO_WRAP_SUPPORT (0),
|
|
.INCOMPLETE_WRAP_SUPPORT (0),
|
|
.BURSTWRAP_CONST_MASK (7),
|
|
.BURSTWRAP_CONST_VALUE (7),
|
|
.ADAPTER_VERSION ("13.1")
|
|
) sram_multiplexer_avl_burst_adapter (
|
|
.clk (clk_0_clk_clk), // cr0.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
|
|
.sink0_valid (sram_multiplexer_avl_cmd_width_adapter_src_valid), // sink0.valid
|
|
.sink0_data (sram_multiplexer_avl_cmd_width_adapter_src_data), // .data
|
|
.sink0_channel (sram_multiplexer_avl_cmd_width_adapter_src_channel), // .channel
|
|
.sink0_startofpacket (sram_multiplexer_avl_cmd_width_adapter_src_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (sram_multiplexer_avl_cmd_width_adapter_src_endofpacket), // .endofpacket
|
|
.sink0_ready (sram_multiplexer_avl_cmd_width_adapter_src_ready), // .ready
|
|
.source0_valid (sram_multiplexer_avl_burst_adapter_source0_valid), // source0.valid
|
|
.source0_data (sram_multiplexer_avl_burst_adapter_source0_data), // .data
|
|
.source0_channel (sram_multiplexer_avl_burst_adapter_source0_channel), // .channel
|
|
.source0_startofpacket (sram_multiplexer_avl_burst_adapter_source0_startofpacket), // .startofpacket
|
|
.source0_endofpacket (sram_multiplexer_avl_burst_adapter_source0_endofpacket), // .endofpacket
|
|
.source0_ready (sram_multiplexer_avl_burst_adapter_source0_ready) // .ready
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_demux cmd_demux (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_src_ready), // sink.ready
|
|
.sink_channel (router_src_channel), // .channel
|
|
.sink_data (router_src_data), // .data
|
|
.sink_startofpacket (router_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_src_valid), // .valid
|
|
.src0_ready (cmd_demux_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_src0_valid), // .valid
|
|
.src0_data (cmd_demux_src0_data), // .data
|
|
.src0_channel (cmd_demux_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
|
|
.src1_ready (cmd_demux_src1_ready), // src1.ready
|
|
.src1_valid (cmd_demux_src1_valid), // .valid
|
|
.src1_data (cmd_demux_src1_data), // .data
|
|
.src1_channel (cmd_demux_src1_channel), // .channel
|
|
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
|
|
.src2_ready (cmd_demux_src2_ready), // src2.ready
|
|
.src2_valid (cmd_demux_src2_valid), // .valid
|
|
.src2_data (cmd_demux_src2_data), // .data
|
|
.src2_channel (cmd_demux_src2_channel), // .channel
|
|
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
|
|
.src3_ready (cmd_demux_src3_ready), // src3.ready
|
|
.src3_valid (cmd_demux_src3_valid), // .valid
|
|
.src3_data (cmd_demux_src3_data), // .data
|
|
.src3_channel (cmd_demux_src3_channel), // .channel
|
|
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
|
|
.src4_ready (cmd_demux_src4_ready), // src4.ready
|
|
.src4_valid (cmd_demux_src4_valid), // .valid
|
|
.src4_data (cmd_demux_src4_data), // .data
|
|
.src4_channel (cmd_demux_src4_channel), // .channel
|
|
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
|
|
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
|
|
.src5_ready (cmd_demux_src5_ready), // src5.ready
|
|
.src5_valid (cmd_demux_src5_valid), // .valid
|
|
.src5_data (cmd_demux_src5_data), // .data
|
|
.src5_channel (cmd_demux_src5_channel), // .channel
|
|
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
|
|
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
|
|
.src6_ready (cmd_demux_src6_ready), // src6.ready
|
|
.src6_valid (cmd_demux_src6_valid), // .valid
|
|
.src6_data (cmd_demux_src6_data), // .data
|
|
.src6_channel (cmd_demux_src6_channel), // .channel
|
|
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
|
|
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
|
|
.src7_ready (cmd_demux_src7_ready), // src7.ready
|
|
.src7_valid (cmd_demux_src7_valid), // .valid
|
|
.src7_data (cmd_demux_src7_data), // .data
|
|
.src7_channel (cmd_demux_src7_channel), // .channel
|
|
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
|
|
.src7_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
|
|
.src8_ready (cmd_demux_src8_ready), // src8.ready
|
|
.src8_valid (cmd_demux_src8_valid), // .valid
|
|
.src8_data (cmd_demux_src8_data), // .data
|
|
.src8_channel (cmd_demux_src8_channel), // .channel
|
|
.src8_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
|
|
.src8_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
|
|
.src9_ready (cmd_demux_src9_ready), // src9.ready
|
|
.src9_valid (cmd_demux_src9_valid), // .valid
|
|
.src9_data (cmd_demux_src9_data), // .data
|
|
.src9_channel (cmd_demux_src9_channel), // .channel
|
|
.src9_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
|
|
.src9_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
|
|
.src10_ready (cmd_demux_src10_ready), // src10.ready
|
|
.src10_valid (cmd_demux_src10_valid), // .valid
|
|
.src10_data (cmd_demux_src10_data), // .data
|
|
.src10_channel (cmd_demux_src10_channel), // .channel
|
|
.src10_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
|
|
.src10_endofpacket (cmd_demux_src10_endofpacket), // .endofpacket
|
|
.src11_ready (cmd_demux_src11_ready), // src11.ready
|
|
.src11_valid (cmd_demux_src11_valid), // .valid
|
|
.src11_data (cmd_demux_src11_data), // .data
|
|
.src11_channel (cmd_demux_src11_channel), // .channel
|
|
.src11_startofpacket (cmd_demux_src11_startofpacket), // .startofpacket
|
|
.src11_endofpacket (cmd_demux_src11_endofpacket), // .endofpacket
|
|
.src12_ready (cmd_demux_src12_ready), // src12.ready
|
|
.src12_valid (cmd_demux_src12_valid), // .valid
|
|
.src12_data (cmd_demux_src12_data), // .data
|
|
.src12_channel (cmd_demux_src12_channel), // .channel
|
|
.src12_startofpacket (cmd_demux_src12_startofpacket), // .startofpacket
|
|
.src12_endofpacket (cmd_demux_src12_endofpacket), // .endofpacket
|
|
.src13_ready (cmd_demux_src13_ready), // src13.ready
|
|
.src13_valid (cmd_demux_src13_valid), // .valid
|
|
.src13_data (cmd_demux_src13_data), // .data
|
|
.src13_channel (cmd_demux_src13_channel), // .channel
|
|
.src13_startofpacket (cmd_demux_src13_startofpacket), // .startofpacket
|
|
.src13_endofpacket (cmd_demux_src13_endofpacket), // .endofpacket
|
|
.src14_ready (cmd_demux_src14_ready), // src14.ready
|
|
.src14_valid (cmd_demux_src14_valid), // .valid
|
|
.src14_data (cmd_demux_src14_data), // .data
|
|
.src14_channel (cmd_demux_src14_channel), // .channel
|
|
.src14_startofpacket (cmd_demux_src14_startofpacket), // .startofpacket
|
|
.src14_endofpacket (cmd_demux_src14_endofpacket), // .endofpacket
|
|
.src15_ready (cmd_demux_src15_ready), // src15.ready
|
|
.src15_valid (cmd_demux_src15_valid), // .valid
|
|
.src15_data (cmd_demux_src15_data), // .data
|
|
.src15_channel (cmd_demux_src15_channel), // .channel
|
|
.src15_startofpacket (cmd_demux_src15_startofpacket), // .startofpacket
|
|
.src15_endofpacket (cmd_demux_src15_endofpacket), // .endofpacket
|
|
.src16_ready (cmd_demux_src16_ready), // src16.ready
|
|
.src16_valid (cmd_demux_src16_valid), // .valid
|
|
.src16_data (cmd_demux_src16_data), // .data
|
|
.src16_channel (cmd_demux_src16_channel), // .channel
|
|
.src16_startofpacket (cmd_demux_src16_startofpacket), // .startofpacket
|
|
.src16_endofpacket (cmd_demux_src16_endofpacket), // .endofpacket
|
|
.src17_ready (cmd_demux_src17_ready), // src17.ready
|
|
.src17_valid (cmd_demux_src17_valid), // .valid
|
|
.src17_data (cmd_demux_src17_data), // .data
|
|
.src17_channel (cmd_demux_src17_channel), // .channel
|
|
.src17_startofpacket (cmd_demux_src17_startofpacket), // .startofpacket
|
|
.src17_endofpacket (cmd_demux_src17_endofpacket), // .endofpacket
|
|
.src18_ready (cmd_demux_src18_ready), // src18.ready
|
|
.src18_valid (cmd_demux_src18_valid), // .valid
|
|
.src18_data (cmd_demux_src18_data), // .data
|
|
.src18_channel (cmd_demux_src18_channel), // .channel
|
|
.src18_startofpacket (cmd_demux_src18_startofpacket), // .startofpacket
|
|
.src18_endofpacket (cmd_demux_src18_endofpacket), // .endofpacket
|
|
.src19_ready (cmd_demux_src19_ready), // src19.ready
|
|
.src19_valid (cmd_demux_src19_valid), // .valid
|
|
.src19_data (cmd_demux_src19_data), // .data
|
|
.src19_channel (cmd_demux_src19_channel), // .channel
|
|
.src19_startofpacket (cmd_demux_src19_startofpacket), // .startofpacket
|
|
.src19_endofpacket (cmd_demux_src19_endofpacket), // .endofpacket
|
|
.src20_ready (cmd_demux_src20_ready), // src20.ready
|
|
.src20_valid (cmd_demux_src20_valid), // .valid
|
|
.src20_data (cmd_demux_src20_data), // .data
|
|
.src20_channel (cmd_demux_src20_channel), // .channel
|
|
.src20_startofpacket (cmd_demux_src20_startofpacket), // .startofpacket
|
|
.src20_endofpacket (cmd_demux_src20_endofpacket), // .endofpacket
|
|
.src21_ready (cmd_demux_src21_ready), // src21.ready
|
|
.src21_valid (cmd_demux_src21_valid), // .valid
|
|
.src21_data (cmd_demux_src21_data), // .data
|
|
.src21_channel (cmd_demux_src21_channel), // .channel
|
|
.src21_startofpacket (cmd_demux_src21_startofpacket), // .startofpacket
|
|
.src21_endofpacket (cmd_demux_src21_endofpacket), // .endofpacket
|
|
.src22_ready (cmd_demux_src22_ready), // src22.ready
|
|
.src22_valid (cmd_demux_src22_valid), // .valid
|
|
.src22_data (cmd_demux_src22_data), // .data
|
|
.src22_channel (cmd_demux_src22_channel), // .channel
|
|
.src22_startofpacket (cmd_demux_src22_startofpacket), // .startofpacket
|
|
.src22_endofpacket (cmd_demux_src22_endofpacket), // .endofpacket
|
|
.src23_ready (cmd_demux_src23_ready), // src23.ready
|
|
.src23_valid (cmd_demux_src23_valid), // .valid
|
|
.src23_data (cmd_demux_src23_data), // .data
|
|
.src23_channel (cmd_demux_src23_channel), // .channel
|
|
.src23_startofpacket (cmd_demux_src23_startofpacket), // .startofpacket
|
|
.src23_endofpacket (cmd_demux_src23_endofpacket), // .endofpacket
|
|
.src24_ready (cmd_demux_src24_ready), // src24.ready
|
|
.src24_valid (cmd_demux_src24_valid), // .valid
|
|
.src24_data (cmd_demux_src24_data), // .data
|
|
.src24_channel (cmd_demux_src24_channel), // .channel
|
|
.src24_startofpacket (cmd_demux_src24_startofpacket), // .startofpacket
|
|
.src24_endofpacket (cmd_demux_src24_endofpacket), // .endofpacket
|
|
.src25_ready (cmd_demux_src25_ready), // src25.ready
|
|
.src25_valid (cmd_demux_src25_valid), // .valid
|
|
.src25_data (cmd_demux_src25_data), // .data
|
|
.src25_channel (cmd_demux_src25_channel), // .channel
|
|
.src25_startofpacket (cmd_demux_src25_startofpacket), // .startofpacket
|
|
.src25_endofpacket (cmd_demux_src25_endofpacket), // .endofpacket
|
|
.src26_ready (cmd_demux_src26_ready), // src26.ready
|
|
.src26_valid (cmd_demux_src26_valid), // .valid
|
|
.src26_data (cmd_demux_src26_data), // .data
|
|
.src26_channel (cmd_demux_src26_channel), // .channel
|
|
.src26_startofpacket (cmd_demux_src26_startofpacket), // .startofpacket
|
|
.src26_endofpacket (cmd_demux_src26_endofpacket), // .endofpacket
|
|
.src27_ready (cmd_demux_src27_ready), // src27.ready
|
|
.src27_valid (cmd_demux_src27_valid), // .valid
|
|
.src27_data (cmd_demux_src27_data), // .data
|
|
.src27_channel (cmd_demux_src27_channel), // .channel
|
|
.src27_startofpacket (cmd_demux_src27_startofpacket), // .startofpacket
|
|
.src27_endofpacket (cmd_demux_src27_endofpacket), // .endofpacket
|
|
.src28_ready (cmd_demux_src28_ready), // src28.ready
|
|
.src28_valid (cmd_demux_src28_valid), // .valid
|
|
.src28_data (cmd_demux_src28_data), // .data
|
|
.src28_channel (cmd_demux_src28_channel), // .channel
|
|
.src28_startofpacket (cmd_demux_src28_startofpacket), // .startofpacket
|
|
.src28_endofpacket (cmd_demux_src28_endofpacket), // .endofpacket
|
|
.src29_ready (cmd_demux_src29_ready), // src29.ready
|
|
.src29_valid (cmd_demux_src29_valid), // .valid
|
|
.src29_data (cmd_demux_src29_data), // .data
|
|
.src29_channel (cmd_demux_src29_channel), // .channel
|
|
.src29_startofpacket (cmd_demux_src29_startofpacket), // .startofpacket
|
|
.src29_endofpacket (cmd_demux_src29_endofpacket), // .endofpacket
|
|
.src30_ready (cmd_demux_src30_ready), // src30.ready
|
|
.src30_valid (cmd_demux_src30_valid), // .valid
|
|
.src30_data (cmd_demux_src30_data), // .data
|
|
.src30_channel (cmd_demux_src30_channel), // .channel
|
|
.src30_startofpacket (cmd_demux_src30_startofpacket), // .startofpacket
|
|
.src30_endofpacket (cmd_demux_src30_endofpacket), // .endofpacket
|
|
.src31_ready (cmd_demux_src31_ready), // src31.ready
|
|
.src31_valid (cmd_demux_src31_valid), // .valid
|
|
.src31_data (cmd_demux_src31_data), // .data
|
|
.src31_channel (cmd_demux_src31_channel), // .channel
|
|
.src31_startofpacket (cmd_demux_src31_startofpacket), // .startofpacket
|
|
.src31_endofpacket (cmd_demux_src31_endofpacket), // .endofpacket
|
|
.src32_ready (cmd_demux_src32_ready), // src32.ready
|
|
.src32_valid (cmd_demux_src32_valid), // .valid
|
|
.src32_data (cmd_demux_src32_data), // .data
|
|
.src32_channel (cmd_demux_src32_channel), // .channel
|
|
.src32_startofpacket (cmd_demux_src32_startofpacket), // .startofpacket
|
|
.src32_endofpacket (cmd_demux_src32_endofpacket), // .endofpacket
|
|
.src33_ready (cmd_demux_src33_ready), // src33.ready
|
|
.src33_valid (cmd_demux_src33_valid), // .valid
|
|
.src33_data (cmd_demux_src33_data), // .data
|
|
.src33_channel (cmd_demux_src33_channel), // .channel
|
|
.src33_startofpacket (cmd_demux_src33_startofpacket), // .startofpacket
|
|
.src33_endofpacket (cmd_demux_src33_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (nios2_dma_m_read_limiter_cmd_src_ready), // sink.ready
|
|
.sink_channel (nios2_dma_m_read_limiter_cmd_src_channel), // .channel
|
|
.sink_data (nios2_dma_m_read_limiter_cmd_src_data), // .data
|
|
.sink_startofpacket (nios2_dma_m_read_limiter_cmd_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (nios2_dma_m_read_limiter_cmd_src_endofpacket), // .endofpacket
|
|
.sink_valid (nios2_dma_m_read_limiter_cmd_valid_data), // sink_valid.data
|
|
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_001_src0_valid), // .valid
|
|
.src0_data (cmd_demux_001_src0_data), // .data
|
|
.src0_channel (cmd_demux_001_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
|
|
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
|
|
.src1_valid (cmd_demux_001_src1_valid), // .valid
|
|
.src1_data (cmd_demux_001_src1_data), // .data
|
|
.src1_channel (cmd_demux_001_src1_channel), // .channel
|
|
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
|
|
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
|
|
.src2_valid (cmd_demux_001_src2_valid), // .valid
|
|
.src2_data (cmd_demux_001_src2_data), // .data
|
|
.src2_channel (cmd_demux_001_src2_channel), // .channel
|
|
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
|
|
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
|
|
.src3_valid (cmd_demux_001_src3_valid), // .valid
|
|
.src3_data (cmd_demux_001_src3_data), // .data
|
|
.src3_channel (cmd_demux_001_src3_channel), // .channel
|
|
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
|
|
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
|
|
.src4_valid (cmd_demux_001_src4_valid), // .valid
|
|
.src4_data (cmd_demux_001_src4_data), // .data
|
|
.src4_channel (cmd_demux_001_src4_channel), // .channel
|
|
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
|
|
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
|
|
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
|
|
.src5_valid (cmd_demux_001_src5_valid), // .valid
|
|
.src5_data (cmd_demux_001_src5_data), // .data
|
|
.src5_channel (cmd_demux_001_src5_channel), // .channel
|
|
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
|
|
.src5_endofpacket (cmd_demux_001_src5_endofpacket), // .endofpacket
|
|
.src6_ready (cmd_demux_001_src6_ready), // src6.ready
|
|
.src6_valid (cmd_demux_001_src6_valid), // .valid
|
|
.src6_data (cmd_demux_001_src6_data), // .data
|
|
.src6_channel (cmd_demux_001_src6_channel), // .channel
|
|
.src6_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
|
|
.src6_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
|
|
.src7_ready (cmd_demux_001_src7_ready), // src7.ready
|
|
.src7_valid (cmd_demux_001_src7_valid), // .valid
|
|
.src7_data (cmd_demux_001_src7_data), // .data
|
|
.src7_channel (cmd_demux_001_src7_channel), // .channel
|
|
.src7_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
|
|
.src7_endofpacket (cmd_demux_001_src7_endofpacket), // .endofpacket
|
|
.src8_ready (cmd_demux_001_src8_ready), // src8.ready
|
|
.src8_valid (cmd_demux_001_src8_valid), // .valid
|
|
.src8_data (cmd_demux_001_src8_data), // .data
|
|
.src8_channel (cmd_demux_001_src8_channel), // .channel
|
|
.src8_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
|
|
.src8_endofpacket (cmd_demux_001_src8_endofpacket), // .endofpacket
|
|
.src9_ready (cmd_demux_001_src9_ready), // src9.ready
|
|
.src9_valid (cmd_demux_001_src9_valid), // .valid
|
|
.src9_data (cmd_demux_001_src9_data), // .data
|
|
.src9_channel (cmd_demux_001_src9_channel), // .channel
|
|
.src9_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
|
|
.src9_endofpacket (cmd_demux_001_src9_endofpacket), // .endofpacket
|
|
.src10_ready (cmd_demux_001_src10_ready), // src10.ready
|
|
.src10_valid (cmd_demux_001_src10_valid), // .valid
|
|
.src10_data (cmd_demux_001_src10_data), // .data
|
|
.src10_channel (cmd_demux_001_src10_channel), // .channel
|
|
.src10_startofpacket (cmd_demux_001_src10_startofpacket), // .startofpacket
|
|
.src10_endofpacket (cmd_demux_001_src10_endofpacket), // .endofpacket
|
|
.src11_ready (cmd_demux_001_src11_ready), // src11.ready
|
|
.src11_valid (cmd_demux_001_src11_valid), // .valid
|
|
.src11_data (cmd_demux_001_src11_data), // .data
|
|
.src11_channel (cmd_demux_001_src11_channel), // .channel
|
|
.src11_startofpacket (cmd_demux_001_src11_startofpacket), // .startofpacket
|
|
.src11_endofpacket (cmd_demux_001_src11_endofpacket), // .endofpacket
|
|
.src12_ready (cmd_demux_001_src12_ready), // src12.ready
|
|
.src12_valid (cmd_demux_001_src12_valid), // .valid
|
|
.src12_data (cmd_demux_001_src12_data), // .data
|
|
.src12_channel (cmd_demux_001_src12_channel), // .channel
|
|
.src12_startofpacket (cmd_demux_001_src12_startofpacket), // .startofpacket
|
|
.src12_endofpacket (cmd_demux_001_src12_endofpacket), // .endofpacket
|
|
.src13_ready (cmd_demux_001_src13_ready), // src13.ready
|
|
.src13_valid (cmd_demux_001_src13_valid), // .valid
|
|
.src13_data (cmd_demux_001_src13_data), // .data
|
|
.src13_channel (cmd_demux_001_src13_channel), // .channel
|
|
.src13_startofpacket (cmd_demux_001_src13_startofpacket), // .startofpacket
|
|
.src13_endofpacket (cmd_demux_001_src13_endofpacket), // .endofpacket
|
|
.src14_ready (cmd_demux_001_src14_ready), // src14.ready
|
|
.src14_valid (cmd_demux_001_src14_valid), // .valid
|
|
.src14_data (cmd_demux_001_src14_data), // .data
|
|
.src14_channel (cmd_demux_001_src14_channel), // .channel
|
|
.src14_startofpacket (cmd_demux_001_src14_startofpacket), // .startofpacket
|
|
.src14_endofpacket (cmd_demux_001_src14_endofpacket), // .endofpacket
|
|
.src15_ready (cmd_demux_001_src15_ready), // src15.ready
|
|
.src15_valid (cmd_demux_001_src15_valid), // .valid
|
|
.src15_data (cmd_demux_001_src15_data), // .data
|
|
.src15_channel (cmd_demux_001_src15_channel), // .channel
|
|
.src15_startofpacket (cmd_demux_001_src15_startofpacket), // .startofpacket
|
|
.src15_endofpacket (cmd_demux_001_src15_endofpacket), // .endofpacket
|
|
.src16_ready (cmd_demux_001_src16_ready), // src16.ready
|
|
.src16_valid (cmd_demux_001_src16_valid), // .valid
|
|
.src16_data (cmd_demux_001_src16_data), // .data
|
|
.src16_channel (cmd_demux_001_src16_channel), // .channel
|
|
.src16_startofpacket (cmd_demux_001_src16_startofpacket), // .startofpacket
|
|
.src16_endofpacket (cmd_demux_001_src16_endofpacket), // .endofpacket
|
|
.src17_ready (cmd_demux_001_src17_ready), // src17.ready
|
|
.src17_valid (cmd_demux_001_src17_valid), // .valid
|
|
.src17_data (cmd_demux_001_src17_data), // .data
|
|
.src17_channel (cmd_demux_001_src17_channel), // .channel
|
|
.src17_startofpacket (cmd_demux_001_src17_startofpacket), // .startofpacket
|
|
.src17_endofpacket (cmd_demux_001_src17_endofpacket), // .endofpacket
|
|
.src18_ready (cmd_demux_001_src18_ready), // src18.ready
|
|
.src18_valid (cmd_demux_001_src18_valid), // .valid
|
|
.src18_data (cmd_demux_001_src18_data), // .data
|
|
.src18_channel (cmd_demux_001_src18_channel), // .channel
|
|
.src18_startofpacket (cmd_demux_001_src18_startofpacket), // .startofpacket
|
|
.src18_endofpacket (cmd_demux_001_src18_endofpacket), // .endofpacket
|
|
.src19_ready (cmd_demux_001_src19_ready), // src19.ready
|
|
.src19_valid (cmd_demux_001_src19_valid), // .valid
|
|
.src19_data (cmd_demux_001_src19_data), // .data
|
|
.src19_channel (cmd_demux_001_src19_channel), // .channel
|
|
.src19_startofpacket (cmd_demux_001_src19_startofpacket), // .startofpacket
|
|
.src19_endofpacket (cmd_demux_001_src19_endofpacket), // .endofpacket
|
|
.src20_ready (cmd_demux_001_src20_ready), // src20.ready
|
|
.src20_valid (cmd_demux_001_src20_valid), // .valid
|
|
.src20_data (cmd_demux_001_src20_data), // .data
|
|
.src20_channel (cmd_demux_001_src20_channel), // .channel
|
|
.src20_startofpacket (cmd_demux_001_src20_startofpacket), // .startofpacket
|
|
.src20_endofpacket (cmd_demux_001_src20_endofpacket), // .endofpacket
|
|
.src21_ready (cmd_demux_001_src21_ready), // src21.ready
|
|
.src21_valid (cmd_demux_001_src21_valid), // .valid
|
|
.src21_data (cmd_demux_001_src21_data), // .data
|
|
.src21_channel (cmd_demux_001_src21_channel), // .channel
|
|
.src21_startofpacket (cmd_demux_001_src21_startofpacket), // .startofpacket
|
|
.src21_endofpacket (cmd_demux_001_src21_endofpacket), // .endofpacket
|
|
.src22_ready (cmd_demux_001_src22_ready), // src22.ready
|
|
.src22_valid (cmd_demux_001_src22_valid), // .valid
|
|
.src22_data (cmd_demux_001_src22_data), // .data
|
|
.src22_channel (cmd_demux_001_src22_channel), // .channel
|
|
.src22_startofpacket (cmd_demux_001_src22_startofpacket), // .startofpacket
|
|
.src22_endofpacket (cmd_demux_001_src22_endofpacket), // .endofpacket
|
|
.src23_ready (cmd_demux_001_src23_ready), // src23.ready
|
|
.src23_valid (cmd_demux_001_src23_valid), // .valid
|
|
.src23_data (cmd_demux_001_src23_data), // .data
|
|
.src23_channel (cmd_demux_001_src23_channel), // .channel
|
|
.src23_startofpacket (cmd_demux_001_src23_startofpacket), // .startofpacket
|
|
.src23_endofpacket (cmd_demux_001_src23_endofpacket), // .endofpacket
|
|
.src24_ready (cmd_demux_001_src24_ready), // src24.ready
|
|
.src24_valid (cmd_demux_001_src24_valid), // .valid
|
|
.src24_data (cmd_demux_001_src24_data), // .data
|
|
.src24_channel (cmd_demux_001_src24_channel), // .channel
|
|
.src24_startofpacket (cmd_demux_001_src24_startofpacket), // .startofpacket
|
|
.src24_endofpacket (cmd_demux_001_src24_endofpacket), // .endofpacket
|
|
.src25_ready (cmd_demux_001_src25_ready), // src25.ready
|
|
.src25_valid (cmd_demux_001_src25_valid), // .valid
|
|
.src25_data (cmd_demux_001_src25_data), // .data
|
|
.src25_channel (cmd_demux_001_src25_channel), // .channel
|
|
.src25_startofpacket (cmd_demux_001_src25_startofpacket), // .startofpacket
|
|
.src25_endofpacket (cmd_demux_001_src25_endofpacket), // .endofpacket
|
|
.src26_ready (cmd_demux_001_src26_ready), // src26.ready
|
|
.src26_valid (cmd_demux_001_src26_valid), // .valid
|
|
.src26_data (cmd_demux_001_src26_data), // .data
|
|
.src26_channel (cmd_demux_001_src26_channel), // .channel
|
|
.src26_startofpacket (cmd_demux_001_src26_startofpacket), // .startofpacket
|
|
.src26_endofpacket (cmd_demux_001_src26_endofpacket), // .endofpacket
|
|
.src27_ready (cmd_demux_001_src27_ready), // src27.ready
|
|
.src27_valid (cmd_demux_001_src27_valid), // .valid
|
|
.src27_data (cmd_demux_001_src27_data), // .data
|
|
.src27_channel (cmd_demux_001_src27_channel), // .channel
|
|
.src27_startofpacket (cmd_demux_001_src27_startofpacket), // .startofpacket
|
|
.src27_endofpacket (cmd_demux_001_src27_endofpacket), // .endofpacket
|
|
.src28_ready (cmd_demux_001_src28_ready), // src28.ready
|
|
.src28_valid (cmd_demux_001_src28_valid), // .valid
|
|
.src28_data (cmd_demux_001_src28_data), // .data
|
|
.src28_channel (cmd_demux_001_src28_channel), // .channel
|
|
.src28_startofpacket (cmd_demux_001_src28_startofpacket), // .startofpacket
|
|
.src28_endofpacket (cmd_demux_001_src28_endofpacket), // .endofpacket
|
|
.src29_ready (cmd_demux_001_src29_ready), // src29.ready
|
|
.src29_valid (cmd_demux_001_src29_valid), // .valid
|
|
.src29_data (cmd_demux_001_src29_data), // .data
|
|
.src29_channel (cmd_demux_001_src29_channel), // .channel
|
|
.src29_startofpacket (cmd_demux_001_src29_startofpacket), // .startofpacket
|
|
.src29_endofpacket (cmd_demux_001_src29_endofpacket), // .endofpacket
|
|
.src30_ready (cmd_demux_001_src30_ready), // src30.ready
|
|
.src30_valid (cmd_demux_001_src30_valid), // .valid
|
|
.src30_data (cmd_demux_001_src30_data), // .data
|
|
.src30_channel (cmd_demux_001_src30_channel), // .channel
|
|
.src30_startofpacket (cmd_demux_001_src30_startofpacket), // .startofpacket
|
|
.src30_endofpacket (cmd_demux_001_src30_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_002_src_ready), // sink.ready
|
|
.sink_channel (router_002_src_channel), // .channel
|
|
.sink_data (router_002_src_data), // .data
|
|
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_002_src_valid), // .valid
|
|
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_002_src0_valid), // .valid
|
|
.src0_data (cmd_demux_002_src0_data), // .data
|
|
.src0_channel (cmd_demux_002_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
|
|
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
|
|
.src1_valid (cmd_demux_002_src1_valid), // .valid
|
|
.src1_data (cmd_demux_002_src1_data), // .data
|
|
.src1_channel (cmd_demux_002_src1_channel), // .channel
|
|
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
|
|
.src2_ready (cmd_demux_002_src2_ready), // src2.ready
|
|
.src2_valid (cmd_demux_002_src2_valid), // .valid
|
|
.src2_data (cmd_demux_002_src2_data), // .data
|
|
.src2_channel (cmd_demux_002_src2_channel), // .channel
|
|
.src2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (cmd_demux_002_src2_endofpacket), // .endofpacket
|
|
.src3_ready (cmd_demux_002_src3_ready), // src3.ready
|
|
.src3_valid (cmd_demux_002_src3_valid), // .valid
|
|
.src3_data (cmd_demux_002_src3_data), // .data
|
|
.src3_channel (cmd_demux_002_src3_channel), // .channel
|
|
.src3_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (cmd_demux_002_src3_endofpacket), // .endofpacket
|
|
.src4_ready (cmd_demux_002_src4_ready), // src4.ready
|
|
.src4_valid (cmd_demux_002_src4_valid), // .valid
|
|
.src4_data (cmd_demux_002_src4_data), // .data
|
|
.src4_channel (cmd_demux_002_src4_channel), // .channel
|
|
.src4_startofpacket (cmd_demux_002_src4_startofpacket), // .startofpacket
|
|
.src4_endofpacket (cmd_demux_002_src4_endofpacket), // .endofpacket
|
|
.src5_ready (cmd_demux_002_src5_ready), // src5.ready
|
|
.src5_valid (cmd_demux_002_src5_valid), // .valid
|
|
.src5_data (cmd_demux_002_src5_data), // .data
|
|
.src5_channel (cmd_demux_002_src5_channel), // .channel
|
|
.src5_startofpacket (cmd_demux_002_src5_startofpacket), // .startofpacket
|
|
.src5_endofpacket (cmd_demux_002_src5_endofpacket), // .endofpacket
|
|
.src6_ready (cmd_demux_002_src6_ready), // src6.ready
|
|
.src6_valid (cmd_demux_002_src6_valid), // .valid
|
|
.src6_data (cmd_demux_002_src6_data), // .data
|
|
.src6_channel (cmd_demux_002_src6_channel), // .channel
|
|
.src6_startofpacket (cmd_demux_002_src6_startofpacket), // .startofpacket
|
|
.src6_endofpacket (cmd_demux_002_src6_endofpacket), // .endofpacket
|
|
.src7_ready (cmd_demux_002_src7_ready), // src7.ready
|
|
.src7_valid (cmd_demux_002_src7_valid), // .valid
|
|
.src7_data (cmd_demux_002_src7_data), // .data
|
|
.src7_channel (cmd_demux_002_src7_channel), // .channel
|
|
.src7_startofpacket (cmd_demux_002_src7_startofpacket), // .startofpacket
|
|
.src7_endofpacket (cmd_demux_002_src7_endofpacket), // .endofpacket
|
|
.src8_ready (cmd_demux_002_src8_ready), // src8.ready
|
|
.src8_valid (cmd_demux_002_src8_valid), // .valid
|
|
.src8_data (cmd_demux_002_src8_data), // .data
|
|
.src8_channel (cmd_demux_002_src8_channel), // .channel
|
|
.src8_startofpacket (cmd_demux_002_src8_startofpacket), // .startofpacket
|
|
.src8_endofpacket (cmd_demux_002_src8_endofpacket), // .endofpacket
|
|
.src9_ready (cmd_demux_002_src9_ready), // src9.ready
|
|
.src9_valid (cmd_demux_002_src9_valid), // .valid
|
|
.src9_data (cmd_demux_002_src9_data), // .data
|
|
.src9_channel (cmd_demux_002_src9_channel), // .channel
|
|
.src9_startofpacket (cmd_demux_002_src9_startofpacket), // .startofpacket
|
|
.src9_endofpacket (cmd_demux_002_src9_endofpacket), // .endofpacket
|
|
.src10_ready (cmd_demux_002_src10_ready), // src10.ready
|
|
.src10_valid (cmd_demux_002_src10_valid), // .valid
|
|
.src10_data (cmd_demux_002_src10_data), // .data
|
|
.src10_channel (cmd_demux_002_src10_channel), // .channel
|
|
.src10_startofpacket (cmd_demux_002_src10_startofpacket), // .startofpacket
|
|
.src10_endofpacket (cmd_demux_002_src10_endofpacket), // .endofpacket
|
|
.src11_ready (cmd_demux_002_src11_ready), // src11.ready
|
|
.src11_valid (cmd_demux_002_src11_valid), // .valid
|
|
.src11_data (cmd_demux_002_src11_data), // .data
|
|
.src11_channel (cmd_demux_002_src11_channel), // .channel
|
|
.src11_startofpacket (cmd_demux_002_src11_startofpacket), // .startofpacket
|
|
.src11_endofpacket (cmd_demux_002_src11_endofpacket), // .endofpacket
|
|
.src12_ready (cmd_demux_002_src12_ready), // src12.ready
|
|
.src12_valid (cmd_demux_002_src12_valid), // .valid
|
|
.src12_data (cmd_demux_002_src12_data), // .data
|
|
.src12_channel (cmd_demux_002_src12_channel), // .channel
|
|
.src12_startofpacket (cmd_demux_002_src12_startofpacket), // .startofpacket
|
|
.src12_endofpacket (cmd_demux_002_src12_endofpacket), // .endofpacket
|
|
.src13_ready (cmd_demux_002_src13_ready), // src13.ready
|
|
.src13_valid (cmd_demux_002_src13_valid), // .valid
|
|
.src13_data (cmd_demux_002_src13_data), // .data
|
|
.src13_channel (cmd_demux_002_src13_channel), // .channel
|
|
.src13_startofpacket (cmd_demux_002_src13_startofpacket), // .startofpacket
|
|
.src13_endofpacket (cmd_demux_002_src13_endofpacket), // .endofpacket
|
|
.src14_ready (cmd_demux_002_src14_ready), // src14.ready
|
|
.src14_valid (cmd_demux_002_src14_valid), // .valid
|
|
.src14_data (cmd_demux_002_src14_data), // .data
|
|
.src14_channel (cmd_demux_002_src14_channel), // .channel
|
|
.src14_startofpacket (cmd_demux_002_src14_startofpacket), // .startofpacket
|
|
.src14_endofpacket (cmd_demux_002_src14_endofpacket), // .endofpacket
|
|
.src15_ready (cmd_demux_002_src15_ready), // src15.ready
|
|
.src15_valid (cmd_demux_002_src15_valid), // .valid
|
|
.src15_data (cmd_demux_002_src15_data), // .data
|
|
.src15_channel (cmd_demux_002_src15_channel), // .channel
|
|
.src15_startofpacket (cmd_demux_002_src15_startofpacket), // .startofpacket
|
|
.src15_endofpacket (cmd_demux_002_src15_endofpacket), // .endofpacket
|
|
.src16_ready (cmd_demux_002_src16_ready), // src16.ready
|
|
.src16_valid (cmd_demux_002_src16_valid), // .valid
|
|
.src16_data (cmd_demux_002_src16_data), // .data
|
|
.src16_channel (cmd_demux_002_src16_channel), // .channel
|
|
.src16_startofpacket (cmd_demux_002_src16_startofpacket), // .startofpacket
|
|
.src16_endofpacket (cmd_demux_002_src16_endofpacket), // .endofpacket
|
|
.src17_ready (cmd_demux_002_src17_ready), // src17.ready
|
|
.src17_valid (cmd_demux_002_src17_valid), // .valid
|
|
.src17_data (cmd_demux_002_src17_data), // .data
|
|
.src17_channel (cmd_demux_002_src17_channel), // .channel
|
|
.src17_startofpacket (cmd_demux_002_src17_startofpacket), // .startofpacket
|
|
.src17_endofpacket (cmd_demux_002_src17_endofpacket), // .endofpacket
|
|
.src18_ready (cmd_demux_002_src18_ready), // src18.ready
|
|
.src18_valid (cmd_demux_002_src18_valid), // .valid
|
|
.src18_data (cmd_demux_002_src18_data), // .data
|
|
.src18_channel (cmd_demux_002_src18_channel), // .channel
|
|
.src18_startofpacket (cmd_demux_002_src18_startofpacket), // .startofpacket
|
|
.src18_endofpacket (cmd_demux_002_src18_endofpacket), // .endofpacket
|
|
.src19_ready (cmd_demux_002_src19_ready), // src19.ready
|
|
.src19_valid (cmd_demux_002_src19_valid), // .valid
|
|
.src19_data (cmd_demux_002_src19_data), // .data
|
|
.src19_channel (cmd_demux_002_src19_channel), // .channel
|
|
.src19_startofpacket (cmd_demux_002_src19_startofpacket), // .startofpacket
|
|
.src19_endofpacket (cmd_demux_002_src19_endofpacket), // .endofpacket
|
|
.src20_ready (cmd_demux_002_src20_ready), // src20.ready
|
|
.src20_valid (cmd_demux_002_src20_valid), // .valid
|
|
.src20_data (cmd_demux_002_src20_data), // .data
|
|
.src20_channel (cmd_demux_002_src20_channel), // .channel
|
|
.src20_startofpacket (cmd_demux_002_src20_startofpacket), // .startofpacket
|
|
.src20_endofpacket (cmd_demux_002_src20_endofpacket), // .endofpacket
|
|
.src21_ready (cmd_demux_002_src21_ready), // src21.ready
|
|
.src21_valid (cmd_demux_002_src21_valid), // .valid
|
|
.src21_data (cmd_demux_002_src21_data), // .data
|
|
.src21_channel (cmd_demux_002_src21_channel), // .channel
|
|
.src21_startofpacket (cmd_demux_002_src21_startofpacket), // .startofpacket
|
|
.src21_endofpacket (cmd_demux_002_src21_endofpacket), // .endofpacket
|
|
.src22_ready (cmd_demux_002_src22_ready), // src22.ready
|
|
.src22_valid (cmd_demux_002_src22_valid), // .valid
|
|
.src22_data (cmd_demux_002_src22_data), // .data
|
|
.src22_channel (cmd_demux_002_src22_channel), // .channel
|
|
.src22_startofpacket (cmd_demux_002_src22_startofpacket), // .startofpacket
|
|
.src22_endofpacket (cmd_demux_002_src22_endofpacket), // .endofpacket
|
|
.src23_ready (cmd_demux_002_src23_ready), // src23.ready
|
|
.src23_valid (cmd_demux_002_src23_valid), // .valid
|
|
.src23_data (cmd_demux_002_src23_data), // .data
|
|
.src23_channel (cmd_demux_002_src23_channel), // .channel
|
|
.src23_startofpacket (cmd_demux_002_src23_startofpacket), // .startofpacket
|
|
.src23_endofpacket (cmd_demux_002_src23_endofpacket), // .endofpacket
|
|
.src24_ready (cmd_demux_002_src24_ready), // src24.ready
|
|
.src24_valid (cmd_demux_002_src24_valid), // .valid
|
|
.src24_data (cmd_demux_002_src24_data), // .data
|
|
.src24_channel (cmd_demux_002_src24_channel), // .channel
|
|
.src24_startofpacket (cmd_demux_002_src24_startofpacket), // .startofpacket
|
|
.src24_endofpacket (cmd_demux_002_src24_endofpacket), // .endofpacket
|
|
.src25_ready (cmd_demux_002_src25_ready), // src25.ready
|
|
.src25_valid (cmd_demux_002_src25_valid), // .valid
|
|
.src25_data (cmd_demux_002_src25_data), // .data
|
|
.src25_channel (cmd_demux_002_src25_channel), // .channel
|
|
.src25_startofpacket (cmd_demux_002_src25_startofpacket), // .startofpacket
|
|
.src25_endofpacket (cmd_demux_002_src25_endofpacket), // .endofpacket
|
|
.src26_ready (cmd_demux_002_src26_ready), // src26.ready
|
|
.src26_valid (cmd_demux_002_src26_valid), // .valid
|
|
.src26_data (cmd_demux_002_src26_data), // .data
|
|
.src26_channel (cmd_demux_002_src26_channel), // .channel
|
|
.src26_startofpacket (cmd_demux_002_src26_startofpacket), // .startofpacket
|
|
.src26_endofpacket (cmd_demux_002_src26_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_demux_003 cmd_demux_003 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_003_src_ready), // sink.ready
|
|
.sink_channel (router_003_src_channel), // .channel
|
|
.sink_data (router_003_src_data), // .data
|
|
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_003_src_valid), // .valid
|
|
.src0_ready (cmd_demux_003_src0_ready), // src0.ready
|
|
.src0_valid (cmd_demux_003_src0_valid), // .valid
|
|
.src0_data (cmd_demux_003_src0_data), // .data
|
|
.src0_channel (cmd_demux_003_src0_channel), // .channel
|
|
.src0_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (cmd_demux_003_src0_endofpacket), // .endofpacket
|
|
.src1_ready (cmd_demux_003_src1_ready), // src1.ready
|
|
.src1_valid (cmd_demux_003_src1_valid), // .valid
|
|
.src1_data (cmd_demux_003_src1_data), // .data
|
|
.src1_channel (cmd_demux_003_src1_channel), // .channel
|
|
.src1_startofpacket (cmd_demux_003_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (cmd_demux_003_src1_endofpacket), // .endofpacket
|
|
.src2_ready (cmd_demux_003_src2_ready), // src2.ready
|
|
.src2_valid (cmd_demux_003_src2_valid), // .valid
|
|
.src2_data (cmd_demux_003_src2_data), // .data
|
|
.src2_channel (cmd_demux_003_src2_channel), // .channel
|
|
.src2_startofpacket (cmd_demux_003_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (cmd_demux_003_src2_endofpacket), // .endofpacket
|
|
.src3_ready (cmd_demux_003_src3_ready), // src3.ready
|
|
.src3_valid (cmd_demux_003_src3_valid), // .valid
|
|
.src3_data (cmd_demux_003_src3_data), // .data
|
|
.src3_channel (cmd_demux_003_src3_channel), // .channel
|
|
.src3_startofpacket (cmd_demux_003_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (cmd_demux_003_src3_endofpacket), // .endofpacket
|
|
.src4_ready (cmd_demux_003_src4_ready), // src4.ready
|
|
.src4_valid (cmd_demux_003_src4_valid), // .valid
|
|
.src4_data (cmd_demux_003_src4_data), // .data
|
|
.src4_channel (cmd_demux_003_src4_channel), // .channel
|
|
.src4_startofpacket (cmd_demux_003_src4_startofpacket), // .startofpacket
|
|
.src4_endofpacket (cmd_demux_003_src4_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_src_ready), // src.ready
|
|
.src_valid (cmd_mux_src_valid), // .valid
|
|
.src_data (cmd_mux_src_data), // .data
|
|
.src_channel (cmd_mux_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src0_valid), // .valid
|
|
.sink0_channel (cmd_demux_src0_channel), // .channel
|
|
.sink0_data (cmd_demux_src0_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src0_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src0_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src0_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src0_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src0_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src0_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_001 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_001_src_ready), // src.ready
|
|
.src_valid (cmd_mux_001_src_valid), // .valid
|
|
.src_data (cmd_mux_001_src_data), // .data
|
|
.src_channel (cmd_mux_001_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src1_valid), // .valid
|
|
.sink0_channel (cmd_demux_src1_channel), // .channel
|
|
.sink0_data (cmd_demux_src1_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src1_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src1_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src1_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src1_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src1_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src1_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src1_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_002 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_002_src_ready), // src.ready
|
|
.src_valid (cmd_mux_002_src_valid), // .valid
|
|
.src_data (cmd_mux_002_src_data), // .data
|
|
.src_channel (cmd_mux_002_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src2_valid), // .valid
|
|
.sink0_channel (cmd_demux_src2_channel), // .channel
|
|
.sink0_data (cmd_demux_src2_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src2_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src2_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src2_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src2_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src2_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src2_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src2_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_003 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_003_src_ready), // src.ready
|
|
.src_valid (cmd_mux_003_src_valid), // .valid
|
|
.src_data (cmd_mux_003_src_data), // .data
|
|
.src_channel (cmd_mux_003_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src3_valid), // .valid
|
|
.sink0_channel (cmd_demux_src3_channel), // .channel
|
|
.sink0_data (cmd_demux_src3_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src3_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src3_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src3_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src3_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src3_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src3_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src3_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src3_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src3_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_004 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_004_src_ready), // src.ready
|
|
.src_valid (cmd_mux_004_src_valid), // .valid
|
|
.src_data (cmd_mux_004_src_data), // .data
|
|
.src_channel (cmd_mux_004_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src4_valid), // .valid
|
|
.sink0_channel (cmd_demux_src4_channel), // .channel
|
|
.sink0_data (cmd_demux_src4_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src4_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src4_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src4_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src4_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src4_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src4_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src4_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src4_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src4_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src4_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_005 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_005_src_ready), // src.ready
|
|
.src_valid (cmd_mux_005_src_valid), // .valid
|
|
.src_data (cmd_mux_005_src_data), // .data
|
|
.src_channel (cmd_mux_005_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src5_valid), // .valid
|
|
.sink0_channel (cmd_demux_src5_channel), // .channel
|
|
.sink0_data (cmd_demux_src5_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src5_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src5_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src5_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src5_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src5_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_003_src0_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_003_src0_valid), // .valid
|
|
.sink2_channel (cmd_demux_003_src0_channel), // .channel
|
|
.sink2_data (cmd_demux_003_src0_data), // .data
|
|
.sink2_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_003_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_006 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_006_src_ready), // src.ready
|
|
.src_valid (cmd_mux_006_src_valid), // .valid
|
|
.src_data (cmd_mux_006_src_data), // .data
|
|
.src_channel (cmd_mux_006_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src6_valid), // .valid
|
|
.sink0_channel (cmd_demux_src6_channel), // .channel
|
|
.sink0_data (cmd_demux_src6_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src6_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src6_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src6_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src6_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src5_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src5_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src5_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src5_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src5_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src5_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_007 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_007_src_ready), // src.ready
|
|
.src_valid (cmd_mux_007_src_valid), // .valid
|
|
.src_data (cmd_mux_007_src_data), // .data
|
|
.src_channel (cmd_mux_007_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src7_valid), // .valid
|
|
.sink0_channel (cmd_demux_src7_channel), // .channel
|
|
.sink0_data (cmd_demux_src7_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src7_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src7_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src7_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src7_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src7_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src6_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src6_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src6_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src6_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src6_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src6_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_008 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_008_src_ready), // src.ready
|
|
.src_valid (cmd_mux_008_src_valid), // .valid
|
|
.src_data (cmd_mux_008_src_data), // .data
|
|
.src_channel (cmd_mux_008_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src8_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src8_valid), // .valid
|
|
.sink0_channel (cmd_demux_src8_channel), // .channel
|
|
.sink0_data (cmd_demux_src8_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src8_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src8_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src8_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src8_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src8_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src7_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src7_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src7_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src7_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src7_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src7_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_009 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_009_src_ready), // src.ready
|
|
.src_valid (cmd_mux_009_src_valid), // .valid
|
|
.src_data (cmd_mux_009_src_data), // .data
|
|
.src_channel (cmd_mux_009_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src9_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src9_valid), // .valid
|
|
.sink0_channel (cmd_demux_src9_channel), // .channel
|
|
.sink0_data (cmd_demux_src9_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src9_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src9_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src9_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src9_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src9_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src8_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src8_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src8_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src8_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src8_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src8_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_010 cmd_mux_010 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_010_src_ready), // src.ready
|
|
.src_valid (cmd_mux_010_src_valid), // .valid
|
|
.src_data (cmd_mux_010_src_data), // .data
|
|
.src_channel (cmd_mux_010_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src10_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src10_valid), // .valid
|
|
.sink0_channel (cmd_demux_src10_channel), // .channel
|
|
.sink0_data (cmd_demux_src10_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src10_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_011 cmd_mux_011 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_011_src_ready), // src.ready
|
|
.src_valid (cmd_mux_011_src_valid), // .valid
|
|
.src_data (cmd_mux_011_src_data), // .data
|
|
.src_channel (cmd_mux_011_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src11_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src11_valid), // .valid
|
|
.sink0_channel (cmd_demux_src11_channel), // .channel
|
|
.sink0_data (cmd_demux_src11_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src11_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src11_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src10_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src10_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src10_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src10_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src10_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src10_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src9_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src9_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src9_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src9_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src9_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src9_endofpacket), // .endofpacket
|
|
.sink3_ready (cmd_demux_003_src1_ready), // sink3.ready
|
|
.sink3_valid (cmd_demux_003_src1_valid), // .valid
|
|
.sink3_channel (cmd_demux_003_src1_channel), // .channel
|
|
.sink3_data (cmd_demux_003_src1_data), // .data
|
|
.sink3_startofpacket (cmd_demux_003_src1_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (cmd_demux_003_src1_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_011 cmd_mux_012 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_012_src_ready), // src.ready
|
|
.src_valid (cmd_mux_012_src_valid), // .valid
|
|
.src_data (cmd_mux_012_src_data), // .data
|
|
.src_channel (cmd_mux_012_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src12_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src12_valid), // .valid
|
|
.sink0_channel (cmd_demux_src12_channel), // .channel
|
|
.sink0_data (cmd_demux_src12_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src12_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src12_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src11_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src11_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src11_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src11_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src11_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src11_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src10_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src10_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src10_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src10_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src10_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src10_endofpacket), // .endofpacket
|
|
.sink3_ready (cmd_demux_003_src2_ready), // sink3.ready
|
|
.sink3_valid (cmd_demux_003_src2_valid), // .valid
|
|
.sink3_channel (cmd_demux_003_src2_channel), // .channel
|
|
.sink3_data (cmd_demux_003_src2_data), // .data
|
|
.sink3_startofpacket (cmd_demux_003_src2_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (cmd_demux_003_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_011 cmd_mux_013 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_013_src_ready), // src.ready
|
|
.src_valid (cmd_mux_013_src_valid), // .valid
|
|
.src_data (cmd_mux_013_src_data), // .data
|
|
.src_channel (cmd_mux_013_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src13_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src13_valid), // .valid
|
|
.sink0_channel (cmd_demux_src13_channel), // .channel
|
|
.sink0_data (cmd_demux_src13_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src13_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src13_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src12_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src12_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src12_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src12_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src12_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src12_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src11_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src11_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src11_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src11_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src11_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src11_endofpacket), // .endofpacket
|
|
.sink3_ready (cmd_demux_003_src3_ready), // sink3.ready
|
|
.sink3_valid (cmd_demux_003_src3_valid), // .valid
|
|
.sink3_channel (cmd_demux_003_src3_channel), // .channel
|
|
.sink3_data (cmd_demux_003_src3_data), // .data
|
|
.sink3_startofpacket (cmd_demux_003_src3_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (cmd_demux_003_src3_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_011 cmd_mux_014 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_014_src_ready), // src.ready
|
|
.src_valid (cmd_mux_014_src_valid), // .valid
|
|
.src_data (cmd_mux_014_src_data), // .data
|
|
.src_channel (cmd_mux_014_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src14_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src14_valid), // .valid
|
|
.sink0_channel (cmd_demux_src14_channel), // .channel
|
|
.sink0_data (cmd_demux_src14_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src14_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src14_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src13_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src13_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src13_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src13_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src13_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src13_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src12_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src12_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src12_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src12_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src12_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src12_endofpacket), // .endofpacket
|
|
.sink3_ready (cmd_demux_003_src4_ready), // sink3.ready
|
|
.sink3_valid (cmd_demux_003_src4_valid), // .valid
|
|
.sink3_channel (cmd_demux_003_src4_channel), // .channel
|
|
.sink3_data (cmd_demux_003_src4_data), // .data
|
|
.sink3_startofpacket (cmd_demux_003_src4_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (cmd_demux_003_src4_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_015 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_015_src_ready), // src.ready
|
|
.src_valid (cmd_mux_015_src_valid), // .valid
|
|
.src_data (cmd_mux_015_src_data), // .data
|
|
.src_channel (cmd_mux_015_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src15_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src15_valid), // .valid
|
|
.sink0_channel (cmd_demux_src15_channel), // .channel
|
|
.sink0_data (cmd_demux_src15_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src15_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src15_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src14_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src14_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src14_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src14_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src14_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src14_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src13_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src13_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src13_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src13_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src13_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src13_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_016 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_016_src_ready), // src.ready
|
|
.src_valid (cmd_mux_016_src_valid), // .valid
|
|
.src_data (cmd_mux_016_src_data), // .data
|
|
.src_channel (cmd_mux_016_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src16_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src16_valid), // .valid
|
|
.sink0_channel (cmd_demux_src16_channel), // .channel
|
|
.sink0_data (cmd_demux_src16_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src16_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src16_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src15_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src15_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src15_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src15_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src15_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src15_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src14_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src14_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src14_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src14_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src14_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src14_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_017 cmd_mux_017 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_017_src_ready), // src.ready
|
|
.src_valid (cmd_mux_017_src_valid), // .valid
|
|
.src_data (cmd_mux_017_src_data), // .data
|
|
.src_channel (cmd_mux_017_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src17_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src17_valid), // .valid
|
|
.sink0_channel (cmd_demux_src17_channel), // .channel
|
|
.sink0_data (cmd_demux_src17_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src17_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src17_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src16_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src16_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src16_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src16_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src16_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src16_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_017 cmd_mux_018 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_018_src_ready), // src.ready
|
|
.src_valid (cmd_mux_018_src_valid), // .valid
|
|
.src_data (cmd_mux_018_src_data), // .data
|
|
.src_channel (cmd_mux_018_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src18_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src18_valid), // .valid
|
|
.sink0_channel (cmd_demux_src18_channel), // .channel
|
|
.sink0_data (cmd_demux_src18_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src18_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src18_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src17_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src17_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src17_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src17_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src17_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src17_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_019 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_019_src_ready), // src.ready
|
|
.src_valid (cmd_mux_019_src_valid), // .valid
|
|
.src_data (cmd_mux_019_src_data), // .data
|
|
.src_channel (cmd_mux_019_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src19_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src19_valid), // .valid
|
|
.sink0_channel (cmd_demux_src19_channel), // .channel
|
|
.sink0_data (cmd_demux_src19_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src19_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src19_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src18_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src18_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src18_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src18_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src18_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src18_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src15_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src15_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src15_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src15_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src15_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src15_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_020 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_020_src_ready), // src.ready
|
|
.src_valid (cmd_mux_020_src_valid), // .valid
|
|
.src_data (cmd_mux_020_src_data), // .data
|
|
.src_channel (cmd_mux_020_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src20_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src20_valid), // .valid
|
|
.sink0_channel (cmd_demux_src20_channel), // .channel
|
|
.sink0_data (cmd_demux_src20_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src20_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src20_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src19_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src19_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src19_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src19_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src19_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src19_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src16_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src16_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src16_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src16_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src16_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src16_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_021 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_021_src_ready), // src.ready
|
|
.src_valid (cmd_mux_021_src_valid), // .valid
|
|
.src_data (cmd_mux_021_src_data), // .data
|
|
.src_channel (cmd_mux_021_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src21_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src21_valid), // .valid
|
|
.sink0_channel (cmd_demux_src21_channel), // .channel
|
|
.sink0_data (cmd_demux_src21_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src21_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src21_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src20_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src20_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src20_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src20_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src20_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src20_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src17_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src17_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src17_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src17_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src17_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src17_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_022 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_022_src_ready), // src.ready
|
|
.src_valid (cmd_mux_022_src_valid), // .valid
|
|
.src_data (cmd_mux_022_src_data), // .data
|
|
.src_channel (cmd_mux_022_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src22_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src22_valid), // .valid
|
|
.sink0_channel (cmd_demux_src22_channel), // .channel
|
|
.sink0_data (cmd_demux_src22_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src22_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src22_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src21_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src21_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src21_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src21_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src21_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src21_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src18_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src18_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src18_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src18_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src18_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src18_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_023 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_023_src_ready), // src.ready
|
|
.src_valid (cmd_mux_023_src_valid), // .valid
|
|
.src_data (cmd_mux_023_src_data), // .data
|
|
.src_channel (cmd_mux_023_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_023_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_023_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src23_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src23_valid), // .valid
|
|
.sink0_channel (cmd_demux_src23_channel), // .channel
|
|
.sink0_data (cmd_demux_src23_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src23_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src23_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src22_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src22_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src22_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src22_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src22_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src22_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src19_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src19_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src19_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src19_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src19_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src19_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_024 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_024_src_ready), // src.ready
|
|
.src_valid (cmd_mux_024_src_valid), // .valid
|
|
.src_data (cmd_mux_024_src_data), // .data
|
|
.src_channel (cmd_mux_024_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_024_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_024_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src24_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src24_valid), // .valid
|
|
.sink0_channel (cmd_demux_src24_channel), // .channel
|
|
.sink0_data (cmd_demux_src24_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src24_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src24_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src23_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src23_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src23_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src23_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src23_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src23_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src20_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src20_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src20_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src20_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src20_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src20_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_017 cmd_mux_025 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_025_src_ready), // src.ready
|
|
.src_valid (cmd_mux_025_src_valid), // .valid
|
|
.src_data (cmd_mux_025_src_data), // .data
|
|
.src_channel (cmd_mux_025_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_025_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_025_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src25_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src25_valid), // .valid
|
|
.sink0_channel (cmd_demux_src25_channel), // .channel
|
|
.sink0_data (cmd_demux_src25_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src25_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src25_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src24_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src24_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src24_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src24_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src24_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src24_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_026 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_026_src_ready), // src.ready
|
|
.src_valid (cmd_mux_026_src_valid), // .valid
|
|
.src_data (cmd_mux_026_src_data), // .data
|
|
.src_channel (cmd_mux_026_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_026_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_026_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src26_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src26_valid), // .valid
|
|
.sink0_channel (cmd_demux_src26_channel), // .channel
|
|
.sink0_data (cmd_demux_src26_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src26_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src26_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src25_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src25_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src25_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src25_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src25_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src25_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src21_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src21_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src21_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src21_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src21_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src21_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_027 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_027_src_ready), // src.ready
|
|
.src_valid (cmd_mux_027_src_valid), // .valid
|
|
.src_data (cmd_mux_027_src_data), // .data
|
|
.src_channel (cmd_mux_027_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_027_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_027_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src27_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src27_valid), // .valid
|
|
.sink0_channel (cmd_demux_src27_channel), // .channel
|
|
.sink0_data (cmd_demux_src27_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src27_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src27_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src26_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src26_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src26_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src26_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src26_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src26_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src22_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src22_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src22_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src22_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src22_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src22_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_028 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_028_src_ready), // src.ready
|
|
.src_valid (cmd_mux_028_src_valid), // .valid
|
|
.src_data (cmd_mux_028_src_data), // .data
|
|
.src_channel (cmd_mux_028_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_028_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_028_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src28_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src28_valid), // .valid
|
|
.sink0_channel (cmd_demux_src28_channel), // .channel
|
|
.sink0_data (cmd_demux_src28_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src28_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src28_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src27_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src27_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src27_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src27_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src27_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src27_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src23_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src23_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src23_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src23_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src23_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src23_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_029 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_029_src_ready), // src.ready
|
|
.src_valid (cmd_mux_029_src_valid), // .valid
|
|
.src_data (cmd_mux_029_src_data), // .data
|
|
.src_channel (cmd_mux_029_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_029_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_029_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src29_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src29_valid), // .valid
|
|
.sink0_channel (cmd_demux_src29_channel), // .channel
|
|
.sink0_data (cmd_demux_src29_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src29_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src29_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src28_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src28_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src28_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src28_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src28_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src28_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src24_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src24_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src24_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src24_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src24_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src24_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_030 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_030_src_ready), // src.ready
|
|
.src_valid (cmd_mux_030_src_valid), // .valid
|
|
.src_data (cmd_mux_030_src_data), // .data
|
|
.src_channel (cmd_mux_030_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_030_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_030_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src30_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src30_valid), // .valid
|
|
.sink0_channel (cmd_demux_src30_channel), // .channel
|
|
.sink0_data (cmd_demux_src30_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src30_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src30_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src29_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src29_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src29_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src29_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src29_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src29_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src25_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src25_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src25_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src25_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src25_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src25_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_010 cmd_mux_031 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_031_src_ready), // src.ready
|
|
.src_valid (cmd_mux_031_src_valid), // .valid
|
|
.src_data (cmd_mux_031_src_data), // .data
|
|
.src_channel (cmd_mux_031_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_031_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_031_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src31_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src31_valid), // .valid
|
|
.sink0_channel (cmd_demux_src31_channel), // .channel
|
|
.sink0_data (cmd_demux_src31_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src31_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src31_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux_010 cmd_mux_032 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_032_src_ready), // src.ready
|
|
.src_valid (cmd_mux_032_src_valid), // .valid
|
|
.src_data (cmd_mux_032_src_data), // .data
|
|
.src_channel (cmd_mux_032_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_032_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_032_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src32_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src32_valid), // .valid
|
|
.sink0_channel (cmd_demux_src32_channel), // .channel
|
|
.sink0_data (cmd_demux_src32_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src32_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src32_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_cmd_mux cmd_mux_033 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (cmd_mux_033_src_ready), // src.ready
|
|
.src_valid (cmd_mux_033_src_valid), // .valid
|
|
.src_data (cmd_mux_033_src_data), // .data
|
|
.src_channel (cmd_mux_033_src_channel), // .channel
|
|
.src_startofpacket (cmd_mux_033_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (cmd_mux_033_src_endofpacket), // .endofpacket
|
|
.sink0_ready (cmd_demux_src33_ready), // sink0.ready
|
|
.sink0_valid (cmd_demux_src33_valid), // .valid
|
|
.sink0_channel (cmd_demux_src33_channel), // .channel
|
|
.sink0_data (cmd_demux_src33_data), // .data
|
|
.sink0_startofpacket (cmd_demux_src33_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (cmd_demux_src33_endofpacket), // .endofpacket
|
|
.sink1_ready (cmd_demux_001_src30_ready), // sink1.ready
|
|
.sink1_valid (cmd_demux_001_src30_valid), // .valid
|
|
.sink1_channel (cmd_demux_001_src30_channel), // .channel
|
|
.sink1_data (cmd_demux_001_src30_data), // .data
|
|
.sink1_startofpacket (cmd_demux_001_src30_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (cmd_demux_001_src30_endofpacket), // .endofpacket
|
|
.sink2_ready (cmd_demux_002_src26_ready), // sink2.ready
|
|
.sink2_valid (cmd_demux_002_src26_valid), // .valid
|
|
.sink2_channel (cmd_demux_002_src26_channel), // .channel
|
|
.sink2_data (cmd_demux_002_src26_data), // .data
|
|
.sink2_startofpacket (cmd_demux_002_src26_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (cmd_demux_002_src26_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_004_src_ready), // sink.ready
|
|
.sink_channel (router_004_src_channel), // .channel
|
|
.sink_data (router_004_src_data), // .data
|
|
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_004_src_valid), // .valid
|
|
.src0_ready (rsp_demux_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_src0_valid), // .valid
|
|
.src0_data (rsp_demux_src0_data), // .data
|
|
.src0_channel (rsp_demux_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_src1_valid), // .valid
|
|
.src1_data (rsp_demux_src1_data), // .data
|
|
.src1_channel (rsp_demux_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_src2_valid), // .valid
|
|
.src2_data (rsp_demux_src2_data), // .data
|
|
.src2_channel (rsp_demux_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_001 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_005_src_ready), // sink.ready
|
|
.sink_channel (router_005_src_channel), // .channel
|
|
.sink_data (router_005_src_data), // .data
|
|
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_005_src_valid), // .valid
|
|
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_001_src0_valid), // .valid
|
|
.src0_data (rsp_demux_001_src0_data), // .data
|
|
.src0_channel (rsp_demux_001_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_001_src1_valid), // .valid
|
|
.src1_data (rsp_demux_001_src1_data), // .data
|
|
.src1_channel (rsp_demux_001_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_001_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_001_src2_valid), // .valid
|
|
.src2_data (rsp_demux_001_src2_data), // .data
|
|
.src2_channel (rsp_demux_001_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_002 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_006_src_ready), // sink.ready
|
|
.sink_channel (router_006_src_channel), // .channel
|
|
.sink_data (router_006_src_data), // .data
|
|
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_006_src_valid), // .valid
|
|
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_002_src0_valid), // .valid
|
|
.src0_data (rsp_demux_002_src0_data), // .data
|
|
.src0_channel (rsp_demux_002_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_002_src1_valid), // .valid
|
|
.src1_data (rsp_demux_002_src1_data), // .data
|
|
.src1_channel (rsp_demux_002_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_002_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_002_src2_valid), // .valid
|
|
.src2_data (rsp_demux_002_src2_data), // .data
|
|
.src2_channel (rsp_demux_002_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_002_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_002_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_003 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (sram_multiplexer_avl_rsp_width_adapter_src_ready), // sink.ready
|
|
.sink_channel (sram_multiplexer_avl_rsp_width_adapter_src_channel), // .channel
|
|
.sink_data (sram_multiplexer_avl_rsp_width_adapter_src_data), // .data
|
|
.sink_startofpacket (sram_multiplexer_avl_rsp_width_adapter_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (sram_multiplexer_avl_rsp_width_adapter_src_endofpacket), // .endofpacket
|
|
.sink_valid (sram_multiplexer_avl_rsp_width_adapter_src_valid), // .valid
|
|
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_003_src0_valid), // .valid
|
|
.src0_data (rsp_demux_003_src0_data), // .data
|
|
.src0_channel (rsp_demux_003_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_003_src1_valid), // .valid
|
|
.src1_data (rsp_demux_003_src1_data), // .data
|
|
.src1_channel (rsp_demux_003_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_003_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_003_src2_valid), // .valid
|
|
.src2_data (rsp_demux_003_src2_data), // .data
|
|
.src2_channel (rsp_demux_003_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_003_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_003_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_004 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_008_src_ready), // sink.ready
|
|
.sink_channel (router_008_src_channel), // .channel
|
|
.sink_data (router_008_src_data), // .data
|
|
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_008_src_valid), // .valid
|
|
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_004_src0_valid), // .valid
|
|
.src0_data (rsp_demux_004_src0_data), // .data
|
|
.src0_channel (rsp_demux_004_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_004_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_004_src1_valid), // .valid
|
|
.src1_data (rsp_demux_004_src1_data), // .data
|
|
.src1_channel (rsp_demux_004_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_004_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_004_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_004_src2_valid), // .valid
|
|
.src2_data (rsp_demux_004_src2_data), // .data
|
|
.src2_channel (rsp_demux_004_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_004_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_004_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_005 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_009_src_ready), // sink.ready
|
|
.sink_channel (router_009_src_channel), // .channel
|
|
.sink_data (router_009_src_data), // .data
|
|
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_009_src_valid), // .valid
|
|
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_005_src0_valid), // .valid
|
|
.src0_data (rsp_demux_005_src0_data), // .data
|
|
.src0_channel (rsp_demux_005_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_005_src1_valid), // .valid
|
|
.src1_data (rsp_demux_005_src1_data), // .data
|
|
.src1_channel (rsp_demux_005_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_005_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_005_src2_valid), // .valid
|
|
.src2_data (rsp_demux_005_src2_data), // .data
|
|
.src2_channel (rsp_demux_005_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_005_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_005_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_006 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_010_src_ready), // sink.ready
|
|
.sink_channel (router_010_src_channel), // .channel
|
|
.sink_data (router_010_src_data), // .data
|
|
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_010_src_valid), // .valid
|
|
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_006_src0_valid), // .valid
|
|
.src0_data (rsp_demux_006_src0_data), // .data
|
|
.src0_channel (rsp_demux_006_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_006_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_006_src1_valid), // .valid
|
|
.src1_data (rsp_demux_006_src1_data), // .data
|
|
.src1_channel (rsp_demux_006_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_006_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_006_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_006_src2_valid), // .valid
|
|
.src2_data (rsp_demux_006_src2_data), // .data
|
|
.src2_channel (rsp_demux_006_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_006_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_006_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_007 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_011_src_ready), // sink.ready
|
|
.sink_channel (router_011_src_channel), // .channel
|
|
.sink_data (router_011_src_data), // .data
|
|
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_011_src_valid), // .valid
|
|
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_007_src0_valid), // .valid
|
|
.src0_data (rsp_demux_007_src0_data), // .data
|
|
.src0_channel (rsp_demux_007_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_007_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_007_src1_valid), // .valid
|
|
.src1_data (rsp_demux_007_src1_data), // .data
|
|
.src1_channel (rsp_demux_007_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_007_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_007_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_007_src2_valid), // .valid
|
|
.src2_data (rsp_demux_007_src2_data), // .data
|
|
.src2_channel (rsp_demux_007_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_007_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_007_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_008 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_012_src_ready), // sink.ready
|
|
.sink_channel (router_012_src_channel), // .channel
|
|
.sink_data (router_012_src_data), // .data
|
|
.sink_startofpacket (router_012_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_012_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_012_src_valid), // .valid
|
|
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_008_src0_valid), // .valid
|
|
.src0_data (rsp_demux_008_src0_data), // .data
|
|
.src0_channel (rsp_demux_008_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_008_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_008_src1_valid), // .valid
|
|
.src1_data (rsp_demux_008_src1_data), // .data
|
|
.src1_channel (rsp_demux_008_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_008_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_008_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_008_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_008_src2_valid), // .valid
|
|
.src2_data (rsp_demux_008_src2_data), // .data
|
|
.src2_channel (rsp_demux_008_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_008_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_008_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_009 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_013_src_ready), // sink.ready
|
|
.sink_channel (router_013_src_channel), // .channel
|
|
.sink_data (router_013_src_data), // .data
|
|
.sink_startofpacket (router_013_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_013_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_013_src_valid), // .valid
|
|
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_009_src0_valid), // .valid
|
|
.src0_data (rsp_demux_009_src0_data), // .data
|
|
.src0_channel (rsp_demux_009_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_009_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_009_src1_valid), // .valid
|
|
.src1_data (rsp_demux_009_src1_data), // .data
|
|
.src1_channel (rsp_demux_009_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_009_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_009_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_009_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_009_src2_valid), // .valid
|
|
.src2_data (rsp_demux_009_src2_data), // .data
|
|
.src2_channel (rsp_demux_009_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_009_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_009_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_010 rsp_demux_010 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_014_src_ready), // sink.ready
|
|
.sink_channel (router_014_src_channel), // .channel
|
|
.sink_data (router_014_src_data), // .data
|
|
.sink_startofpacket (router_014_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_014_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_014_src_valid), // .valid
|
|
.src0_ready (rsp_demux_010_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_010_src0_valid), // .valid
|
|
.src0_data (rsp_demux_010_src0_data), // .data
|
|
.src0_channel (rsp_demux_010_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_010_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_011 rsp_demux_011 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_015_src_ready), // sink.ready
|
|
.sink_channel (router_015_src_channel), // .channel
|
|
.sink_data (router_015_src_data), // .data
|
|
.sink_startofpacket (router_015_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_015_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_015_src_valid), // .valid
|
|
.src0_ready (rsp_demux_011_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_011_src0_valid), // .valid
|
|
.src0_data (rsp_demux_011_src0_data), // .data
|
|
.src0_channel (rsp_demux_011_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_011_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_011_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_011_src1_valid), // .valid
|
|
.src1_data (rsp_demux_011_src1_data), // .data
|
|
.src1_channel (rsp_demux_011_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_011_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_011_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_011_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_011_src2_valid), // .valid
|
|
.src2_data (rsp_demux_011_src2_data), // .data
|
|
.src2_channel (rsp_demux_011_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_011_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_011_src2_endofpacket), // .endofpacket
|
|
.src3_ready (rsp_demux_011_src3_ready), // src3.ready
|
|
.src3_valid (rsp_demux_011_src3_valid), // .valid
|
|
.src3_data (rsp_demux_011_src3_data), // .data
|
|
.src3_channel (rsp_demux_011_src3_channel), // .channel
|
|
.src3_startofpacket (rsp_demux_011_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (rsp_demux_011_src3_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_011 rsp_demux_012 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_016_src_ready), // sink.ready
|
|
.sink_channel (router_016_src_channel), // .channel
|
|
.sink_data (router_016_src_data), // .data
|
|
.sink_startofpacket (router_016_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_016_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_016_src_valid), // .valid
|
|
.src0_ready (rsp_demux_012_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_012_src0_valid), // .valid
|
|
.src0_data (rsp_demux_012_src0_data), // .data
|
|
.src0_channel (rsp_demux_012_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_012_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_012_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_012_src1_valid), // .valid
|
|
.src1_data (rsp_demux_012_src1_data), // .data
|
|
.src1_channel (rsp_demux_012_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_012_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_012_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_012_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_012_src2_valid), // .valid
|
|
.src2_data (rsp_demux_012_src2_data), // .data
|
|
.src2_channel (rsp_demux_012_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_012_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_012_src2_endofpacket), // .endofpacket
|
|
.src3_ready (rsp_demux_012_src3_ready), // src3.ready
|
|
.src3_valid (rsp_demux_012_src3_valid), // .valid
|
|
.src3_data (rsp_demux_012_src3_data), // .data
|
|
.src3_channel (rsp_demux_012_src3_channel), // .channel
|
|
.src3_startofpacket (rsp_demux_012_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (rsp_demux_012_src3_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_011 rsp_demux_013 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_017_src_ready), // sink.ready
|
|
.sink_channel (router_017_src_channel), // .channel
|
|
.sink_data (router_017_src_data), // .data
|
|
.sink_startofpacket (router_017_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_017_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_017_src_valid), // .valid
|
|
.src0_ready (rsp_demux_013_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_013_src0_valid), // .valid
|
|
.src0_data (rsp_demux_013_src0_data), // .data
|
|
.src0_channel (rsp_demux_013_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_013_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_013_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_013_src1_valid), // .valid
|
|
.src1_data (rsp_demux_013_src1_data), // .data
|
|
.src1_channel (rsp_demux_013_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_013_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_013_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_013_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_013_src2_valid), // .valid
|
|
.src2_data (rsp_demux_013_src2_data), // .data
|
|
.src2_channel (rsp_demux_013_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_013_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_013_src2_endofpacket), // .endofpacket
|
|
.src3_ready (rsp_demux_013_src3_ready), // src3.ready
|
|
.src3_valid (rsp_demux_013_src3_valid), // .valid
|
|
.src3_data (rsp_demux_013_src3_data), // .data
|
|
.src3_channel (rsp_demux_013_src3_channel), // .channel
|
|
.src3_startofpacket (rsp_demux_013_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (rsp_demux_013_src3_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_011 rsp_demux_014 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_018_src_ready), // sink.ready
|
|
.sink_channel (router_018_src_channel), // .channel
|
|
.sink_data (router_018_src_data), // .data
|
|
.sink_startofpacket (router_018_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_018_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_018_src_valid), // .valid
|
|
.src0_ready (rsp_demux_014_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_014_src0_valid), // .valid
|
|
.src0_data (rsp_demux_014_src0_data), // .data
|
|
.src0_channel (rsp_demux_014_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_014_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_014_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_014_src1_valid), // .valid
|
|
.src1_data (rsp_demux_014_src1_data), // .data
|
|
.src1_channel (rsp_demux_014_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_014_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_014_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_014_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_014_src2_valid), // .valid
|
|
.src2_data (rsp_demux_014_src2_data), // .data
|
|
.src2_channel (rsp_demux_014_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_014_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_014_src2_endofpacket), // .endofpacket
|
|
.src3_ready (rsp_demux_014_src3_ready), // src3.ready
|
|
.src3_valid (rsp_demux_014_src3_valid), // .valid
|
|
.src3_data (rsp_demux_014_src3_data), // .data
|
|
.src3_channel (rsp_demux_014_src3_channel), // .channel
|
|
.src3_startofpacket (rsp_demux_014_src3_startofpacket), // .startofpacket
|
|
.src3_endofpacket (rsp_demux_014_src3_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_015 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_019_src_ready), // sink.ready
|
|
.sink_channel (router_019_src_channel), // .channel
|
|
.sink_data (router_019_src_data), // .data
|
|
.sink_startofpacket (router_019_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_019_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_019_src_valid), // .valid
|
|
.src0_ready (rsp_demux_015_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_015_src0_valid), // .valid
|
|
.src0_data (rsp_demux_015_src0_data), // .data
|
|
.src0_channel (rsp_demux_015_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_015_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_015_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_015_src1_valid), // .valid
|
|
.src1_data (rsp_demux_015_src1_data), // .data
|
|
.src1_channel (rsp_demux_015_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_015_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_015_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_015_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_015_src2_valid), // .valid
|
|
.src2_data (rsp_demux_015_src2_data), // .data
|
|
.src2_channel (rsp_demux_015_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_015_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_015_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_016 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_020_src_ready), // sink.ready
|
|
.sink_channel (router_020_src_channel), // .channel
|
|
.sink_data (router_020_src_data), // .data
|
|
.sink_startofpacket (router_020_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_020_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_020_src_valid), // .valid
|
|
.src0_ready (rsp_demux_016_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_016_src0_valid), // .valid
|
|
.src0_data (rsp_demux_016_src0_data), // .data
|
|
.src0_channel (rsp_demux_016_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_016_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_016_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_016_src1_valid), // .valid
|
|
.src1_data (rsp_demux_016_src1_data), // .data
|
|
.src1_channel (rsp_demux_016_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_016_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_016_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_016_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_016_src2_valid), // .valid
|
|
.src2_data (rsp_demux_016_src2_data), // .data
|
|
.src2_channel (rsp_demux_016_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_016_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_016_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_017 rsp_demux_017 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_021_src_ready), // sink.ready
|
|
.sink_channel (router_021_src_channel), // .channel
|
|
.sink_data (router_021_src_data), // .data
|
|
.sink_startofpacket (router_021_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_021_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_021_src_valid), // .valid
|
|
.src0_ready (rsp_demux_017_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_017_src0_valid), // .valid
|
|
.src0_data (rsp_demux_017_src0_data), // .data
|
|
.src0_channel (rsp_demux_017_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_017_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_017_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_017_src1_valid), // .valid
|
|
.src1_data (rsp_demux_017_src1_data), // .data
|
|
.src1_channel (rsp_demux_017_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_017_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_017_src1_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_017 rsp_demux_018 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_022_src_ready), // sink.ready
|
|
.sink_channel (router_022_src_channel), // .channel
|
|
.sink_data (router_022_src_data), // .data
|
|
.sink_startofpacket (router_022_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_022_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_022_src_valid), // .valid
|
|
.src0_ready (rsp_demux_018_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_018_src0_valid), // .valid
|
|
.src0_data (rsp_demux_018_src0_data), // .data
|
|
.src0_channel (rsp_demux_018_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_018_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_018_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_018_src1_valid), // .valid
|
|
.src1_data (rsp_demux_018_src1_data), // .data
|
|
.src1_channel (rsp_demux_018_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_018_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_018_src1_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_019 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_023_src_ready), // sink.ready
|
|
.sink_channel (router_023_src_channel), // .channel
|
|
.sink_data (router_023_src_data), // .data
|
|
.sink_startofpacket (router_023_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_023_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_023_src_valid), // .valid
|
|
.src0_ready (rsp_demux_019_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_019_src0_valid), // .valid
|
|
.src0_data (rsp_demux_019_src0_data), // .data
|
|
.src0_channel (rsp_demux_019_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_019_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_019_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_019_src1_valid), // .valid
|
|
.src1_data (rsp_demux_019_src1_data), // .data
|
|
.src1_channel (rsp_demux_019_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_019_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_019_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_019_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_019_src2_valid), // .valid
|
|
.src2_data (rsp_demux_019_src2_data), // .data
|
|
.src2_channel (rsp_demux_019_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_019_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_019_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_020 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_024_src_ready), // sink.ready
|
|
.sink_channel (router_024_src_channel), // .channel
|
|
.sink_data (router_024_src_data), // .data
|
|
.sink_startofpacket (router_024_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_024_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_024_src_valid), // .valid
|
|
.src0_ready (rsp_demux_020_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_020_src0_valid), // .valid
|
|
.src0_data (rsp_demux_020_src0_data), // .data
|
|
.src0_channel (rsp_demux_020_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_020_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_020_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_020_src1_valid), // .valid
|
|
.src1_data (rsp_demux_020_src1_data), // .data
|
|
.src1_channel (rsp_demux_020_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_020_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_020_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_020_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_020_src2_valid), // .valid
|
|
.src2_data (rsp_demux_020_src2_data), // .data
|
|
.src2_channel (rsp_demux_020_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_020_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_020_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_021 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_025_src_ready), // sink.ready
|
|
.sink_channel (router_025_src_channel), // .channel
|
|
.sink_data (router_025_src_data), // .data
|
|
.sink_startofpacket (router_025_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_025_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_025_src_valid), // .valid
|
|
.src0_ready (rsp_demux_021_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_021_src0_valid), // .valid
|
|
.src0_data (rsp_demux_021_src0_data), // .data
|
|
.src0_channel (rsp_demux_021_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_021_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_021_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_021_src1_valid), // .valid
|
|
.src1_data (rsp_demux_021_src1_data), // .data
|
|
.src1_channel (rsp_demux_021_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_021_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_021_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_021_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_021_src2_valid), // .valid
|
|
.src2_data (rsp_demux_021_src2_data), // .data
|
|
.src2_channel (rsp_demux_021_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_021_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_021_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_022 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_026_src_ready), // sink.ready
|
|
.sink_channel (router_026_src_channel), // .channel
|
|
.sink_data (router_026_src_data), // .data
|
|
.sink_startofpacket (router_026_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_026_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_026_src_valid), // .valid
|
|
.src0_ready (rsp_demux_022_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_022_src0_valid), // .valid
|
|
.src0_data (rsp_demux_022_src0_data), // .data
|
|
.src0_channel (rsp_demux_022_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_022_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_022_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_022_src1_valid), // .valid
|
|
.src1_data (rsp_demux_022_src1_data), // .data
|
|
.src1_channel (rsp_demux_022_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_022_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_022_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_022_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_022_src2_valid), // .valid
|
|
.src2_data (rsp_demux_022_src2_data), // .data
|
|
.src2_channel (rsp_demux_022_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_022_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_022_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_023 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_027_src_ready), // sink.ready
|
|
.sink_channel (router_027_src_channel), // .channel
|
|
.sink_data (router_027_src_data), // .data
|
|
.sink_startofpacket (router_027_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_027_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_027_src_valid), // .valid
|
|
.src0_ready (rsp_demux_023_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_023_src0_valid), // .valid
|
|
.src0_data (rsp_demux_023_src0_data), // .data
|
|
.src0_channel (rsp_demux_023_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_023_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_023_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_023_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_023_src1_valid), // .valid
|
|
.src1_data (rsp_demux_023_src1_data), // .data
|
|
.src1_channel (rsp_demux_023_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_023_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_023_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_023_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_023_src2_valid), // .valid
|
|
.src2_data (rsp_demux_023_src2_data), // .data
|
|
.src2_channel (rsp_demux_023_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_023_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_023_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_024 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_028_src_ready), // sink.ready
|
|
.sink_channel (router_028_src_channel), // .channel
|
|
.sink_data (router_028_src_data), // .data
|
|
.sink_startofpacket (router_028_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_028_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_028_src_valid), // .valid
|
|
.src0_ready (rsp_demux_024_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_024_src0_valid), // .valid
|
|
.src0_data (rsp_demux_024_src0_data), // .data
|
|
.src0_channel (rsp_demux_024_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_024_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_024_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_024_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_024_src1_valid), // .valid
|
|
.src1_data (rsp_demux_024_src1_data), // .data
|
|
.src1_channel (rsp_demux_024_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_024_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_024_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_024_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_024_src2_valid), // .valid
|
|
.src2_data (rsp_demux_024_src2_data), // .data
|
|
.src2_channel (rsp_demux_024_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_024_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_024_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_017 rsp_demux_025 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_029_src_ready), // sink.ready
|
|
.sink_channel (router_029_src_channel), // .channel
|
|
.sink_data (router_029_src_data), // .data
|
|
.sink_startofpacket (router_029_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_029_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_029_src_valid), // .valid
|
|
.src0_ready (rsp_demux_025_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_025_src0_valid), // .valid
|
|
.src0_data (rsp_demux_025_src0_data), // .data
|
|
.src0_channel (rsp_demux_025_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_025_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_025_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_025_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_025_src1_valid), // .valid
|
|
.src1_data (rsp_demux_025_src1_data), // .data
|
|
.src1_channel (rsp_demux_025_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_025_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_025_src1_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_026 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_030_src_ready), // sink.ready
|
|
.sink_channel (router_030_src_channel), // .channel
|
|
.sink_data (router_030_src_data), // .data
|
|
.sink_startofpacket (router_030_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_030_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_030_src_valid), // .valid
|
|
.src0_ready (rsp_demux_026_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_026_src0_valid), // .valid
|
|
.src0_data (rsp_demux_026_src0_data), // .data
|
|
.src0_channel (rsp_demux_026_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_026_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_026_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_026_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_026_src1_valid), // .valid
|
|
.src1_data (rsp_demux_026_src1_data), // .data
|
|
.src1_channel (rsp_demux_026_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_026_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_026_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_026_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_026_src2_valid), // .valid
|
|
.src2_data (rsp_demux_026_src2_data), // .data
|
|
.src2_channel (rsp_demux_026_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_026_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_026_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_027 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_031_src_ready), // sink.ready
|
|
.sink_channel (router_031_src_channel), // .channel
|
|
.sink_data (router_031_src_data), // .data
|
|
.sink_startofpacket (router_031_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_031_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_031_src_valid), // .valid
|
|
.src0_ready (rsp_demux_027_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_027_src0_valid), // .valid
|
|
.src0_data (rsp_demux_027_src0_data), // .data
|
|
.src0_channel (rsp_demux_027_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_027_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_027_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_027_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_027_src1_valid), // .valid
|
|
.src1_data (rsp_demux_027_src1_data), // .data
|
|
.src1_channel (rsp_demux_027_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_027_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_027_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_027_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_027_src2_valid), // .valid
|
|
.src2_data (rsp_demux_027_src2_data), // .data
|
|
.src2_channel (rsp_demux_027_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_027_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_027_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_028 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_032_src_ready), // sink.ready
|
|
.sink_channel (router_032_src_channel), // .channel
|
|
.sink_data (router_032_src_data), // .data
|
|
.sink_startofpacket (router_032_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_032_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_032_src_valid), // .valid
|
|
.src0_ready (rsp_demux_028_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_028_src0_valid), // .valid
|
|
.src0_data (rsp_demux_028_src0_data), // .data
|
|
.src0_channel (rsp_demux_028_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_028_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_028_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_028_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_028_src1_valid), // .valid
|
|
.src1_data (rsp_demux_028_src1_data), // .data
|
|
.src1_channel (rsp_demux_028_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_028_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_028_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_028_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_028_src2_valid), // .valid
|
|
.src2_data (rsp_demux_028_src2_data), // .data
|
|
.src2_channel (rsp_demux_028_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_028_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_028_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_029 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_033_src_ready), // sink.ready
|
|
.sink_channel (router_033_src_channel), // .channel
|
|
.sink_data (router_033_src_data), // .data
|
|
.sink_startofpacket (router_033_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_033_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_033_src_valid), // .valid
|
|
.src0_ready (rsp_demux_029_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_029_src0_valid), // .valid
|
|
.src0_data (rsp_demux_029_src0_data), // .data
|
|
.src0_channel (rsp_demux_029_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_029_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_029_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_029_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_029_src1_valid), // .valid
|
|
.src1_data (rsp_demux_029_src1_data), // .data
|
|
.src1_channel (rsp_demux_029_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_029_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_029_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_029_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_029_src2_valid), // .valid
|
|
.src2_data (rsp_demux_029_src2_data), // .data
|
|
.src2_channel (rsp_demux_029_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_029_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_029_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_030 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_034_src_ready), // sink.ready
|
|
.sink_channel (router_034_src_channel), // .channel
|
|
.sink_data (router_034_src_data), // .data
|
|
.sink_startofpacket (router_034_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_034_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_034_src_valid), // .valid
|
|
.src0_ready (rsp_demux_030_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_030_src0_valid), // .valid
|
|
.src0_data (rsp_demux_030_src0_data), // .data
|
|
.src0_channel (rsp_demux_030_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_030_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_030_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_030_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_030_src1_valid), // .valid
|
|
.src1_data (rsp_demux_030_src1_data), // .data
|
|
.src1_channel (rsp_demux_030_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_030_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_030_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_030_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_030_src2_valid), // .valid
|
|
.src2_data (rsp_demux_030_src2_data), // .data
|
|
.src2_channel (rsp_demux_030_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_030_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_030_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_010 rsp_demux_031 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_035_src_ready), // sink.ready
|
|
.sink_channel (router_035_src_channel), // .channel
|
|
.sink_data (router_035_src_data), // .data
|
|
.sink_startofpacket (router_035_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_035_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_035_src_valid), // .valid
|
|
.src0_ready (rsp_demux_031_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_031_src0_valid), // .valid
|
|
.src0_data (rsp_demux_031_src0_data), // .data
|
|
.src0_channel (rsp_demux_031_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_031_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_031_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux_010 rsp_demux_032 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_036_src_ready), // sink.ready
|
|
.sink_channel (router_036_src_channel), // .channel
|
|
.sink_data (router_036_src_data), // .data
|
|
.sink_startofpacket (router_036_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_036_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_036_src_valid), // .valid
|
|
.src0_ready (rsp_demux_032_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_032_src0_valid), // .valid
|
|
.src0_data (rsp_demux_032_src0_data), // .data
|
|
.src0_channel (rsp_demux_032_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_032_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_032_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_demux rsp_demux_033 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.sink_ready (router_037_src_ready), // sink.ready
|
|
.sink_channel (router_037_src_channel), // .channel
|
|
.sink_data (router_037_src_data), // .data
|
|
.sink_startofpacket (router_037_src_startofpacket), // .startofpacket
|
|
.sink_endofpacket (router_037_src_endofpacket), // .endofpacket
|
|
.sink_valid (router_037_src_valid), // .valid
|
|
.src0_ready (rsp_demux_033_src0_ready), // src0.ready
|
|
.src0_valid (rsp_demux_033_src0_valid), // .valid
|
|
.src0_data (rsp_demux_033_src0_data), // .data
|
|
.src0_channel (rsp_demux_033_src0_channel), // .channel
|
|
.src0_startofpacket (rsp_demux_033_src0_startofpacket), // .startofpacket
|
|
.src0_endofpacket (rsp_demux_033_src0_endofpacket), // .endofpacket
|
|
.src1_ready (rsp_demux_033_src1_ready), // src1.ready
|
|
.src1_valid (rsp_demux_033_src1_valid), // .valid
|
|
.src1_data (rsp_demux_033_src1_data), // .data
|
|
.src1_channel (rsp_demux_033_src1_channel), // .channel
|
|
.src1_startofpacket (rsp_demux_033_src1_startofpacket), // .startofpacket
|
|
.src1_endofpacket (rsp_demux_033_src1_endofpacket), // .endofpacket
|
|
.src2_ready (rsp_demux_033_src2_ready), // src2.ready
|
|
.src2_valid (rsp_demux_033_src2_valid), // .valid
|
|
.src2_data (rsp_demux_033_src2_data), // .data
|
|
.src2_channel (rsp_demux_033_src2_channel), // .channel
|
|
.src2_startofpacket (rsp_demux_033_src2_startofpacket), // .startofpacket
|
|
.src2_endofpacket (rsp_demux_033_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_mux rsp_mux (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_src_ready), // src.ready
|
|
.src_valid (rsp_mux_src_valid), // .valid
|
|
.src_data (rsp_mux_src_data), // .data
|
|
.src_channel (rsp_mux_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src0_valid), // .valid
|
|
.sink0_channel (rsp_demux_src0_channel), // .channel
|
|
.sink0_data (rsp_demux_src0_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
|
|
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
|
|
.sink1_valid (rsp_demux_001_src0_valid), // .valid
|
|
.sink1_channel (rsp_demux_001_src0_channel), // .channel
|
|
.sink1_data (rsp_demux_001_src0_data), // .data
|
|
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
|
|
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
|
|
.sink2_valid (rsp_demux_002_src0_valid), // .valid
|
|
.sink2_channel (rsp_demux_002_src0_channel), // .channel
|
|
.sink2_data (rsp_demux_002_src0_data), // .data
|
|
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
|
|
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
|
|
.sink3_valid (rsp_demux_003_src0_valid), // .valid
|
|
.sink3_channel (rsp_demux_003_src0_channel), // .channel
|
|
.sink3_data (rsp_demux_003_src0_data), // .data
|
|
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
|
|
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
|
|
.sink4_valid (rsp_demux_004_src0_valid), // .valid
|
|
.sink4_channel (rsp_demux_004_src0_channel), // .channel
|
|
.sink4_data (rsp_demux_004_src0_data), // .data
|
|
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
|
|
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
|
|
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
|
|
.sink5_valid (rsp_demux_005_src0_valid), // .valid
|
|
.sink5_channel (rsp_demux_005_src0_channel), // .channel
|
|
.sink5_data (rsp_demux_005_src0_data), // .data
|
|
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
|
|
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
|
|
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
|
|
.sink6_valid (rsp_demux_006_src0_valid), // .valid
|
|
.sink6_channel (rsp_demux_006_src0_channel), // .channel
|
|
.sink6_data (rsp_demux_006_src0_data), // .data
|
|
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
|
|
.sink6_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
|
|
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
|
|
.sink7_valid (rsp_demux_007_src0_valid), // .valid
|
|
.sink7_channel (rsp_demux_007_src0_channel), // .channel
|
|
.sink7_data (rsp_demux_007_src0_data), // .data
|
|
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
|
|
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
|
|
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
|
|
.sink8_valid (rsp_demux_008_src0_valid), // .valid
|
|
.sink8_channel (rsp_demux_008_src0_channel), // .channel
|
|
.sink8_data (rsp_demux_008_src0_data), // .data
|
|
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
|
|
.sink8_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
|
|
.sink9_ready (rsp_demux_009_src0_ready), // sink9.ready
|
|
.sink9_valid (rsp_demux_009_src0_valid), // .valid
|
|
.sink9_channel (rsp_demux_009_src0_channel), // .channel
|
|
.sink9_data (rsp_demux_009_src0_data), // .data
|
|
.sink9_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
|
|
.sink9_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
|
|
.sink10_ready (rsp_demux_010_src0_ready), // sink10.ready
|
|
.sink10_valid (rsp_demux_010_src0_valid), // .valid
|
|
.sink10_channel (rsp_demux_010_src0_channel), // .channel
|
|
.sink10_data (rsp_demux_010_src0_data), // .data
|
|
.sink10_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
|
|
.sink10_endofpacket (rsp_demux_010_src0_endofpacket), // .endofpacket
|
|
.sink11_ready (rsp_demux_011_src0_ready), // sink11.ready
|
|
.sink11_valid (rsp_demux_011_src0_valid), // .valid
|
|
.sink11_channel (rsp_demux_011_src0_channel), // .channel
|
|
.sink11_data (rsp_demux_011_src0_data), // .data
|
|
.sink11_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
|
|
.sink11_endofpacket (rsp_demux_011_src0_endofpacket), // .endofpacket
|
|
.sink12_ready (rsp_demux_012_src0_ready), // sink12.ready
|
|
.sink12_valid (rsp_demux_012_src0_valid), // .valid
|
|
.sink12_channel (rsp_demux_012_src0_channel), // .channel
|
|
.sink12_data (rsp_demux_012_src0_data), // .data
|
|
.sink12_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
|
|
.sink12_endofpacket (rsp_demux_012_src0_endofpacket), // .endofpacket
|
|
.sink13_ready (rsp_demux_013_src0_ready), // sink13.ready
|
|
.sink13_valid (rsp_demux_013_src0_valid), // .valid
|
|
.sink13_channel (rsp_demux_013_src0_channel), // .channel
|
|
.sink13_data (rsp_demux_013_src0_data), // .data
|
|
.sink13_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
|
|
.sink13_endofpacket (rsp_demux_013_src0_endofpacket), // .endofpacket
|
|
.sink14_ready (rsp_demux_014_src0_ready), // sink14.ready
|
|
.sink14_valid (rsp_demux_014_src0_valid), // .valid
|
|
.sink14_channel (rsp_demux_014_src0_channel), // .channel
|
|
.sink14_data (rsp_demux_014_src0_data), // .data
|
|
.sink14_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
|
|
.sink14_endofpacket (rsp_demux_014_src0_endofpacket), // .endofpacket
|
|
.sink15_ready (rsp_demux_015_src0_ready), // sink15.ready
|
|
.sink15_valid (rsp_demux_015_src0_valid), // .valid
|
|
.sink15_channel (rsp_demux_015_src0_channel), // .channel
|
|
.sink15_data (rsp_demux_015_src0_data), // .data
|
|
.sink15_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
|
|
.sink15_endofpacket (rsp_demux_015_src0_endofpacket), // .endofpacket
|
|
.sink16_ready (rsp_demux_016_src0_ready), // sink16.ready
|
|
.sink16_valid (rsp_demux_016_src0_valid), // .valid
|
|
.sink16_channel (rsp_demux_016_src0_channel), // .channel
|
|
.sink16_data (rsp_demux_016_src0_data), // .data
|
|
.sink16_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
|
|
.sink16_endofpacket (rsp_demux_016_src0_endofpacket), // .endofpacket
|
|
.sink17_ready (rsp_demux_017_src0_ready), // sink17.ready
|
|
.sink17_valid (rsp_demux_017_src0_valid), // .valid
|
|
.sink17_channel (rsp_demux_017_src0_channel), // .channel
|
|
.sink17_data (rsp_demux_017_src0_data), // .data
|
|
.sink17_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
|
|
.sink17_endofpacket (rsp_demux_017_src0_endofpacket), // .endofpacket
|
|
.sink18_ready (rsp_demux_018_src0_ready), // sink18.ready
|
|
.sink18_valid (rsp_demux_018_src0_valid), // .valid
|
|
.sink18_channel (rsp_demux_018_src0_channel), // .channel
|
|
.sink18_data (rsp_demux_018_src0_data), // .data
|
|
.sink18_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
|
|
.sink18_endofpacket (rsp_demux_018_src0_endofpacket), // .endofpacket
|
|
.sink19_ready (rsp_demux_019_src0_ready), // sink19.ready
|
|
.sink19_valid (rsp_demux_019_src0_valid), // .valid
|
|
.sink19_channel (rsp_demux_019_src0_channel), // .channel
|
|
.sink19_data (rsp_demux_019_src0_data), // .data
|
|
.sink19_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
|
|
.sink19_endofpacket (rsp_demux_019_src0_endofpacket), // .endofpacket
|
|
.sink20_ready (rsp_demux_020_src0_ready), // sink20.ready
|
|
.sink20_valid (rsp_demux_020_src0_valid), // .valid
|
|
.sink20_channel (rsp_demux_020_src0_channel), // .channel
|
|
.sink20_data (rsp_demux_020_src0_data), // .data
|
|
.sink20_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
|
|
.sink20_endofpacket (rsp_demux_020_src0_endofpacket), // .endofpacket
|
|
.sink21_ready (rsp_demux_021_src0_ready), // sink21.ready
|
|
.sink21_valid (rsp_demux_021_src0_valid), // .valid
|
|
.sink21_channel (rsp_demux_021_src0_channel), // .channel
|
|
.sink21_data (rsp_demux_021_src0_data), // .data
|
|
.sink21_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
|
|
.sink21_endofpacket (rsp_demux_021_src0_endofpacket), // .endofpacket
|
|
.sink22_ready (rsp_demux_022_src0_ready), // sink22.ready
|
|
.sink22_valid (rsp_demux_022_src0_valid), // .valid
|
|
.sink22_channel (rsp_demux_022_src0_channel), // .channel
|
|
.sink22_data (rsp_demux_022_src0_data), // .data
|
|
.sink22_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
|
|
.sink22_endofpacket (rsp_demux_022_src0_endofpacket), // .endofpacket
|
|
.sink23_ready (rsp_demux_023_src0_ready), // sink23.ready
|
|
.sink23_valid (rsp_demux_023_src0_valid), // .valid
|
|
.sink23_channel (rsp_demux_023_src0_channel), // .channel
|
|
.sink23_data (rsp_demux_023_src0_data), // .data
|
|
.sink23_startofpacket (rsp_demux_023_src0_startofpacket), // .startofpacket
|
|
.sink23_endofpacket (rsp_demux_023_src0_endofpacket), // .endofpacket
|
|
.sink24_ready (rsp_demux_024_src0_ready), // sink24.ready
|
|
.sink24_valid (rsp_demux_024_src0_valid), // .valid
|
|
.sink24_channel (rsp_demux_024_src0_channel), // .channel
|
|
.sink24_data (rsp_demux_024_src0_data), // .data
|
|
.sink24_startofpacket (rsp_demux_024_src0_startofpacket), // .startofpacket
|
|
.sink24_endofpacket (rsp_demux_024_src0_endofpacket), // .endofpacket
|
|
.sink25_ready (rsp_demux_025_src0_ready), // sink25.ready
|
|
.sink25_valid (rsp_demux_025_src0_valid), // .valid
|
|
.sink25_channel (rsp_demux_025_src0_channel), // .channel
|
|
.sink25_data (rsp_demux_025_src0_data), // .data
|
|
.sink25_startofpacket (rsp_demux_025_src0_startofpacket), // .startofpacket
|
|
.sink25_endofpacket (rsp_demux_025_src0_endofpacket), // .endofpacket
|
|
.sink26_ready (rsp_demux_026_src0_ready), // sink26.ready
|
|
.sink26_valid (rsp_demux_026_src0_valid), // .valid
|
|
.sink26_channel (rsp_demux_026_src0_channel), // .channel
|
|
.sink26_data (rsp_demux_026_src0_data), // .data
|
|
.sink26_startofpacket (rsp_demux_026_src0_startofpacket), // .startofpacket
|
|
.sink26_endofpacket (rsp_demux_026_src0_endofpacket), // .endofpacket
|
|
.sink27_ready (rsp_demux_027_src0_ready), // sink27.ready
|
|
.sink27_valid (rsp_demux_027_src0_valid), // .valid
|
|
.sink27_channel (rsp_demux_027_src0_channel), // .channel
|
|
.sink27_data (rsp_demux_027_src0_data), // .data
|
|
.sink27_startofpacket (rsp_demux_027_src0_startofpacket), // .startofpacket
|
|
.sink27_endofpacket (rsp_demux_027_src0_endofpacket), // .endofpacket
|
|
.sink28_ready (rsp_demux_028_src0_ready), // sink28.ready
|
|
.sink28_valid (rsp_demux_028_src0_valid), // .valid
|
|
.sink28_channel (rsp_demux_028_src0_channel), // .channel
|
|
.sink28_data (rsp_demux_028_src0_data), // .data
|
|
.sink28_startofpacket (rsp_demux_028_src0_startofpacket), // .startofpacket
|
|
.sink28_endofpacket (rsp_demux_028_src0_endofpacket), // .endofpacket
|
|
.sink29_ready (rsp_demux_029_src0_ready), // sink29.ready
|
|
.sink29_valid (rsp_demux_029_src0_valid), // .valid
|
|
.sink29_channel (rsp_demux_029_src0_channel), // .channel
|
|
.sink29_data (rsp_demux_029_src0_data), // .data
|
|
.sink29_startofpacket (rsp_demux_029_src0_startofpacket), // .startofpacket
|
|
.sink29_endofpacket (rsp_demux_029_src0_endofpacket), // .endofpacket
|
|
.sink30_ready (rsp_demux_030_src0_ready), // sink30.ready
|
|
.sink30_valid (rsp_demux_030_src0_valid), // .valid
|
|
.sink30_channel (rsp_demux_030_src0_channel), // .channel
|
|
.sink30_data (rsp_demux_030_src0_data), // .data
|
|
.sink30_startofpacket (rsp_demux_030_src0_startofpacket), // .startofpacket
|
|
.sink30_endofpacket (rsp_demux_030_src0_endofpacket), // .endofpacket
|
|
.sink31_ready (rsp_demux_031_src0_ready), // sink31.ready
|
|
.sink31_valid (rsp_demux_031_src0_valid), // .valid
|
|
.sink31_channel (rsp_demux_031_src0_channel), // .channel
|
|
.sink31_data (rsp_demux_031_src0_data), // .data
|
|
.sink31_startofpacket (rsp_demux_031_src0_startofpacket), // .startofpacket
|
|
.sink31_endofpacket (rsp_demux_031_src0_endofpacket), // .endofpacket
|
|
.sink32_ready (rsp_demux_032_src0_ready), // sink32.ready
|
|
.sink32_valid (rsp_demux_032_src0_valid), // .valid
|
|
.sink32_channel (rsp_demux_032_src0_channel), // .channel
|
|
.sink32_data (rsp_demux_032_src0_data), // .data
|
|
.sink32_startofpacket (rsp_demux_032_src0_startofpacket), // .startofpacket
|
|
.sink32_endofpacket (rsp_demux_032_src0_endofpacket), // .endofpacket
|
|
.sink33_ready (rsp_demux_033_src0_ready), // sink33.ready
|
|
.sink33_valid (rsp_demux_033_src0_valid), // .valid
|
|
.sink33_channel (rsp_demux_033_src0_channel), // .channel
|
|
.sink33_data (rsp_demux_033_src0_data), // .data
|
|
.sink33_startofpacket (rsp_demux_033_src0_startofpacket), // .startofpacket
|
|
.sink33_endofpacket (rsp_demux_033_src0_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_001_src_ready), // src.ready
|
|
.src_valid (rsp_mux_001_src_valid), // .valid
|
|
.src_data (rsp_mux_001_src_data), // .data
|
|
.src_channel (rsp_mux_001_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src1_valid), // .valid
|
|
.sink0_channel (rsp_demux_src1_channel), // .channel
|
|
.sink0_data (rsp_demux_src1_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
|
|
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
|
|
.sink1_valid (rsp_demux_001_src1_valid), // .valid
|
|
.sink1_channel (rsp_demux_001_src1_channel), // .channel
|
|
.sink1_data (rsp_demux_001_src1_data), // .data
|
|
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
|
|
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
|
|
.sink2_valid (rsp_demux_002_src1_valid), // .valid
|
|
.sink2_channel (rsp_demux_002_src1_channel), // .channel
|
|
.sink2_data (rsp_demux_002_src1_data), // .data
|
|
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
|
|
.sink3_ready (rsp_demux_003_src1_ready), // sink3.ready
|
|
.sink3_valid (rsp_demux_003_src1_valid), // .valid
|
|
.sink3_channel (rsp_demux_003_src1_channel), // .channel
|
|
.sink3_data (rsp_demux_003_src1_data), // .data
|
|
.sink3_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
|
|
.sink4_ready (rsp_demux_004_src1_ready), // sink4.ready
|
|
.sink4_valid (rsp_demux_004_src1_valid), // .valid
|
|
.sink4_channel (rsp_demux_004_src1_channel), // .channel
|
|
.sink4_data (rsp_demux_004_src1_data), // .data
|
|
.sink4_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
|
|
.sink4_endofpacket (rsp_demux_004_src1_endofpacket), // .endofpacket
|
|
.sink5_ready (rsp_demux_005_src1_ready), // sink5.ready
|
|
.sink5_valid (rsp_demux_005_src1_valid), // .valid
|
|
.sink5_channel (rsp_demux_005_src1_channel), // .channel
|
|
.sink5_data (rsp_demux_005_src1_data), // .data
|
|
.sink5_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
|
|
.sink5_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
|
|
.sink6_ready (rsp_demux_006_src1_ready), // sink6.ready
|
|
.sink6_valid (rsp_demux_006_src1_valid), // .valid
|
|
.sink6_channel (rsp_demux_006_src1_channel), // .channel
|
|
.sink6_data (rsp_demux_006_src1_data), // .data
|
|
.sink6_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
|
|
.sink6_endofpacket (rsp_demux_006_src1_endofpacket), // .endofpacket
|
|
.sink7_ready (rsp_demux_007_src1_ready), // sink7.ready
|
|
.sink7_valid (rsp_demux_007_src1_valid), // .valid
|
|
.sink7_channel (rsp_demux_007_src1_channel), // .channel
|
|
.sink7_data (rsp_demux_007_src1_data), // .data
|
|
.sink7_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
|
|
.sink7_endofpacket (rsp_demux_007_src1_endofpacket), // .endofpacket
|
|
.sink8_ready (rsp_demux_008_src1_ready), // sink8.ready
|
|
.sink8_valid (rsp_demux_008_src1_valid), // .valid
|
|
.sink8_channel (rsp_demux_008_src1_channel), // .channel
|
|
.sink8_data (rsp_demux_008_src1_data), // .data
|
|
.sink8_startofpacket (rsp_demux_008_src1_startofpacket), // .startofpacket
|
|
.sink8_endofpacket (rsp_demux_008_src1_endofpacket), // .endofpacket
|
|
.sink9_ready (rsp_demux_009_src1_ready), // sink9.ready
|
|
.sink9_valid (rsp_demux_009_src1_valid), // .valid
|
|
.sink9_channel (rsp_demux_009_src1_channel), // .channel
|
|
.sink9_data (rsp_demux_009_src1_data), // .data
|
|
.sink9_startofpacket (rsp_demux_009_src1_startofpacket), // .startofpacket
|
|
.sink9_endofpacket (rsp_demux_009_src1_endofpacket), // .endofpacket
|
|
.sink10_ready (rsp_demux_011_src1_ready), // sink10.ready
|
|
.sink10_valid (rsp_demux_011_src1_valid), // .valid
|
|
.sink10_channel (rsp_demux_011_src1_channel), // .channel
|
|
.sink10_data (rsp_demux_011_src1_data), // .data
|
|
.sink10_startofpacket (rsp_demux_011_src1_startofpacket), // .startofpacket
|
|
.sink10_endofpacket (rsp_demux_011_src1_endofpacket), // .endofpacket
|
|
.sink11_ready (rsp_demux_012_src1_ready), // sink11.ready
|
|
.sink11_valid (rsp_demux_012_src1_valid), // .valid
|
|
.sink11_channel (rsp_demux_012_src1_channel), // .channel
|
|
.sink11_data (rsp_demux_012_src1_data), // .data
|
|
.sink11_startofpacket (rsp_demux_012_src1_startofpacket), // .startofpacket
|
|
.sink11_endofpacket (rsp_demux_012_src1_endofpacket), // .endofpacket
|
|
.sink12_ready (rsp_demux_013_src1_ready), // sink12.ready
|
|
.sink12_valid (rsp_demux_013_src1_valid), // .valid
|
|
.sink12_channel (rsp_demux_013_src1_channel), // .channel
|
|
.sink12_data (rsp_demux_013_src1_data), // .data
|
|
.sink12_startofpacket (rsp_demux_013_src1_startofpacket), // .startofpacket
|
|
.sink12_endofpacket (rsp_demux_013_src1_endofpacket), // .endofpacket
|
|
.sink13_ready (rsp_demux_014_src1_ready), // sink13.ready
|
|
.sink13_valid (rsp_demux_014_src1_valid), // .valid
|
|
.sink13_channel (rsp_demux_014_src1_channel), // .channel
|
|
.sink13_data (rsp_demux_014_src1_data), // .data
|
|
.sink13_startofpacket (rsp_demux_014_src1_startofpacket), // .startofpacket
|
|
.sink13_endofpacket (rsp_demux_014_src1_endofpacket), // .endofpacket
|
|
.sink14_ready (rsp_demux_015_src1_ready), // sink14.ready
|
|
.sink14_valid (rsp_demux_015_src1_valid), // .valid
|
|
.sink14_channel (rsp_demux_015_src1_channel), // .channel
|
|
.sink14_data (rsp_demux_015_src1_data), // .data
|
|
.sink14_startofpacket (rsp_demux_015_src1_startofpacket), // .startofpacket
|
|
.sink14_endofpacket (rsp_demux_015_src1_endofpacket), // .endofpacket
|
|
.sink15_ready (rsp_demux_016_src1_ready), // sink15.ready
|
|
.sink15_valid (rsp_demux_016_src1_valid), // .valid
|
|
.sink15_channel (rsp_demux_016_src1_channel), // .channel
|
|
.sink15_data (rsp_demux_016_src1_data), // .data
|
|
.sink15_startofpacket (rsp_demux_016_src1_startofpacket), // .startofpacket
|
|
.sink15_endofpacket (rsp_demux_016_src1_endofpacket), // .endofpacket
|
|
.sink16_ready (rsp_demux_017_src1_ready), // sink16.ready
|
|
.sink16_valid (rsp_demux_017_src1_valid), // .valid
|
|
.sink16_channel (rsp_demux_017_src1_channel), // .channel
|
|
.sink16_data (rsp_demux_017_src1_data), // .data
|
|
.sink16_startofpacket (rsp_demux_017_src1_startofpacket), // .startofpacket
|
|
.sink16_endofpacket (rsp_demux_017_src1_endofpacket), // .endofpacket
|
|
.sink17_ready (rsp_demux_018_src1_ready), // sink17.ready
|
|
.sink17_valid (rsp_demux_018_src1_valid), // .valid
|
|
.sink17_channel (rsp_demux_018_src1_channel), // .channel
|
|
.sink17_data (rsp_demux_018_src1_data), // .data
|
|
.sink17_startofpacket (rsp_demux_018_src1_startofpacket), // .startofpacket
|
|
.sink17_endofpacket (rsp_demux_018_src1_endofpacket), // .endofpacket
|
|
.sink18_ready (rsp_demux_019_src1_ready), // sink18.ready
|
|
.sink18_valid (rsp_demux_019_src1_valid), // .valid
|
|
.sink18_channel (rsp_demux_019_src1_channel), // .channel
|
|
.sink18_data (rsp_demux_019_src1_data), // .data
|
|
.sink18_startofpacket (rsp_demux_019_src1_startofpacket), // .startofpacket
|
|
.sink18_endofpacket (rsp_demux_019_src1_endofpacket), // .endofpacket
|
|
.sink19_ready (rsp_demux_020_src1_ready), // sink19.ready
|
|
.sink19_valid (rsp_demux_020_src1_valid), // .valid
|
|
.sink19_channel (rsp_demux_020_src1_channel), // .channel
|
|
.sink19_data (rsp_demux_020_src1_data), // .data
|
|
.sink19_startofpacket (rsp_demux_020_src1_startofpacket), // .startofpacket
|
|
.sink19_endofpacket (rsp_demux_020_src1_endofpacket), // .endofpacket
|
|
.sink20_ready (rsp_demux_021_src1_ready), // sink20.ready
|
|
.sink20_valid (rsp_demux_021_src1_valid), // .valid
|
|
.sink20_channel (rsp_demux_021_src1_channel), // .channel
|
|
.sink20_data (rsp_demux_021_src1_data), // .data
|
|
.sink20_startofpacket (rsp_demux_021_src1_startofpacket), // .startofpacket
|
|
.sink20_endofpacket (rsp_demux_021_src1_endofpacket), // .endofpacket
|
|
.sink21_ready (rsp_demux_022_src1_ready), // sink21.ready
|
|
.sink21_valid (rsp_demux_022_src1_valid), // .valid
|
|
.sink21_channel (rsp_demux_022_src1_channel), // .channel
|
|
.sink21_data (rsp_demux_022_src1_data), // .data
|
|
.sink21_startofpacket (rsp_demux_022_src1_startofpacket), // .startofpacket
|
|
.sink21_endofpacket (rsp_demux_022_src1_endofpacket), // .endofpacket
|
|
.sink22_ready (rsp_demux_023_src1_ready), // sink22.ready
|
|
.sink22_valid (rsp_demux_023_src1_valid), // .valid
|
|
.sink22_channel (rsp_demux_023_src1_channel), // .channel
|
|
.sink22_data (rsp_demux_023_src1_data), // .data
|
|
.sink22_startofpacket (rsp_demux_023_src1_startofpacket), // .startofpacket
|
|
.sink22_endofpacket (rsp_demux_023_src1_endofpacket), // .endofpacket
|
|
.sink23_ready (rsp_demux_024_src1_ready), // sink23.ready
|
|
.sink23_valid (rsp_demux_024_src1_valid), // .valid
|
|
.sink23_channel (rsp_demux_024_src1_channel), // .channel
|
|
.sink23_data (rsp_demux_024_src1_data), // .data
|
|
.sink23_startofpacket (rsp_demux_024_src1_startofpacket), // .startofpacket
|
|
.sink23_endofpacket (rsp_demux_024_src1_endofpacket), // .endofpacket
|
|
.sink24_ready (rsp_demux_025_src1_ready), // sink24.ready
|
|
.sink24_valid (rsp_demux_025_src1_valid), // .valid
|
|
.sink24_channel (rsp_demux_025_src1_channel), // .channel
|
|
.sink24_data (rsp_demux_025_src1_data), // .data
|
|
.sink24_startofpacket (rsp_demux_025_src1_startofpacket), // .startofpacket
|
|
.sink24_endofpacket (rsp_demux_025_src1_endofpacket), // .endofpacket
|
|
.sink25_ready (rsp_demux_026_src1_ready), // sink25.ready
|
|
.sink25_valid (rsp_demux_026_src1_valid), // .valid
|
|
.sink25_channel (rsp_demux_026_src1_channel), // .channel
|
|
.sink25_data (rsp_demux_026_src1_data), // .data
|
|
.sink25_startofpacket (rsp_demux_026_src1_startofpacket), // .startofpacket
|
|
.sink25_endofpacket (rsp_demux_026_src1_endofpacket), // .endofpacket
|
|
.sink26_ready (rsp_demux_027_src1_ready), // sink26.ready
|
|
.sink26_valid (rsp_demux_027_src1_valid), // .valid
|
|
.sink26_channel (rsp_demux_027_src1_channel), // .channel
|
|
.sink26_data (rsp_demux_027_src1_data), // .data
|
|
.sink26_startofpacket (rsp_demux_027_src1_startofpacket), // .startofpacket
|
|
.sink26_endofpacket (rsp_demux_027_src1_endofpacket), // .endofpacket
|
|
.sink27_ready (rsp_demux_028_src1_ready), // sink27.ready
|
|
.sink27_valid (rsp_demux_028_src1_valid), // .valid
|
|
.sink27_channel (rsp_demux_028_src1_channel), // .channel
|
|
.sink27_data (rsp_demux_028_src1_data), // .data
|
|
.sink27_startofpacket (rsp_demux_028_src1_startofpacket), // .startofpacket
|
|
.sink27_endofpacket (rsp_demux_028_src1_endofpacket), // .endofpacket
|
|
.sink28_ready (rsp_demux_029_src1_ready), // sink28.ready
|
|
.sink28_valid (rsp_demux_029_src1_valid), // .valid
|
|
.sink28_channel (rsp_demux_029_src1_channel), // .channel
|
|
.sink28_data (rsp_demux_029_src1_data), // .data
|
|
.sink28_startofpacket (rsp_demux_029_src1_startofpacket), // .startofpacket
|
|
.sink28_endofpacket (rsp_demux_029_src1_endofpacket), // .endofpacket
|
|
.sink29_ready (rsp_demux_030_src1_ready), // sink29.ready
|
|
.sink29_valid (rsp_demux_030_src1_valid), // .valid
|
|
.sink29_channel (rsp_demux_030_src1_channel), // .channel
|
|
.sink29_data (rsp_demux_030_src1_data), // .data
|
|
.sink29_startofpacket (rsp_demux_030_src1_startofpacket), // .startofpacket
|
|
.sink29_endofpacket (rsp_demux_030_src1_endofpacket), // .endofpacket
|
|
.sink30_ready (rsp_demux_033_src1_ready), // sink30.ready
|
|
.sink30_valid (rsp_demux_033_src1_valid), // .valid
|
|
.sink30_channel (rsp_demux_033_src1_channel), // .channel
|
|
.sink30_data (rsp_demux_033_src1_data), // .data
|
|
.sink30_startofpacket (rsp_demux_033_src1_startofpacket), // .startofpacket
|
|
.sink30_endofpacket (rsp_demux_033_src1_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_002_src_ready), // src.ready
|
|
.src_valid (rsp_mux_002_src_valid), // .valid
|
|
.src_data (rsp_mux_002_src_data), // .data
|
|
.src_channel (rsp_mux_002_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_src2_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_src2_valid), // .valid
|
|
.sink0_channel (rsp_demux_src2_channel), // .channel
|
|
.sink0_data (rsp_demux_src2_data), // .data
|
|
.sink0_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
|
|
.sink1_ready (rsp_demux_001_src2_ready), // sink1.ready
|
|
.sink1_valid (rsp_demux_001_src2_valid), // .valid
|
|
.sink1_channel (rsp_demux_001_src2_channel), // .channel
|
|
.sink1_data (rsp_demux_001_src2_data), // .data
|
|
.sink1_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (rsp_demux_001_src2_endofpacket), // .endofpacket
|
|
.sink2_ready (rsp_demux_002_src2_ready), // sink2.ready
|
|
.sink2_valid (rsp_demux_002_src2_valid), // .valid
|
|
.sink2_channel (rsp_demux_002_src2_channel), // .channel
|
|
.sink2_data (rsp_demux_002_src2_data), // .data
|
|
.sink2_startofpacket (rsp_demux_002_src2_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (rsp_demux_002_src2_endofpacket), // .endofpacket
|
|
.sink3_ready (rsp_demux_003_src2_ready), // sink3.ready
|
|
.sink3_valid (rsp_demux_003_src2_valid), // .valid
|
|
.sink3_channel (rsp_demux_003_src2_channel), // .channel
|
|
.sink3_data (rsp_demux_003_src2_data), // .data
|
|
.sink3_startofpacket (rsp_demux_003_src2_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (rsp_demux_003_src2_endofpacket), // .endofpacket
|
|
.sink4_ready (rsp_demux_004_src2_ready), // sink4.ready
|
|
.sink4_valid (rsp_demux_004_src2_valid), // .valid
|
|
.sink4_channel (rsp_demux_004_src2_channel), // .channel
|
|
.sink4_data (rsp_demux_004_src2_data), // .data
|
|
.sink4_startofpacket (rsp_demux_004_src2_startofpacket), // .startofpacket
|
|
.sink4_endofpacket (rsp_demux_004_src2_endofpacket), // .endofpacket
|
|
.sink5_ready (rsp_demux_006_src2_ready), // sink5.ready
|
|
.sink5_valid (rsp_demux_006_src2_valid), // .valid
|
|
.sink5_channel (rsp_demux_006_src2_channel), // .channel
|
|
.sink5_data (rsp_demux_006_src2_data), // .data
|
|
.sink5_startofpacket (rsp_demux_006_src2_startofpacket), // .startofpacket
|
|
.sink5_endofpacket (rsp_demux_006_src2_endofpacket), // .endofpacket
|
|
.sink6_ready (rsp_demux_007_src2_ready), // sink6.ready
|
|
.sink6_valid (rsp_demux_007_src2_valid), // .valid
|
|
.sink6_channel (rsp_demux_007_src2_channel), // .channel
|
|
.sink6_data (rsp_demux_007_src2_data), // .data
|
|
.sink6_startofpacket (rsp_demux_007_src2_startofpacket), // .startofpacket
|
|
.sink6_endofpacket (rsp_demux_007_src2_endofpacket), // .endofpacket
|
|
.sink7_ready (rsp_demux_008_src2_ready), // sink7.ready
|
|
.sink7_valid (rsp_demux_008_src2_valid), // .valid
|
|
.sink7_channel (rsp_demux_008_src2_channel), // .channel
|
|
.sink7_data (rsp_demux_008_src2_data), // .data
|
|
.sink7_startofpacket (rsp_demux_008_src2_startofpacket), // .startofpacket
|
|
.sink7_endofpacket (rsp_demux_008_src2_endofpacket), // .endofpacket
|
|
.sink8_ready (rsp_demux_009_src2_ready), // sink8.ready
|
|
.sink8_valid (rsp_demux_009_src2_valid), // .valid
|
|
.sink8_channel (rsp_demux_009_src2_channel), // .channel
|
|
.sink8_data (rsp_demux_009_src2_data), // .data
|
|
.sink8_startofpacket (rsp_demux_009_src2_startofpacket), // .startofpacket
|
|
.sink8_endofpacket (rsp_demux_009_src2_endofpacket), // .endofpacket
|
|
.sink9_ready (rsp_demux_011_src2_ready), // sink9.ready
|
|
.sink9_valid (rsp_demux_011_src2_valid), // .valid
|
|
.sink9_channel (rsp_demux_011_src2_channel), // .channel
|
|
.sink9_data (rsp_demux_011_src2_data), // .data
|
|
.sink9_startofpacket (rsp_demux_011_src2_startofpacket), // .startofpacket
|
|
.sink9_endofpacket (rsp_demux_011_src2_endofpacket), // .endofpacket
|
|
.sink10_ready (rsp_demux_012_src2_ready), // sink10.ready
|
|
.sink10_valid (rsp_demux_012_src2_valid), // .valid
|
|
.sink10_channel (rsp_demux_012_src2_channel), // .channel
|
|
.sink10_data (rsp_demux_012_src2_data), // .data
|
|
.sink10_startofpacket (rsp_demux_012_src2_startofpacket), // .startofpacket
|
|
.sink10_endofpacket (rsp_demux_012_src2_endofpacket), // .endofpacket
|
|
.sink11_ready (rsp_demux_013_src2_ready), // sink11.ready
|
|
.sink11_valid (rsp_demux_013_src2_valid), // .valid
|
|
.sink11_channel (rsp_demux_013_src2_channel), // .channel
|
|
.sink11_data (rsp_demux_013_src2_data), // .data
|
|
.sink11_startofpacket (rsp_demux_013_src2_startofpacket), // .startofpacket
|
|
.sink11_endofpacket (rsp_demux_013_src2_endofpacket), // .endofpacket
|
|
.sink12_ready (rsp_demux_014_src2_ready), // sink12.ready
|
|
.sink12_valid (rsp_demux_014_src2_valid), // .valid
|
|
.sink12_channel (rsp_demux_014_src2_channel), // .channel
|
|
.sink12_data (rsp_demux_014_src2_data), // .data
|
|
.sink12_startofpacket (rsp_demux_014_src2_startofpacket), // .startofpacket
|
|
.sink12_endofpacket (rsp_demux_014_src2_endofpacket), // .endofpacket
|
|
.sink13_ready (rsp_demux_015_src2_ready), // sink13.ready
|
|
.sink13_valid (rsp_demux_015_src2_valid), // .valid
|
|
.sink13_channel (rsp_demux_015_src2_channel), // .channel
|
|
.sink13_data (rsp_demux_015_src2_data), // .data
|
|
.sink13_startofpacket (rsp_demux_015_src2_startofpacket), // .startofpacket
|
|
.sink13_endofpacket (rsp_demux_015_src2_endofpacket), // .endofpacket
|
|
.sink14_ready (rsp_demux_016_src2_ready), // sink14.ready
|
|
.sink14_valid (rsp_demux_016_src2_valid), // .valid
|
|
.sink14_channel (rsp_demux_016_src2_channel), // .channel
|
|
.sink14_data (rsp_demux_016_src2_data), // .data
|
|
.sink14_startofpacket (rsp_demux_016_src2_startofpacket), // .startofpacket
|
|
.sink14_endofpacket (rsp_demux_016_src2_endofpacket), // .endofpacket
|
|
.sink15_ready (rsp_demux_019_src2_ready), // sink15.ready
|
|
.sink15_valid (rsp_demux_019_src2_valid), // .valid
|
|
.sink15_channel (rsp_demux_019_src2_channel), // .channel
|
|
.sink15_data (rsp_demux_019_src2_data), // .data
|
|
.sink15_startofpacket (rsp_demux_019_src2_startofpacket), // .startofpacket
|
|
.sink15_endofpacket (rsp_demux_019_src2_endofpacket), // .endofpacket
|
|
.sink16_ready (rsp_demux_020_src2_ready), // sink16.ready
|
|
.sink16_valid (rsp_demux_020_src2_valid), // .valid
|
|
.sink16_channel (rsp_demux_020_src2_channel), // .channel
|
|
.sink16_data (rsp_demux_020_src2_data), // .data
|
|
.sink16_startofpacket (rsp_demux_020_src2_startofpacket), // .startofpacket
|
|
.sink16_endofpacket (rsp_demux_020_src2_endofpacket), // .endofpacket
|
|
.sink17_ready (rsp_demux_021_src2_ready), // sink17.ready
|
|
.sink17_valid (rsp_demux_021_src2_valid), // .valid
|
|
.sink17_channel (rsp_demux_021_src2_channel), // .channel
|
|
.sink17_data (rsp_demux_021_src2_data), // .data
|
|
.sink17_startofpacket (rsp_demux_021_src2_startofpacket), // .startofpacket
|
|
.sink17_endofpacket (rsp_demux_021_src2_endofpacket), // .endofpacket
|
|
.sink18_ready (rsp_demux_022_src2_ready), // sink18.ready
|
|
.sink18_valid (rsp_demux_022_src2_valid), // .valid
|
|
.sink18_channel (rsp_demux_022_src2_channel), // .channel
|
|
.sink18_data (rsp_demux_022_src2_data), // .data
|
|
.sink18_startofpacket (rsp_demux_022_src2_startofpacket), // .startofpacket
|
|
.sink18_endofpacket (rsp_demux_022_src2_endofpacket), // .endofpacket
|
|
.sink19_ready (rsp_demux_023_src2_ready), // sink19.ready
|
|
.sink19_valid (rsp_demux_023_src2_valid), // .valid
|
|
.sink19_channel (rsp_demux_023_src2_channel), // .channel
|
|
.sink19_data (rsp_demux_023_src2_data), // .data
|
|
.sink19_startofpacket (rsp_demux_023_src2_startofpacket), // .startofpacket
|
|
.sink19_endofpacket (rsp_demux_023_src2_endofpacket), // .endofpacket
|
|
.sink20_ready (rsp_demux_024_src2_ready), // sink20.ready
|
|
.sink20_valid (rsp_demux_024_src2_valid), // .valid
|
|
.sink20_channel (rsp_demux_024_src2_channel), // .channel
|
|
.sink20_data (rsp_demux_024_src2_data), // .data
|
|
.sink20_startofpacket (rsp_demux_024_src2_startofpacket), // .startofpacket
|
|
.sink20_endofpacket (rsp_demux_024_src2_endofpacket), // .endofpacket
|
|
.sink21_ready (rsp_demux_026_src2_ready), // sink21.ready
|
|
.sink21_valid (rsp_demux_026_src2_valid), // .valid
|
|
.sink21_channel (rsp_demux_026_src2_channel), // .channel
|
|
.sink21_data (rsp_demux_026_src2_data), // .data
|
|
.sink21_startofpacket (rsp_demux_026_src2_startofpacket), // .startofpacket
|
|
.sink21_endofpacket (rsp_demux_026_src2_endofpacket), // .endofpacket
|
|
.sink22_ready (rsp_demux_027_src2_ready), // sink22.ready
|
|
.sink22_valid (rsp_demux_027_src2_valid), // .valid
|
|
.sink22_channel (rsp_demux_027_src2_channel), // .channel
|
|
.sink22_data (rsp_demux_027_src2_data), // .data
|
|
.sink22_startofpacket (rsp_demux_027_src2_startofpacket), // .startofpacket
|
|
.sink22_endofpacket (rsp_demux_027_src2_endofpacket), // .endofpacket
|
|
.sink23_ready (rsp_demux_028_src2_ready), // sink23.ready
|
|
.sink23_valid (rsp_demux_028_src2_valid), // .valid
|
|
.sink23_channel (rsp_demux_028_src2_channel), // .channel
|
|
.sink23_data (rsp_demux_028_src2_data), // .data
|
|
.sink23_startofpacket (rsp_demux_028_src2_startofpacket), // .startofpacket
|
|
.sink23_endofpacket (rsp_demux_028_src2_endofpacket), // .endofpacket
|
|
.sink24_ready (rsp_demux_029_src2_ready), // sink24.ready
|
|
.sink24_valid (rsp_demux_029_src2_valid), // .valid
|
|
.sink24_channel (rsp_demux_029_src2_channel), // .channel
|
|
.sink24_data (rsp_demux_029_src2_data), // .data
|
|
.sink24_startofpacket (rsp_demux_029_src2_startofpacket), // .startofpacket
|
|
.sink24_endofpacket (rsp_demux_029_src2_endofpacket), // .endofpacket
|
|
.sink25_ready (rsp_demux_030_src2_ready), // sink25.ready
|
|
.sink25_valid (rsp_demux_030_src2_valid), // .valid
|
|
.sink25_channel (rsp_demux_030_src2_channel), // .channel
|
|
.sink25_data (rsp_demux_030_src2_data), // .data
|
|
.sink25_startofpacket (rsp_demux_030_src2_startofpacket), // .startofpacket
|
|
.sink25_endofpacket (rsp_demux_030_src2_endofpacket), // .endofpacket
|
|
.sink26_ready (rsp_demux_033_src2_ready), // sink26.ready
|
|
.sink26_valid (rsp_demux_033_src2_valid), // .valid
|
|
.sink26_channel (rsp_demux_033_src2_channel), // .channel
|
|
.sink26_data (rsp_demux_033_src2_data), // .data
|
|
.sink26_startofpacket (rsp_demux_033_src2_startofpacket), // .startofpacket
|
|
.sink26_endofpacket (rsp_demux_033_src2_endofpacket) // .endofpacket
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_rsp_mux_003 rsp_mux_003 (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.src_ready (rsp_mux_003_src_ready), // src.ready
|
|
.src_valid (rsp_mux_003_src_valid), // .valid
|
|
.src_data (rsp_mux_003_src_data), // .data
|
|
.src_channel (rsp_mux_003_src_channel), // .channel
|
|
.src_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
|
|
.src_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
|
|
.sink0_ready (rsp_demux_005_src2_ready), // sink0.ready
|
|
.sink0_valid (rsp_demux_005_src2_valid), // .valid
|
|
.sink0_channel (rsp_demux_005_src2_channel), // .channel
|
|
.sink0_data (rsp_demux_005_src2_data), // .data
|
|
.sink0_startofpacket (rsp_demux_005_src2_startofpacket), // .startofpacket
|
|
.sink0_endofpacket (rsp_demux_005_src2_endofpacket), // .endofpacket
|
|
.sink1_ready (rsp_demux_011_src3_ready), // sink1.ready
|
|
.sink1_valid (rsp_demux_011_src3_valid), // .valid
|
|
.sink1_channel (rsp_demux_011_src3_channel), // .channel
|
|
.sink1_data (rsp_demux_011_src3_data), // .data
|
|
.sink1_startofpacket (rsp_demux_011_src3_startofpacket), // .startofpacket
|
|
.sink1_endofpacket (rsp_demux_011_src3_endofpacket), // .endofpacket
|
|
.sink2_ready (rsp_demux_012_src3_ready), // sink2.ready
|
|
.sink2_valid (rsp_demux_012_src3_valid), // .valid
|
|
.sink2_channel (rsp_demux_012_src3_channel), // .channel
|
|
.sink2_data (rsp_demux_012_src3_data), // .data
|
|
.sink2_startofpacket (rsp_demux_012_src3_startofpacket), // .startofpacket
|
|
.sink2_endofpacket (rsp_demux_012_src3_endofpacket), // .endofpacket
|
|
.sink3_ready (rsp_demux_013_src3_ready), // sink3.ready
|
|
.sink3_valid (rsp_demux_013_src3_valid), // .valid
|
|
.sink3_channel (rsp_demux_013_src3_channel), // .channel
|
|
.sink3_data (rsp_demux_013_src3_data), // .data
|
|
.sink3_startofpacket (rsp_demux_013_src3_startofpacket), // .startofpacket
|
|
.sink3_endofpacket (rsp_demux_013_src3_endofpacket), // .endofpacket
|
|
.sink4_ready (rsp_demux_014_src3_ready), // sink4.ready
|
|
.sink4_valid (rsp_demux_014_src3_valid), // .valid
|
|
.sink4_channel (rsp_demux_014_src3_channel), // .channel
|
|
.sink4_data (rsp_demux_014_src3_data), // .data
|
|
.sink4_startofpacket (rsp_demux_014_src3_startofpacket), // .startofpacket
|
|
.sink4_endofpacket (rsp_demux_014_src3_endofpacket) // .endofpacket
|
|
);
|
|
|
|
altera_merlin_width_adapter #(
|
|
.IN_PKT_ADDR_H (49),
|
|
.IN_PKT_ADDR_L (18),
|
|
.IN_PKT_DATA_H (15),
|
|
.IN_PKT_DATA_L (0),
|
|
.IN_PKT_BYTEEN_H (17),
|
|
.IN_PKT_BYTEEN_L (16),
|
|
.IN_PKT_BYTE_CNT_H (58),
|
|
.IN_PKT_BYTE_CNT_L (56),
|
|
.IN_PKT_TRANS_COMPRESSED_READ (50),
|
|
.IN_PKT_TRANS_WRITE (52),
|
|
.IN_PKT_BURSTWRAP_H (61),
|
|
.IN_PKT_BURSTWRAP_L (59),
|
|
.IN_PKT_BURST_SIZE_H (64),
|
|
.IN_PKT_BURST_SIZE_L (62),
|
|
.IN_PKT_RESPONSE_STATUS_H (92),
|
|
.IN_PKT_RESPONSE_STATUS_L (91),
|
|
.IN_PKT_TRANS_EXCLUSIVE (55),
|
|
.IN_PKT_BURST_TYPE_H (66),
|
|
.IN_PKT_BURST_TYPE_L (65),
|
|
.IN_PKT_ORI_BURST_SIZE_L (93),
|
|
.IN_PKT_ORI_BURST_SIZE_H (95),
|
|
.IN_ST_DATA_W (96),
|
|
.OUT_PKT_ADDR_H (67),
|
|
.OUT_PKT_ADDR_L (36),
|
|
.OUT_PKT_DATA_H (31),
|
|
.OUT_PKT_DATA_L (0),
|
|
.OUT_PKT_BYTEEN_H (35),
|
|
.OUT_PKT_BYTEEN_L (32),
|
|
.OUT_PKT_BYTE_CNT_H (76),
|
|
.OUT_PKT_BYTE_CNT_L (74),
|
|
.OUT_PKT_TRANS_COMPRESSED_READ (68),
|
|
.OUT_PKT_BURST_SIZE_H (82),
|
|
.OUT_PKT_BURST_SIZE_L (80),
|
|
.OUT_PKT_RESPONSE_STATUS_H (110),
|
|
.OUT_PKT_RESPONSE_STATUS_L (109),
|
|
.OUT_PKT_TRANS_EXCLUSIVE (73),
|
|
.OUT_PKT_BURST_TYPE_H (84),
|
|
.OUT_PKT_BURST_TYPE_L (83),
|
|
.OUT_PKT_ORI_BURST_SIZE_L (111),
|
|
.OUT_PKT_ORI_BURST_SIZE_H (113),
|
|
.OUT_ST_DATA_W (114),
|
|
.ST_CHANNEL_W (34),
|
|
.OPTIMIZE_FOR_RSP (1),
|
|
.RESPONSE_PATH (1),
|
|
.CONSTANT_BURST_SIZE (1),
|
|
.PACKING (1),
|
|
.ENABLE_ADDRESS_ALIGNMENT (0)
|
|
) sram_multiplexer_avl_rsp_width_adapter (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_valid (router_007_src_valid), // sink.valid
|
|
.in_channel (router_007_src_channel), // .channel
|
|
.in_startofpacket (router_007_src_startofpacket), // .startofpacket
|
|
.in_endofpacket (router_007_src_endofpacket), // .endofpacket
|
|
.in_ready (router_007_src_ready), // .ready
|
|
.in_data (router_007_src_data), // .data
|
|
.out_endofpacket (sram_multiplexer_avl_rsp_width_adapter_src_endofpacket), // src.endofpacket
|
|
.out_data (sram_multiplexer_avl_rsp_width_adapter_src_data), // .data
|
|
.out_channel (sram_multiplexer_avl_rsp_width_adapter_src_channel), // .channel
|
|
.out_valid (sram_multiplexer_avl_rsp_width_adapter_src_valid), // .valid
|
|
.out_ready (sram_multiplexer_avl_rsp_width_adapter_src_ready), // .ready
|
|
.out_startofpacket (sram_multiplexer_avl_rsp_width_adapter_src_startofpacket), // .startofpacket
|
|
.in_command_size_data (3'b000) // (terminated)
|
|
);
|
|
|
|
altera_merlin_width_adapter #(
|
|
.IN_PKT_ADDR_H (67),
|
|
.IN_PKT_ADDR_L (36),
|
|
.IN_PKT_DATA_H (31),
|
|
.IN_PKT_DATA_L (0),
|
|
.IN_PKT_BYTEEN_H (35),
|
|
.IN_PKT_BYTEEN_L (32),
|
|
.IN_PKT_BYTE_CNT_H (76),
|
|
.IN_PKT_BYTE_CNT_L (74),
|
|
.IN_PKT_TRANS_COMPRESSED_READ (68),
|
|
.IN_PKT_TRANS_WRITE (70),
|
|
.IN_PKT_BURSTWRAP_H (79),
|
|
.IN_PKT_BURSTWRAP_L (77),
|
|
.IN_PKT_BURST_SIZE_H (82),
|
|
.IN_PKT_BURST_SIZE_L (80),
|
|
.IN_PKT_RESPONSE_STATUS_H (110),
|
|
.IN_PKT_RESPONSE_STATUS_L (109),
|
|
.IN_PKT_TRANS_EXCLUSIVE (73),
|
|
.IN_PKT_BURST_TYPE_H (84),
|
|
.IN_PKT_BURST_TYPE_L (83),
|
|
.IN_PKT_ORI_BURST_SIZE_L (111),
|
|
.IN_PKT_ORI_BURST_SIZE_H (113),
|
|
.IN_ST_DATA_W (114),
|
|
.OUT_PKT_ADDR_H (49),
|
|
.OUT_PKT_ADDR_L (18),
|
|
.OUT_PKT_DATA_H (15),
|
|
.OUT_PKT_DATA_L (0),
|
|
.OUT_PKT_BYTEEN_H (17),
|
|
.OUT_PKT_BYTEEN_L (16),
|
|
.OUT_PKT_BYTE_CNT_H (58),
|
|
.OUT_PKT_BYTE_CNT_L (56),
|
|
.OUT_PKT_TRANS_COMPRESSED_READ (50),
|
|
.OUT_PKT_BURST_SIZE_H (64),
|
|
.OUT_PKT_BURST_SIZE_L (62),
|
|
.OUT_PKT_RESPONSE_STATUS_H (92),
|
|
.OUT_PKT_RESPONSE_STATUS_L (91),
|
|
.OUT_PKT_TRANS_EXCLUSIVE (55),
|
|
.OUT_PKT_BURST_TYPE_H (66),
|
|
.OUT_PKT_BURST_TYPE_L (65),
|
|
.OUT_PKT_ORI_BURST_SIZE_L (93),
|
|
.OUT_PKT_ORI_BURST_SIZE_H (95),
|
|
.OUT_ST_DATA_W (96),
|
|
.ST_CHANNEL_W (34),
|
|
.OPTIMIZE_FOR_RSP (0),
|
|
.RESPONSE_PATH (0),
|
|
.CONSTANT_BURST_SIZE (1),
|
|
.PACKING (1),
|
|
.ENABLE_ADDRESS_ALIGNMENT (0)
|
|
) sram_multiplexer_avl_cmd_width_adapter (
|
|
.clk (clk_0_clk_clk), // clk.clk
|
|
.reset (nios2_dma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
|
|
.in_valid (cmd_mux_003_src_valid), // sink.valid
|
|
.in_channel (cmd_mux_003_src_channel), // .channel
|
|
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
|
|
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
|
|
.in_ready (cmd_mux_003_src_ready), // .ready
|
|
.in_data (cmd_mux_003_src_data), // .data
|
|
.out_endofpacket (sram_multiplexer_avl_cmd_width_adapter_src_endofpacket), // src.endofpacket
|
|
.out_data (sram_multiplexer_avl_cmd_width_adapter_src_data), // .data
|
|
.out_channel (sram_multiplexer_avl_cmd_width_adapter_src_channel), // .channel
|
|
.out_valid (sram_multiplexer_avl_cmd_width_adapter_src_valid), // .valid
|
|
.out_ready (sram_multiplexer_avl_cmd_width_adapter_src_ready), // .ready
|
|
.out_startofpacket (sram_multiplexer_avl_cmd_width_adapter_src_startofpacket), // .startofpacket
|
|
.in_command_size_data (3'b000) // (terminated)
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (nios2_jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_001 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (eth1_mdio_avalon_slave_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (eth1_mdio_avalon_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (eth1_mdio_avalon_slave_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_002 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (eth0_mdio_avalon_slave_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (eth0_mdio_avalon_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (eth0_mdio_avalon_slave_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter_003 #(
|
|
.inBitsPerSymbol (18),
|
|
.inUsePackets (0),
|
|
.inDataWidth (18),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (18),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_003 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (sram_multiplexer_avl_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (sram_multiplexer_avl_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (sram_multiplexer_avl_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_004 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_params_avl_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_params_avl_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_params_avl_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_005 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (nios2_sysid_control_slave_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (nios2_sysid_control_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (nios2_sysid_control_slave_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_006 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (eth0_rx_dma_csr_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (eth0_rx_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (eth0_rx_dma_csr_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_007 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (eth0_tx_dma_csr_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (eth0_tx_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (eth0_tx_dma_csr_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_007_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_008 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (eth1_rx_dma_csr_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (eth1_rx_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (eth1_rx_dma_csr_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_008_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_008_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_008_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_008_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_009 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (eth1_tx_dma_csr_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (eth1_tx_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (eth1_tx_dma_csr_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_009_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_009_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_009_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_009_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_010 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (nios2_dma_csr_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (nios2_dma_csr_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (nios2_dma_csr_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_010_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_010_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_010_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_010_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_011 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (nios2_cpu_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_011_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_011_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_011_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_011_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_012 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (nios2_pll_pll_slave_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (nios2_pll_pll_slave_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (nios2_pll_pll_slave_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_012_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_012_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_012_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_012_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_013 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (nios2_onchip_mem_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (nios2_onchip_mem_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (nios2_onchip_mem_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_013_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_013_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_013_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_013_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_014 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (sdram_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_014_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_014_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_014_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_014_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_015 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (io_led_red_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (io_led_red_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (io_led_red_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_015_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_015_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_015_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_015_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_016 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (nios2_timer_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (nios2_timer_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (nios2_timer_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_016_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_016_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_016_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_016_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_017 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (io_keys_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (io_keys_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (io_keys_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_017_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_017_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_017_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_017_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_018 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (io_switches_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (io_switches_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (io_switches_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_018_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_018_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_018_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_018_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_019 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (io_led_green_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (io_led_green_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (io_led_green_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_019_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_019_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_019_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_019_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_020 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (io_hex_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (io_hex_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (io_hex_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_020_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_020_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_020_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_020_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_021 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_0_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_0_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_0_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_021_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_021_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_021_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_021_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_022 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_1_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_1_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_1_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_022_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_022_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_022_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_022_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_023 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_2_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_2_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_2_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_023_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_023_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_023_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_023_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_024 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_3_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_3_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_3_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_024_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_024_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_024_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_024_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_025 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (io_vga_sync_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (io_vga_sync_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (io_vga_sync_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_025_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_025_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_025_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_025_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_026 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_4_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_4_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_4_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_026_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_026_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_026_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_026_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_027 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_5_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_5_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_5_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_027_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_027_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_027_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_027_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_028 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_6_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_6_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_6_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_028_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_028_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_028_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_028_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_029 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_sprite_7_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_sprite_7_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_sprite_7_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_029_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_029_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_029_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_029_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_030 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (vga_background_offset_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (vga_background_offset_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (vga_background_offset_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_030_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_030_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_030_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_030_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_031 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (audio_pio_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (audio_pio_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (audio_pio_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_031_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_031_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_031_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_031_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_032 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (audio_timer_s1_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (audio_timer_s1_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (audio_timer_s1_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_032_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_032_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_032_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_032_out_0_error) // .error
|
|
);
|
|
|
|
ECE385_mm_interconnect_0_avalon_st_adapter #(
|
|
.inBitsPerSymbol (34),
|
|
.inUsePackets (0),
|
|
.inDataWidth (34),
|
|
.inChannelWidth (0),
|
|
.inErrorWidth (0),
|
|
.inUseEmptyPort (0),
|
|
.inUseValid (1),
|
|
.inUseReady (1),
|
|
.inReadyLatency (0),
|
|
.outDataWidth (34),
|
|
.outChannelWidth (0),
|
|
.outErrorWidth (1),
|
|
.outUseEmptyPort (0),
|
|
.outUseValid (1),
|
|
.outUseReady (1),
|
|
.outReadyLatency (0)
|
|
) avalon_st_adapter_033 (
|
|
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
|
|
.in_rst_0_reset (nios2_dma_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
|
|
.in_0_data (usb_keycode_s2_agent_rdata_fifo_src_data), // in_0.data
|
|
.in_0_valid (usb_keycode_s2_agent_rdata_fifo_src_valid), // .valid
|
|
.in_0_ready (usb_keycode_s2_agent_rdata_fifo_src_ready), // .ready
|
|
.out_0_data (avalon_st_adapter_033_out_0_data), // out_0.data
|
|
.out_0_valid (avalon_st_adapter_033_out_0_valid), // .valid
|
|
.out_0_ready (avalon_st_adapter_033_out_0_ready), // .ready
|
|
.out_0_error (avalon_st_adapter_033_out_0_error) // .error
|
|
);
|
|
|
|
endmodule
|