60 lines
1.8 KiB
Verilog
Executable File
60 lines
1.8 KiB
Verilog
Executable File
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module ECE385_io_keys (
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// inputs:
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address,
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clk,
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in_port,
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reset_n,
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// outputs:
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readdata
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)
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;
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output [ 31: 0] readdata;
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input [ 1: 0] address;
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input clk;
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input [ 3: 0] in_port;
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input reset_n;
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wire clk_en;
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wire [ 3: 0] data_in;
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wire [ 3: 0] read_mux_out;
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reg [ 31: 0] readdata;
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assign clk_en = 1;
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//s1, which is an e_avalon_slave
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assign read_mux_out = {4 {(address == 0)}} & data_in;
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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readdata <= 0;
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else if (clk_en)
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readdata <= {32'b0 | read_mux_out};
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end
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assign data_in = in_port;
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endmodule
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