192 lines
30 KiB
Verilog
Executable File
192 lines
30 KiB
Verilog
Executable File
ECE385 u0 (
|
|
.clk_clk (<connected-to-clk_clk>), // clk.clk
|
|
.eth0_mdio_mdc (<connected-to-eth0_mdio_mdc>), // eth0_mdio.mdc
|
|
.eth0_mdio_mdio_in (<connected-to-eth0_mdio_mdio_in>), // .mdio_in
|
|
.eth0_mdio_mdio_out (<connected-to-eth0_mdio_mdio_out>), // .mdio_out
|
|
.eth0_mdio_mdio_oen (<connected-to-eth0_mdio_mdio_oen>), // .mdio_oen
|
|
.eth0_mdio_phy_addr (<connected-to-eth0_mdio_phy_addr>), // .phy_addr
|
|
.eth0_rx_fifo_in_data (<connected-to-eth0_rx_fifo_in_data>), // eth0_rx_fifo_in.data
|
|
.eth0_rx_fifo_in_valid (<connected-to-eth0_rx_fifo_in_valid>), // .valid
|
|
.eth0_rx_fifo_in_ready (<connected-to-eth0_rx_fifo_in_ready>), // .ready
|
|
.eth0_rx_fifo_in_startofpacket (<connected-to-eth0_rx_fifo_in_startofpacket>), // .startofpacket
|
|
.eth0_rx_fifo_in_endofpacket (<connected-to-eth0_rx_fifo_in_endofpacket>), // .endofpacket
|
|
.eth0_rx_fifo_in_error (<connected-to-eth0_rx_fifo_in_error>), // .error
|
|
.eth0_rx_fifo_in_clk_clk (<connected-to-eth0_rx_fifo_in_clk_clk>), // eth0_rx_fifo_in_clk.clk
|
|
.eth0_rx_fifo_in_clk_reset_reset_n (<connected-to-eth0_rx_fifo_in_clk_reset_reset_n>), // eth0_rx_fifo_in_clk_reset.reset_n
|
|
.eth0_tx_dma_buffer_in_0_data (<connected-to-eth0_tx_dma_buffer_in_0_data>), // eth0_tx_dma_buffer_in_0.data
|
|
.eth0_tx_dma_buffer_in_0_valid (<connected-to-eth0_tx_dma_buffer_in_0_valid>), // .valid
|
|
.eth0_tx_dma_buffer_in_0_ready (<connected-to-eth0_tx_dma_buffer_in_0_ready>), // .ready
|
|
.eth0_tx_dma_buffer_in_0_startofpacket (<connected-to-eth0_tx_dma_buffer_in_0_startofpacket>), // .startofpacket
|
|
.eth0_tx_dma_buffer_in_0_endofpacket (<connected-to-eth0_tx_dma_buffer_in_0_endofpacket>), // .endofpacket
|
|
.eth0_tx_dma_buffer_in_0_empty (<connected-to-eth0_tx_dma_buffer_in_0_empty>), // .empty
|
|
.eth0_tx_dma_buffer_in_clk_0_clk (<connected-to-eth0_tx_dma_buffer_in_clk_0_clk>), // eth0_tx_dma_buffer_in_clk_0.clk
|
|
.eth0_tx_dma_buffer_in_rst_0_reset (<connected-to-eth0_tx_dma_buffer_in_rst_0_reset>), // eth0_tx_dma_buffer_in_rst_0.reset
|
|
.eth0_tx_dma_buffer_out_0_data (<connected-to-eth0_tx_dma_buffer_out_0_data>), // eth0_tx_dma_buffer_out_0.data
|
|
.eth0_tx_dma_buffer_out_0_valid (<connected-to-eth0_tx_dma_buffer_out_0_valid>), // .valid
|
|
.eth0_tx_dma_buffer_out_0_ready (<connected-to-eth0_tx_dma_buffer_out_0_ready>), // .ready
|
|
.eth0_tx_dma_buffer_out_0_startofpacket (<connected-to-eth0_tx_dma_buffer_out_0_startofpacket>), // .startofpacket
|
|
.eth0_tx_dma_buffer_out_0_endofpacket (<connected-to-eth0_tx_dma_buffer_out_0_endofpacket>), // .endofpacket
|
|
.eth0_tx_fifo_out_data (<connected-to-eth0_tx_fifo_out_data>), // eth0_tx_fifo_out.data
|
|
.eth0_tx_fifo_out_valid (<connected-to-eth0_tx_fifo_out_valid>), // .valid
|
|
.eth0_tx_fifo_out_ready (<connected-to-eth0_tx_fifo_out_ready>), // .ready
|
|
.eth0_tx_fifo_out_startofpacket (<connected-to-eth0_tx_fifo_out_startofpacket>), // .startofpacket
|
|
.eth0_tx_fifo_out_endofpacket (<connected-to-eth0_tx_fifo_out_endofpacket>), // .endofpacket
|
|
.eth0_tx_fifo_out_empty (<connected-to-eth0_tx_fifo_out_empty>), // .empty
|
|
.eth0_tx_fifo_out_clk_clk (<connected-to-eth0_tx_fifo_out_clk_clk>), // eth0_tx_fifo_out_clk.clk
|
|
.eth0_tx_fifo_out_clk_reset_reset_n (<connected-to-eth0_tx_fifo_out_clk_reset_reset_n>), // eth0_tx_fifo_out_clk_reset.reset_n
|
|
.eth1_mdio_mdc (<connected-to-eth1_mdio_mdc>), // eth1_mdio.mdc
|
|
.eth1_mdio_mdio_in (<connected-to-eth1_mdio_mdio_in>), // .mdio_in
|
|
.eth1_mdio_mdio_out (<connected-to-eth1_mdio_mdio_out>), // .mdio_out
|
|
.eth1_mdio_mdio_oen (<connected-to-eth1_mdio_mdio_oen>), // .mdio_oen
|
|
.eth1_mdio_phy_addr (<connected-to-eth1_mdio_phy_addr>), // .phy_addr
|
|
.eth1_rx_fifo_in_data (<connected-to-eth1_rx_fifo_in_data>), // eth1_rx_fifo_in.data
|
|
.eth1_rx_fifo_in_valid (<connected-to-eth1_rx_fifo_in_valid>), // .valid
|
|
.eth1_rx_fifo_in_ready (<connected-to-eth1_rx_fifo_in_ready>), // .ready
|
|
.eth1_rx_fifo_in_startofpacket (<connected-to-eth1_rx_fifo_in_startofpacket>), // .startofpacket
|
|
.eth1_rx_fifo_in_endofpacket (<connected-to-eth1_rx_fifo_in_endofpacket>), // .endofpacket
|
|
.eth1_rx_fifo_in_error (<connected-to-eth1_rx_fifo_in_error>), // .error
|
|
.eth1_rx_fifo_in_clk_clk (<connected-to-eth1_rx_fifo_in_clk_clk>), // eth1_rx_fifo_in_clk.clk
|
|
.eth1_rx_fifo_in_clk_reset_reset_n (<connected-to-eth1_rx_fifo_in_clk_reset_reset_n>), // eth1_rx_fifo_in_clk_reset.reset_n
|
|
.eth1_tx_dma_buffer_in_0_data (<connected-to-eth1_tx_dma_buffer_in_0_data>), // eth1_tx_dma_buffer_in_0.data
|
|
.eth1_tx_dma_buffer_in_0_valid (<connected-to-eth1_tx_dma_buffer_in_0_valid>), // .valid
|
|
.eth1_tx_dma_buffer_in_0_ready (<connected-to-eth1_tx_dma_buffer_in_0_ready>), // .ready
|
|
.eth1_tx_dma_buffer_in_0_startofpacket (<connected-to-eth1_tx_dma_buffer_in_0_startofpacket>), // .startofpacket
|
|
.eth1_tx_dma_buffer_in_0_endofpacket (<connected-to-eth1_tx_dma_buffer_in_0_endofpacket>), // .endofpacket
|
|
.eth1_tx_dma_buffer_in_0_empty (<connected-to-eth1_tx_dma_buffer_in_0_empty>), // .empty
|
|
.eth1_tx_dma_buffer_in_clk_0_clk (<connected-to-eth1_tx_dma_buffer_in_clk_0_clk>), // eth1_tx_dma_buffer_in_clk_0.clk
|
|
.eth1_tx_dma_buffer_in_rst_0_reset (<connected-to-eth1_tx_dma_buffer_in_rst_0_reset>), // eth1_tx_dma_buffer_in_rst_0.reset
|
|
.eth1_tx_dma_buffer_out_0_data (<connected-to-eth1_tx_dma_buffer_out_0_data>), // eth1_tx_dma_buffer_out_0.data
|
|
.eth1_tx_dma_buffer_out_0_valid (<connected-to-eth1_tx_dma_buffer_out_0_valid>), // .valid
|
|
.eth1_tx_dma_buffer_out_0_ready (<connected-to-eth1_tx_dma_buffer_out_0_ready>), // .ready
|
|
.eth1_tx_dma_buffer_out_0_startofpacket (<connected-to-eth1_tx_dma_buffer_out_0_startofpacket>), // .startofpacket
|
|
.eth1_tx_dma_buffer_out_0_endofpacket (<connected-to-eth1_tx_dma_buffer_out_0_endofpacket>), // .endofpacket
|
|
.eth1_tx_fifo_out_data (<connected-to-eth1_tx_fifo_out_data>), // eth1_tx_fifo_out.data
|
|
.eth1_tx_fifo_out_valid (<connected-to-eth1_tx_fifo_out_valid>), // .valid
|
|
.eth1_tx_fifo_out_ready (<connected-to-eth1_tx_fifo_out_ready>), // .ready
|
|
.eth1_tx_fifo_out_startofpacket (<connected-to-eth1_tx_fifo_out_startofpacket>), // .startofpacket
|
|
.eth1_tx_fifo_out_endofpacket (<connected-to-eth1_tx_fifo_out_endofpacket>), // .endofpacket
|
|
.eth1_tx_fifo_out_empty (<connected-to-eth1_tx_fifo_out_empty>), // .empty
|
|
.eth1_tx_fifo_out_clk_clk (<connected-to-eth1_tx_fifo_out_clk_clk>), // eth1_tx_fifo_out_clk.clk
|
|
.eth1_tx_fifo_out_clk_reset_reset_n (<connected-to-eth1_tx_fifo_out_clk_reset_reset_n>), // eth1_tx_fifo_out_clk_reset.reset_n
|
|
.io_hex_export (<connected-to-io_hex_export>), // io_hex.export
|
|
.io_keys_export (<connected-to-io_keys_export>), // io_keys.export
|
|
.io_led_green_export (<connected-to-io_led_green_export>), // io_led_green.export
|
|
.io_led_red_export (<connected-to-io_led_red_export>), // io_led_red.export
|
|
.io_switches_export (<connected-to-io_switches_export>), // io_switches.export
|
|
.io_vga_sync_export (<connected-to-io_vga_sync_export>), // io_vga_sync.export
|
|
.nios2_pll_ethernet_clk (<connected-to-nios2_pll_ethernet_clk>), // nios2_pll_ethernet.clk
|
|
.nios2_pll_sdram_clk (<connected-to-nios2_pll_sdram_clk>), // nios2_pll_sdram.clk
|
|
.nios2_pll_vga_clk (<connected-to-nios2_pll_vga_clk>), // nios2_pll_vga.clk
|
|
.otg_hpi_address_export (<connected-to-otg_hpi_address_export>), // otg_hpi_address.export
|
|
.otg_hpi_cs_export (<connected-to-otg_hpi_cs_export>), // otg_hpi_cs.export
|
|
.otg_hpi_data_in_port (<connected-to-otg_hpi_data_in_port>), // otg_hpi_data.in_port
|
|
.otg_hpi_data_out_port (<connected-to-otg_hpi_data_out_port>), // .out_port
|
|
.otg_hpi_r_export (<connected-to-otg_hpi_r_export>), // otg_hpi_r.export
|
|
.otg_hpi_reset_export (<connected-to-otg_hpi_reset_export>), // otg_hpi_reset.export
|
|
.otg_hpi_w_export (<connected-to-otg_hpi_w_export>), // otg_hpi_w.export
|
|
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
|
|
.sdram_addr (<connected-to-sdram_addr>), // sdram.addr
|
|
.sdram_ba (<connected-to-sdram_ba>), // .ba
|
|
.sdram_cas_n (<connected-to-sdram_cas_n>), // .cas_n
|
|
.sdram_cke (<connected-to-sdram_cke>), // .cke
|
|
.sdram_cs_n (<connected-to-sdram_cs_n>), // .cs_n
|
|
.sdram_dq (<connected-to-sdram_dq>), // .dq
|
|
.sdram_dqm (<connected-to-sdram_dqm>), // .dqm
|
|
.sdram_ras_n (<connected-to-sdram_ras_n>), // .ras_n
|
|
.sdram_we_n (<connected-to-sdram_we_n>), // .we_n
|
|
.sram_sram_addr (<connected-to-sram_sram_addr>), // sram.sram_addr
|
|
.sram_sram_ce_n (<connected-to-sram_sram_ce_n>), // .sram_ce_n
|
|
.sram_sram_dq (<connected-to-sram_sram_dq>), // .sram_dq
|
|
.sram_sram_lb_n (<connected-to-sram_sram_lb_n>), // .sram_lb_n
|
|
.sram_sram_oe_n (<connected-to-sram_sram_oe_n>), // .sram_oe_n
|
|
.sram_sram_ub_n (<connected-to-sram_sram_ub_n>), // .sram_ub_n
|
|
.sram_sram_we_n (<connected-to-sram_sram_we_n>), // .sram_we_n
|
|
.usb_clk_clk (<connected-to-usb_clk_clk>), // usb_clk.clk
|
|
.usb_nios2_cpu_custom_instruction_master_readra (<connected-to-usb_nios2_cpu_custom_instruction_master_readra>), // usb_nios2_cpu_custom_instruction_master.readra
|
|
.usb_reset_reset_n (<connected-to-usb_reset_reset_n>), // usb_reset.reset_n
|
|
.vga_vga_drawx (<connected-to-vga_vga_drawx>), // vga.vga_drawx
|
|
.vga_vga_drawy (<connected-to-vga_vga_drawy>), // .vga_drawy
|
|
.vga_vga_val (<connected-to-vga_vga_val>), // .vga_val
|
|
.vga_background_offset_export (<connected-to-vga_background_offset_export>), // vga_background_offset.export
|
|
.vga_sprite_0_clk2_clk (<connected-to-vga_sprite_0_clk2_clk>), // vga_sprite_0_clk2.clk
|
|
.vga_sprite_0_reset2_reset (<connected-to-vga_sprite_0_reset2_reset>), // vga_sprite_0_reset2.reset
|
|
.vga_sprite_0_s2_address (<connected-to-vga_sprite_0_s2_address>), // vga_sprite_0_s2.address
|
|
.vga_sprite_0_s2_chipselect (<connected-to-vga_sprite_0_s2_chipselect>), // .chipselect
|
|
.vga_sprite_0_s2_clken (<connected-to-vga_sprite_0_s2_clken>), // .clken
|
|
.vga_sprite_0_s2_write (<connected-to-vga_sprite_0_s2_write>), // .write
|
|
.vga_sprite_0_s2_readdata (<connected-to-vga_sprite_0_s2_readdata>), // .readdata
|
|
.vga_sprite_0_s2_writedata (<connected-to-vga_sprite_0_s2_writedata>), // .writedata
|
|
.vga_sprite_0_s2_byteenable (<connected-to-vga_sprite_0_s2_byteenable>), // .byteenable
|
|
.vga_sprite_1_clk2_clk (<connected-to-vga_sprite_1_clk2_clk>), // vga_sprite_1_clk2.clk
|
|
.vga_sprite_1_reset2_reset (<connected-to-vga_sprite_1_reset2_reset>), // vga_sprite_1_reset2.reset
|
|
.vga_sprite_1_s2_address (<connected-to-vga_sprite_1_s2_address>), // vga_sprite_1_s2.address
|
|
.vga_sprite_1_s2_chipselect (<connected-to-vga_sprite_1_s2_chipselect>), // .chipselect
|
|
.vga_sprite_1_s2_clken (<connected-to-vga_sprite_1_s2_clken>), // .clken
|
|
.vga_sprite_1_s2_write (<connected-to-vga_sprite_1_s2_write>), // .write
|
|
.vga_sprite_1_s2_readdata (<connected-to-vga_sprite_1_s2_readdata>), // .readdata
|
|
.vga_sprite_1_s2_writedata (<connected-to-vga_sprite_1_s2_writedata>), // .writedata
|
|
.vga_sprite_1_s2_byteenable (<connected-to-vga_sprite_1_s2_byteenable>), // .byteenable
|
|
.vga_sprite_2_clk2_clk (<connected-to-vga_sprite_2_clk2_clk>), // vga_sprite_2_clk2.clk
|
|
.vga_sprite_2_reset2_reset (<connected-to-vga_sprite_2_reset2_reset>), // vga_sprite_2_reset2.reset
|
|
.vga_sprite_2_s2_address (<connected-to-vga_sprite_2_s2_address>), // vga_sprite_2_s2.address
|
|
.vga_sprite_2_s2_chipselect (<connected-to-vga_sprite_2_s2_chipselect>), // .chipselect
|
|
.vga_sprite_2_s2_clken (<connected-to-vga_sprite_2_s2_clken>), // .clken
|
|
.vga_sprite_2_s2_write (<connected-to-vga_sprite_2_s2_write>), // .write
|
|
.vga_sprite_2_s2_readdata (<connected-to-vga_sprite_2_s2_readdata>), // .readdata
|
|
.vga_sprite_2_s2_writedata (<connected-to-vga_sprite_2_s2_writedata>), // .writedata
|
|
.vga_sprite_2_s2_byteenable (<connected-to-vga_sprite_2_s2_byteenable>), // .byteenable
|
|
.vga_sprite_3_clk2_clk (<connected-to-vga_sprite_3_clk2_clk>), // vga_sprite_3_clk2.clk
|
|
.vga_sprite_3_reset2_reset (<connected-to-vga_sprite_3_reset2_reset>), // vga_sprite_3_reset2.reset
|
|
.vga_sprite_3_s2_address (<connected-to-vga_sprite_3_s2_address>), // vga_sprite_3_s2.address
|
|
.vga_sprite_3_s2_chipselect (<connected-to-vga_sprite_3_s2_chipselect>), // .chipselect
|
|
.vga_sprite_3_s2_clken (<connected-to-vga_sprite_3_s2_clken>), // .clken
|
|
.vga_sprite_3_s2_write (<connected-to-vga_sprite_3_s2_write>), // .write
|
|
.vga_sprite_3_s2_readdata (<connected-to-vga_sprite_3_s2_readdata>), // .readdata
|
|
.vga_sprite_3_s2_writedata (<connected-to-vga_sprite_3_s2_writedata>), // .writedata
|
|
.vga_sprite_3_s2_byteenable (<connected-to-vga_sprite_3_s2_byteenable>), // .byteenable
|
|
.vga_sprite_4_clk2_clk (<connected-to-vga_sprite_4_clk2_clk>), // vga_sprite_4_clk2.clk
|
|
.vga_sprite_4_reset2_reset (<connected-to-vga_sprite_4_reset2_reset>), // vga_sprite_4_reset2.reset
|
|
.vga_sprite_4_s2_address (<connected-to-vga_sprite_4_s2_address>), // vga_sprite_4_s2.address
|
|
.vga_sprite_4_s2_chipselect (<connected-to-vga_sprite_4_s2_chipselect>), // .chipselect
|
|
.vga_sprite_4_s2_clken (<connected-to-vga_sprite_4_s2_clken>), // .clken
|
|
.vga_sprite_4_s2_write (<connected-to-vga_sprite_4_s2_write>), // .write
|
|
.vga_sprite_4_s2_readdata (<connected-to-vga_sprite_4_s2_readdata>), // .readdata
|
|
.vga_sprite_4_s2_writedata (<connected-to-vga_sprite_4_s2_writedata>), // .writedata
|
|
.vga_sprite_4_s2_byteenable (<connected-to-vga_sprite_4_s2_byteenable>), // .byteenable
|
|
.vga_sprite_5_clk2_clk (<connected-to-vga_sprite_5_clk2_clk>), // vga_sprite_5_clk2.clk
|
|
.vga_sprite_5_reset2_reset (<connected-to-vga_sprite_5_reset2_reset>), // vga_sprite_5_reset2.reset
|
|
.vga_sprite_5_s2_address (<connected-to-vga_sprite_5_s2_address>), // vga_sprite_5_s2.address
|
|
.vga_sprite_5_s2_chipselect (<connected-to-vga_sprite_5_s2_chipselect>), // .chipselect
|
|
.vga_sprite_5_s2_clken (<connected-to-vga_sprite_5_s2_clken>), // .clken
|
|
.vga_sprite_5_s2_write (<connected-to-vga_sprite_5_s2_write>), // .write
|
|
.vga_sprite_5_s2_readdata (<connected-to-vga_sprite_5_s2_readdata>), // .readdata
|
|
.vga_sprite_5_s2_writedata (<connected-to-vga_sprite_5_s2_writedata>), // .writedata
|
|
.vga_sprite_5_s2_byteenable (<connected-to-vga_sprite_5_s2_byteenable>), // .byteenable
|
|
.vga_sprite_6_clk2_clk (<connected-to-vga_sprite_6_clk2_clk>), // vga_sprite_6_clk2.clk
|
|
.vga_sprite_6_reset2_reset (<connected-to-vga_sprite_6_reset2_reset>), // vga_sprite_6_reset2.reset
|
|
.vga_sprite_6_s2_address (<connected-to-vga_sprite_6_s2_address>), // vga_sprite_6_s2.address
|
|
.vga_sprite_6_s2_chipselect (<connected-to-vga_sprite_6_s2_chipselect>), // .chipselect
|
|
.vga_sprite_6_s2_clken (<connected-to-vga_sprite_6_s2_clken>), // .clken
|
|
.vga_sprite_6_s2_write (<connected-to-vga_sprite_6_s2_write>), // .write
|
|
.vga_sprite_6_s2_readdata (<connected-to-vga_sprite_6_s2_readdata>), // .readdata
|
|
.vga_sprite_6_s2_writedata (<connected-to-vga_sprite_6_s2_writedata>), // .writedata
|
|
.vga_sprite_6_s2_byteenable (<connected-to-vga_sprite_6_s2_byteenable>), // .byteenable
|
|
.vga_sprite_7_clk2_clk (<connected-to-vga_sprite_7_clk2_clk>), // vga_sprite_7_clk2.clk
|
|
.vga_sprite_7_reset2_reset (<connected-to-vga_sprite_7_reset2_reset>), // vga_sprite_7_reset2.reset
|
|
.vga_sprite_7_s2_address (<connected-to-vga_sprite_7_s2_address>), // vga_sprite_7_s2.address
|
|
.vga_sprite_7_s2_chipselect (<connected-to-vga_sprite_7_s2_chipselect>), // .chipselect
|
|
.vga_sprite_7_s2_clken (<connected-to-vga_sprite_7_s2_clken>), // .clken
|
|
.vga_sprite_7_s2_write (<connected-to-vga_sprite_7_s2_write>), // .write
|
|
.vga_sprite_7_s2_readdata (<connected-to-vga_sprite_7_s2_readdata>), // .readdata
|
|
.vga_sprite_7_s2_writedata (<connected-to-vga_sprite_7_s2_writedata>), // .writedata
|
|
.vga_sprite_7_s2_byteenable (<connected-to-vga_sprite_7_s2_byteenable>), // .byteenable
|
|
.vga_sprite_params_pass_address (<connected-to-vga_sprite_params_pass_address>), // vga_sprite_params_pass.address
|
|
.vga_sprite_params_pass_read (<connected-to-vga_sprite_params_pass_read>), // .read
|
|
.vga_sprite_params_pass_readdata (<connected-to-vga_sprite_params_pass_readdata>), // .readdata
|
|
.vga_sprite_params_pass_write (<connected-to-vga_sprite_params_pass_write>), // .write
|
|
.vga_sprite_params_pass_writedata (<connected-to-vga_sprite_params_pass_writedata>), // .writedata
|
|
.vga_sprite_params_reset_reset (<connected-to-vga_sprite_params_reset_reset>), // vga_sprite_params_reset.reset
|
|
.audio_pio_export (<connected-to-audio_pio_export>) // audio_pio.export
|
|
);
|
|
|