419 lines
59 KiB
Groff
419 lines
59 KiB
Groff
Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate C:\Users\xuyh0\Desktop\zjui-ece385\final\ECE385.qsys --synthesis=VERILOG --output-directory=C:\Users\xuyh0\Desktop\zjui-ece385\final\qsys\synthesis --family="Cyclone IV E" --part=EP4CE115F29C7
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Progress: Loading final/ECE385.qsys
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Progress: Reading input file
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Progress: Adding audio_pio [altera_avalon_pio 18.1]
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Progress: Parameterizing module audio_pio
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Progress: Adding audio_timer [altera_avalon_timer 18.1]
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Progress: Parameterizing module audio_timer
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Progress: Adding clk_0 [clock_source 18.1]
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Progress: Parameterizing module clk_0
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Progress: Adding eth0_mdio [lantian_mdio 1.0]
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Progress: Parameterizing module eth0_mdio
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Progress: Adding eth0_rx_dma [altera_avalon_sgdma 18.1]
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Progress: Parameterizing module eth0_rx_dma
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Progress: Adding eth0_rx_fifo [altera_avalon_dc_fifo 18.1]
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Progress: Parameterizing module eth0_rx_fifo
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Progress: Adding eth0_tx_dma [altera_avalon_sgdma 18.1]
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Progress: Parameterizing module eth0_tx_dma
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Progress: Adding eth0_tx_dma_buffer [altera_avalon_st_adapter 18.1]
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Progress: Parameterizing module eth0_tx_dma_buffer
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Progress: Adding eth0_tx_fifo [altera_avalon_dc_fifo 18.1]
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Progress: Parameterizing module eth0_tx_fifo
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Progress: Adding eth1_mdio [lantian_mdio 1.0]
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Progress: Parameterizing module eth1_mdio
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Progress: Adding eth1_rx_dma [altera_avalon_sgdma 18.1]
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Progress: Parameterizing module eth1_rx_dma
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Progress: Adding eth1_rx_fifo [altera_avalon_dc_fifo 18.1]
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Progress: Parameterizing module eth1_rx_fifo
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Progress: Adding eth1_tx_dma [altera_avalon_sgdma 18.1]
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Progress: Parameterizing module eth1_tx_dma
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Progress: Adding eth1_tx_dma_buffer [altera_avalon_st_adapter 18.1]
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Progress: Parameterizing module eth1_tx_dma_buffer
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Progress: Adding eth1_tx_fifo [altera_avalon_dc_fifo 18.1]
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Progress: Parameterizing module eth1_tx_fifo
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Progress: Adding io_hex [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_hex
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Progress: Adding io_keys [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_keys
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Progress: Adding io_led_green [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_led_green
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Progress: Adding io_led_red [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_led_red
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Progress: Adding io_switches [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_switches
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Progress: Adding io_vga_sync [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_vga_sync
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Progress: Adding nios2_cpu [altera_nios2_gen2 18.1]
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Progress: Parameterizing module nios2_cpu
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Progress: Adding nios2_dma [altera_avalon_sgdma 18.1]
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Progress: Parameterizing module nios2_dma
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Progress: Adding nios2_jtag_uart [altera_avalon_jtag_uart 18.1]
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Progress: Parameterizing module nios2_jtag_uart
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Progress: Adding nios2_onchip_mem [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module nios2_onchip_mem
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Progress: Adding nios2_pll [altpll 18.1]
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Progress: Parameterizing module nios2_pll
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Progress: Adding nios2_sysid [altera_avalon_sysid_qsys 18.1]
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Progress: Parameterizing module nios2_sysid
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Progress: Adding nios2_timer [altera_avalon_timer 18.1]
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Progress: Parameterizing module nios2_timer
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Progress: Adding sdram [altera_avalon_new_sdram_controller 18.1]
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Progress: Parameterizing module sdram
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Progress: Adding sram_multiplexer [sram_multiplexer 1.0]
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Progress: Parameterizing module sram_multiplexer
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Progress: Adding usb_clk [clock_source 18.1]
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Progress: Parameterizing module usb_clk
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Progress: Adding usb_hpi_address [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_address
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Progress: Adding usb_hpi_cs [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_cs
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Progress: Adding usb_hpi_data [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_data
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Progress: Adding usb_hpi_r [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_r
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Progress: Adding usb_hpi_reset [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_reset
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Progress: Adding usb_hpi_w [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_w
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Progress: Adding usb_jtag_uart [altera_avalon_jtag_uart 18.1]
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Progress: Parameterizing module usb_jtag_uart
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Progress: Adding usb_keycode [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module usb_keycode
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Progress: Adding usb_nios2_cpu [altera_nios2_gen2 18.1]
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Progress: Parameterizing module usb_nios2_cpu
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Progress: Adding usb_nios2_onchip_mem [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module usb_nios2_onchip_mem
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Progress: Adding usb_nios2_sysid [altera_avalon_sysid_qsys 18.1]
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Progress: Parameterizing module usb_nios2_sysid
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Progress: Adding vga_background_offset [altera_avalon_pio 18.1]
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Progress: Parameterizing module vga_background_offset
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Progress: Adding vga_sprite_0 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_0
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Progress: Adding vga_sprite_1 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_1
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Progress: Adding vga_sprite_2 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_2
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Progress: Adding vga_sprite_3 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_3
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Progress: Adding vga_sprite_4 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_4
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Progress: Adding vga_sprite_5 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_5
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Progress: Adding vga_sprite_6 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_6
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Progress: Adding vga_sprite_7 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_7
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Progress: Adding vga_sprite_params [avalon_mm_passthrough 1.0]
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Progress: Parameterizing module vga_sprite_params
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: ECE385.eth0_rx_dma: Scatter-Gather DMA Controller will only be supported in Quartus Prime Standard Edition in the future release.
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Info: ECE385.eth0_tx_dma: Scatter-Gather DMA Controller will only be supported in Quartus Prime Standard Edition in the future release.
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Info: ECE385.eth0_tx_dma_buffer: Inserting data_format_adapter: data_format_adapter_0
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Info: ECE385.eth1_rx_dma: Scatter-Gather DMA Controller will only be supported in Quartus Prime Standard Edition in the future release.
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Info: ECE385.eth1_tx_dma: Scatter-Gather DMA Controller will only be supported in Quartus Prime Standard Edition in the future release.
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Info: ECE385.eth1_tx_dma_buffer: Inserting data_format_adapter: data_format_adapter_0
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Info: ECE385.io_keys: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.io_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.io_vga_sync: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.nios2_dma: Scatter-Gather DMA Controller will only be supported in Quartus Prime Standard Edition in the future release.
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Info: ECE385.nios2_jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
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Info: ECE385.nios2_sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
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Info: ECE385.nios2_sysid: Time stamp will be automatically updated when this component is generated.
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Info: ECE385.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
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Info: ECE385.usb_hpi_data: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.usb_jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
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Info: ECE385.usb_nios2_sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
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Info: ECE385.usb_nios2_sysid: Time stamp will be automatically updated when this component is generated.
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Info: ECE385: Generating ECE385 "ECE385" for QUARTUS_SYNTH
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Info: audio_pio: Starting RTL generation for module 'ECE385_audio_pio'
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Info: audio_pio: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_audio_pio --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0002_audio_pio_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0002_audio_pio_gen//ECE385_audio_pio_component_configuration.pl --do_build_sim=0 ]
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Info: audio_pio: Done RTL generation for module 'ECE385_audio_pio'
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Info: audio_pio: "ECE385" instantiated altera_avalon_pio "audio_pio"
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Info: audio_timer: Starting RTL generation for module 'ECE385_audio_timer'
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Info: audio_timer: Generation command is [exec D:/Softwares/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I D:/Softwares/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=ECE385_audio_timer --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0003_audio_timer_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0003_audio_timer_gen//ECE385_audio_timer_component_configuration.pl --do_build_sim=0 ]
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Info: audio_timer: Done RTL generation for module 'ECE385_audio_timer'
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Info: audio_timer: "ECE385" instantiated altera_avalon_timer "audio_timer"
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Info: eth0_mdio: "ECE385" instantiated lantian_mdio "eth0_mdio"
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Info: eth0_rx_dma: Starting RTL generation for module 'ECE385_eth0_rx_dma'
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Info: eth0_rx_dma: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_sgdma -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_sgdma/generate_rtl.pl --name=ECE385_eth0_rx_dma --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0005_eth0_rx_dma_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0005_eth0_rx_dma_gen//ECE385_eth0_rx_dma_component_configuration.pl --do_build_sim=0 ]
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Info: eth0_rx_dma: Done RTL generation for module 'ECE385_eth0_rx_dma'
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Info: eth0_rx_dma: "ECE385" instantiated altera_avalon_sgdma "eth0_rx_dma"
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Info: eth0_rx_fifo: "ECE385" instantiated altera_avalon_dc_fifo "eth0_rx_fifo"
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Info: eth0_tx_dma: Starting RTL generation for module 'ECE385_eth0_tx_dma'
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Info: eth0_tx_dma: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_sgdma -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_sgdma/generate_rtl.pl --name=ECE385_eth0_tx_dma --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0007_eth0_tx_dma_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0007_eth0_tx_dma_gen//ECE385_eth0_tx_dma_component_configuration.pl --do_build_sim=0 ]
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Info: eth0_tx_dma: Done RTL generation for module 'ECE385_eth0_tx_dma'
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Info: eth0_tx_dma: "ECE385" instantiated altera_avalon_sgdma "eth0_tx_dma"
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Info: eth0_tx_dma_buffer: "ECE385" instantiated altera_avalon_st_adapter "eth0_tx_dma_buffer"
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Info: eth1_tx_dma: Starting RTL generation for module 'ECE385_eth1_tx_dma'
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Info: eth1_tx_dma: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_sgdma -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_sgdma/generate_rtl.pl --name=ECE385_eth1_tx_dma --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0008_eth1_tx_dma_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0008_eth1_tx_dma_gen//ECE385_eth1_tx_dma_component_configuration.pl --do_build_sim=0 ]
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Info: eth1_tx_dma: Done RTL generation for module 'ECE385_eth1_tx_dma'
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Info: eth1_tx_dma: "ECE385" instantiated altera_avalon_sgdma "eth1_tx_dma"
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Info: io_hex: Starting RTL generation for module 'ECE385_io_hex'
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Info: io_hex: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_io_hex --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0009_io_hex_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0009_io_hex_gen//ECE385_io_hex_component_configuration.pl --do_build_sim=0 ]
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Info: io_hex: Done RTL generation for module 'ECE385_io_hex'
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Info: io_hex: "ECE385" instantiated altera_avalon_pio "io_hex"
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Info: io_keys: Starting RTL generation for module 'ECE385_io_keys'
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Info: io_keys: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_io_keys --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0010_io_keys_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0010_io_keys_gen//ECE385_io_keys_component_configuration.pl --do_build_sim=0 ]
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Info: io_keys: Done RTL generation for module 'ECE385_io_keys'
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Info: io_keys: "ECE385" instantiated altera_avalon_pio "io_keys"
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Info: io_led_green: Starting RTL generation for module 'ECE385_io_led_green'
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Info: io_led_green: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_io_led_green --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0011_io_led_green_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0011_io_led_green_gen//ECE385_io_led_green_component_configuration.pl --do_build_sim=0 ]
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Info: io_led_green: Done RTL generation for module 'ECE385_io_led_green'
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Info: io_led_green: "ECE385" instantiated altera_avalon_pio "io_led_green"
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Info: io_led_red: Starting RTL generation for module 'ECE385_io_led_red'
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Info: io_led_red: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_io_led_red --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0012_io_led_red_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0012_io_led_red_gen//ECE385_io_led_red_component_configuration.pl --do_build_sim=0 ]
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Info: io_led_red: Done RTL generation for module 'ECE385_io_led_red'
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Info: io_led_red: "ECE385" instantiated altera_avalon_pio "io_led_red"
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Info: io_switches: Starting RTL generation for module 'ECE385_io_switches'
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Info: io_switches: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_io_switches --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0013_io_switches_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0013_io_switches_gen//ECE385_io_switches_component_configuration.pl --do_build_sim=0 ]
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Info: io_switches: Done RTL generation for module 'ECE385_io_switches'
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Info: io_switches: "ECE385" instantiated altera_avalon_pio "io_switches"
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Info: io_vga_sync: Starting RTL generation for module 'ECE385_io_vga_sync'
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Info: io_vga_sync: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_io_vga_sync --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0014_io_vga_sync_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0014_io_vga_sync_gen//ECE385_io_vga_sync_component_configuration.pl --do_build_sim=0 ]
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Info: io_vga_sync: Done RTL generation for module 'ECE385_io_vga_sync'
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Info: io_vga_sync: "ECE385" instantiated altera_avalon_pio "io_vga_sync"
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Info: nios2_cpu: "ECE385" instantiated altera_nios2_gen2 "nios2_cpu"
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Info: nios2_dma: Starting RTL generation for module 'ECE385_nios2_dma'
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Info: nios2_dma: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_sgdma -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_sgdma/generate_rtl.pl --name=ECE385_nios2_dma --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0015_nios2_dma_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0015_nios2_dma_gen//ECE385_nios2_dma_component_configuration.pl --do_build_sim=0 ]
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Info: nios2_dma: Done RTL generation for module 'ECE385_nios2_dma'
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Info: nios2_dma: "ECE385" instantiated altera_avalon_sgdma "nios2_dma"
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Info: nios2_jtag_uart: Starting RTL generation for module 'ECE385_nios2_jtag_uart'
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Info: nios2_jtag_uart: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=ECE385_nios2_jtag_uart --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0016_nios2_jtag_uart_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0016_nios2_jtag_uart_gen//ECE385_nios2_jtag_uart_component_configuration.pl --do_build_sim=0 ]
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Info: nios2_jtag_uart: Done RTL generation for module 'ECE385_nios2_jtag_uart'
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Info: nios2_jtag_uart: "ECE385" instantiated altera_avalon_jtag_uart "nios2_jtag_uart"
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Info: nios2_onchip_mem: Starting RTL generation for module 'ECE385_nios2_onchip_mem'
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Info: nios2_onchip_mem: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_nios2_onchip_mem --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0017_nios2_onchip_mem_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0017_nios2_onchip_mem_gen//ECE385_nios2_onchip_mem_component_configuration.pl --do_build_sim=0 ]
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Info: nios2_onchip_mem: Done RTL generation for module 'ECE385_nios2_onchip_mem'
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Info: nios2_onchip_mem: "ECE385" instantiated altera_avalon_onchip_memory2 "nios2_onchip_mem"
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Info: nios2_pll: "ECE385" instantiated altpll "nios2_pll"
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Info: nios2_sysid: "ECE385" instantiated altera_avalon_sysid_qsys "nios2_sysid"
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Info: nios2_timer: Starting RTL generation for module 'ECE385_nios2_timer'
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Info: nios2_timer: Generation command is [exec D:/Softwares/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I D:/Softwares/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=ECE385_nios2_timer --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0021_nios2_timer_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0021_nios2_timer_gen//ECE385_nios2_timer_component_configuration.pl --do_build_sim=0 ]
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Info: nios2_timer: Done RTL generation for module 'ECE385_nios2_timer'
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Info: nios2_timer: "ECE385" instantiated altera_avalon_timer "nios2_timer"
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Info: sdram: Starting RTL generation for module 'ECE385_sdram'
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Info: sdram: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=ECE385_sdram --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0022_sdram_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0022_sdram_gen//ECE385_sdram_component_configuration.pl --do_build_sim=0 ]
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Info: sdram: Done RTL generation for module 'ECE385_sdram'
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Info: sdram: "ECE385" instantiated altera_avalon_new_sdram_controller "sdram"
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Info: sram_multiplexer: "ECE385" instantiated sram_multiplexer "sram_multiplexer"
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Info: usb_hpi_address: Starting RTL generation for module 'ECE385_usb_hpi_address'
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Info: usb_hpi_address: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_usb_hpi_address --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0024_usb_hpi_address_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0024_usb_hpi_address_gen//ECE385_usb_hpi_address_component_configuration.pl --do_build_sim=0 ]
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Info: usb_hpi_address: Done RTL generation for module 'ECE385_usb_hpi_address'
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Info: usb_hpi_address: "ECE385" instantiated altera_avalon_pio "usb_hpi_address"
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Info: usb_hpi_cs: Starting RTL generation for module 'ECE385_usb_hpi_cs'
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Info: usb_hpi_cs: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_usb_hpi_cs --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0025_usb_hpi_cs_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0025_usb_hpi_cs_gen//ECE385_usb_hpi_cs_component_configuration.pl --do_build_sim=0 ]
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Info: usb_hpi_cs: Done RTL generation for module 'ECE385_usb_hpi_cs'
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Info: usb_hpi_cs: "ECE385" instantiated altera_avalon_pio "usb_hpi_cs"
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Info: usb_hpi_data: Starting RTL generation for module 'ECE385_usb_hpi_data'
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Info: usb_hpi_data: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ECE385_usb_hpi_data --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0026_usb_hpi_data_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0026_usb_hpi_data_gen//ECE385_usb_hpi_data_component_configuration.pl --do_build_sim=0 ]
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Info: usb_hpi_data: Done RTL generation for module 'ECE385_usb_hpi_data'
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Info: usb_hpi_data: "ECE385" instantiated altera_avalon_pio "usb_hpi_data"
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Info: usb_keycode: Starting RTL generation for module 'ECE385_usb_keycode'
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Info: usb_keycode: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_usb_keycode --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0027_usb_keycode_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0027_usb_keycode_gen//ECE385_usb_keycode_component_configuration.pl --do_build_sim=0 ]
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Info: usb_keycode: Done RTL generation for module 'ECE385_usb_keycode'
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Info: usb_keycode: "ECE385" instantiated altera_avalon_onchip_memory2 "usb_keycode"
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Info: usb_nios2_cpu: "ECE385" instantiated altera_nios2_gen2 "usb_nios2_cpu"
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Info: usb_nios2_onchip_mem: Starting RTL generation for module 'ECE385_usb_nios2_onchip_mem'
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Info: usb_nios2_onchip_mem: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_usb_nios2_onchip_mem --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0028_usb_nios2_onchip_mem_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0028_usb_nios2_onchip_mem_gen//ECE385_usb_nios2_onchip_mem_component_configuration.pl --do_build_sim=0 ]
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Info: usb_nios2_onchip_mem: Done RTL generation for module 'ECE385_usb_nios2_onchip_mem'
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Info: usb_nios2_onchip_mem: "ECE385" instantiated altera_avalon_onchip_memory2 "usb_nios2_onchip_mem"
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Info: vga_sprite_0: Starting RTL generation for module 'ECE385_vga_sprite_0'
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Info: vga_sprite_0: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_vga_sprite_0 --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0029_vga_sprite_0_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0029_vga_sprite_0_gen//ECE385_vga_sprite_0_component_configuration.pl --do_build_sim=0 ]
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Info: vga_sprite_0: Done RTL generation for module 'ECE385_vga_sprite_0'
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Info: vga_sprite_0: "ECE385" instantiated altera_avalon_onchip_memory2 "vga_sprite_0"
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Info: vga_sprite_1: Starting RTL generation for module 'ECE385_vga_sprite_1'
|
|
Info: vga_sprite_1: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_vga_sprite_1 --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0030_vga_sprite_1_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0030_vga_sprite_1_gen//ECE385_vga_sprite_1_component_configuration.pl --do_build_sim=0 ]
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|
Info: vga_sprite_1: Done RTL generation for module 'ECE385_vga_sprite_1'
|
|
Info: vga_sprite_1: "ECE385" instantiated altera_avalon_onchip_memory2 "vga_sprite_1"
|
|
Info: vga_sprite_2: Starting RTL generation for module 'ECE385_vga_sprite_2'
|
|
Info: vga_sprite_2: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_vga_sprite_2 --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0031_vga_sprite_2_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0031_vga_sprite_2_gen//ECE385_vga_sprite_2_component_configuration.pl --do_build_sim=0 ]
|
|
Info: vga_sprite_2: Done RTL generation for module 'ECE385_vga_sprite_2'
|
|
Info: vga_sprite_2: "ECE385" instantiated altera_avalon_onchip_memory2 "vga_sprite_2"
|
|
Info: vga_sprite_3: Starting RTL generation for module 'ECE385_vga_sprite_3'
|
|
Info: vga_sprite_3: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_vga_sprite_3 --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0032_vga_sprite_3_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0032_vga_sprite_3_gen//ECE385_vga_sprite_3_component_configuration.pl --do_build_sim=0 ]
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|
Info: vga_sprite_3: Done RTL generation for module 'ECE385_vga_sprite_3'
|
|
Info: vga_sprite_3: "ECE385" instantiated altera_avalon_onchip_memory2 "vga_sprite_3"
|
|
Info: vga_sprite_4: Starting RTL generation for module 'ECE385_vga_sprite_4'
|
|
Info: vga_sprite_4: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_vga_sprite_4 --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0033_vga_sprite_4_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0033_vga_sprite_4_gen//ECE385_vga_sprite_4_component_configuration.pl --do_build_sim=0 ]
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|
Info: vga_sprite_4: Done RTL generation for module 'ECE385_vga_sprite_4'
|
|
Info: vga_sprite_4: "ECE385" instantiated altera_avalon_onchip_memory2 "vga_sprite_4"
|
|
Info: vga_sprite_5: Starting RTL generation for module 'ECE385_vga_sprite_5'
|
|
Info: vga_sprite_5: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_vga_sprite_5 --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0034_vga_sprite_5_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0034_vga_sprite_5_gen//ECE385_vga_sprite_5_component_configuration.pl --do_build_sim=0 ]
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|
Info: vga_sprite_5: Done RTL generation for module 'ECE385_vga_sprite_5'
|
|
Info: vga_sprite_5: "ECE385" instantiated altera_avalon_onchip_memory2 "vga_sprite_5"
|
|
Info: vga_sprite_6: Starting RTL generation for module 'ECE385_vga_sprite_6'
|
|
Info: vga_sprite_6: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_vga_sprite_6 --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0035_vga_sprite_6_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0035_vga_sprite_6_gen//ECE385_vga_sprite_6_component_configuration.pl --do_build_sim=0 ]
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Info: vga_sprite_6: Done RTL generation for module 'ECE385_vga_sprite_6'
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|
Info: vga_sprite_6: "ECE385" instantiated altera_avalon_onchip_memory2 "vga_sprite_6"
|
|
Info: vga_sprite_7: Starting RTL generation for module 'ECE385_vga_sprite_7'
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|
Info: vga_sprite_7: Generation command is [exec D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I D:/softwares/intelfpga_lite/18.1/quartus/bin64/perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ECE385_vga_sprite_7 --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0036_vga_sprite_7_gen/ --quartus_dir=D:/softwares/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0036_vga_sprite_7_gen//ECE385_vga_sprite_7_component_configuration.pl --do_build_sim=0 ]
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|
Info: vga_sprite_7: Done RTL generation for module 'ECE385_vga_sprite_7'
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Info: vga_sprite_7: "ECE385" instantiated altera_avalon_onchip_memory2 "vga_sprite_7"
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Info: vga_sprite_params: "ECE385" instantiated avalon_mm_passthrough "vga_sprite_params"
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Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
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|
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0
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|
Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_022: Inserting error_adapter: error_adapter_0
|
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Info: avalon_st_adapter_023: Inserting error_adapter: error_adapter_0
|
|
Info: avalon_st_adapter_024: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_025: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_026: Inserting error_adapter: error_adapter_0
|
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Info: avalon_st_adapter_027: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_028: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_029: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_030: Inserting error_adapter: error_adapter_0
|
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Info: avalon_st_adapter_031: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_032: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_033: Inserting error_adapter: error_adapter_0
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Info: mm_interconnect_0: "ECE385" instantiated altera_mm_interconnect "mm_interconnect_0"
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Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
|
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Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
|
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Info: mm_interconnect_1: "ECE385" instantiated altera_mm_interconnect "mm_interconnect_1"
|
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Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
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Info: mm_interconnect_2: "ECE385" instantiated altera_mm_interconnect "mm_interconnect_2"
|
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Info: irq_mapper: "ECE385" instantiated altera_irq_mapper "irq_mapper"
|
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Info: irq_mapper_001: "ECE385" instantiated altera_irq_mapper "irq_mapper_001"
|
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Info: rst_controller: "ECE385" instantiated altera_reset_controller "rst_controller"
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Info: data_format_adapter_0: "eth0_tx_dma_buffer" instantiated data_format_adapter "data_format_adapter_0"
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Info: cpu: Starting RTL generation for module 'ECE385_nios2_cpu_cpu'
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|
Info: cpu: Generation command is [exec D:/Softwares/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I D:/Softwares/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=ECE385_nios2_cpu_cpu --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0042_cpu_gen/ --quartus_bindir=D:/Softwares/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0042_cpu_gen//ECE385_nios2_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]
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Info: cpu: # 2019.06.04 17:24:19 (*) Starting Nios II generation
|
|
Info: cpu: # 2019.06.04 17:24:19 (*) Checking for plaintext license.
|
|
Info: cpu: # 2019.06.04 17:24:20 (*) Couldn't query license setup in Quartus directory D:/Softwares/intelFPGA_lite/18.1/quartus/bin64/
|
|
Info: cpu: # 2019.06.04 17:24:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
|
|
Info: cpu: # 2019.06.04 17:24:20 (*) LM_LICENSE_FILE environment variable is empty
|
|
Info: cpu: # 2019.06.04 17:24:20 (*) Plaintext license not found.
|
|
Info: cpu: # 2019.06.04 17:24:20 (*) No license required to generate encrypted Nios II/e.
|
|
Info: cpu: # 2019.06.04 17:24:20 (*) Elaborating CPU configuration settings
|
|
Info: cpu: # 2019.06.04 17:24:20 (*) Creating all objects for CPU
|
|
Info: cpu: # 2019.06.04 17:24:21 (*) Generating RTL from CPU objects
|
|
Info: cpu: # 2019.06.04 17:24:21 (*) Creating plain-text RTL
|
|
Info: cpu: # 2019.06.04 17:24:22 (*) Done Nios II generation
|
|
Info: cpu: Done RTL generation for module 'ECE385_nios2_cpu_cpu'
|
|
Info: cpu: "nios2_cpu" instantiated altera_nios2_gen2_unit "cpu"
|
|
Info: cpu: Starting RTL generation for module 'ECE385_usb_nios2_cpu_cpu'
|
|
Info: cpu: Generation command is [exec D:/Softwares/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I D:/Softwares/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I D:/softwares/intelfpga_lite/18.1/quartus/sopc_builder/bin -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- D:/softwares/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=ECE385_usb_nios2_cpu_cpu --dir=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0043_cpu_gen/ --quartus_bindir=D:/Softwares/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/xuyh0/AppData/Local/Temp/alt8051_7451298049073768692.dir/0043_cpu_gen//ECE385_usb_nios2_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]
|
|
Info: cpu: # 2019.06.04 17:24:22 (*) Starting Nios II generation
|
|
Info: cpu: # 2019.06.04 17:24:22 (*) Checking for plaintext license.
|
|
Info: cpu: # 2019.06.04 17:24:23 (*) Couldn't query license setup in Quartus directory D:/Softwares/intelFPGA_lite/18.1/quartus/bin64/
|
|
Info: cpu: # 2019.06.04 17:24:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
|
|
Info: cpu: # 2019.06.04 17:24:23 (*) LM_LICENSE_FILE environment variable is empty
|
|
Info: cpu: # 2019.06.04 17:24:23 (*) Plaintext license not found.
|
|
Info: cpu: # 2019.06.04 17:24:23 (*) No license required to generate encrypted Nios II/e.
|
|
Info: cpu: # 2019.06.04 17:24:23 (*) Elaborating CPU configuration settings
|
|
Info: cpu: # 2019.06.04 17:24:23 (*) Creating all objects for CPU
|
|
Info: cpu: # 2019.06.04 17:24:24 (*) Generating RTL from CPU objects
|
|
Info: cpu: # 2019.06.04 17:24:24 (*) Creating plain-text RTL
|
|
Info: cpu: # 2019.06.04 17:24:25 (*) Done Nios II generation
|
|
Info: cpu: Done RTL generation for module 'ECE385_usb_nios2_cpu_cpu'
|
|
Info: cpu: "usb_nios2_cpu" instantiated altera_nios2_gen2_unit "cpu"
|
|
Info: nios2_cpu_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_cpu_data_master_translator"
|
|
Info: nios2_jtag_uart_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "nios2_jtag_uart_avalon_jtag_slave_translator"
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Info: nios2_cpu_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_cpu_data_master_agent"
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Info: nios2_jtag_uart_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "nios2_jtag_uart_avalon_jtag_slave_agent"
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Info: nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "nios2_jtag_uart_avalon_jtag_slave_agent_rsp_fifo"
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Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
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Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
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Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
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Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003"
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Info: router_004: "mm_interconnect_0" instantiated altera_merlin_router "router_004"
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Info: router_007: "mm_interconnect_0" instantiated altera_merlin_router "router_007"
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Info: router_009: "mm_interconnect_0" instantiated altera_merlin_router "router_009"
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Info: router_014: "mm_interconnect_0" instantiated altera_merlin_router "router_014"
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Info: router_015: "mm_interconnect_0" instantiated altera_merlin_router "router_015"
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Info: router_021: "mm_interconnect_0" instantiated altera_merlin_router "router_021"
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Info: nios2_dma_m_read_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_dma_m_read_limiter"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_avalon_sc_fifo.v
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Info: sram_multiplexer_avl_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "sram_multiplexer_avl_burst_adapter"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
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Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
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Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
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Info: cmd_demux_002: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_002"
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Info: cmd_demux_003: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_003"
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Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
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Info: cmd_mux_010: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_010"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: cmd_mux_011: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_011"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: cmd_mux_017: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_017"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
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Info: rsp_demux_010: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_010"
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Info: rsp_demux_011: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_011"
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Info: rsp_demux_017: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_017"
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Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_mux_002: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_002"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_mux_003: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_003"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: sram_multiplexer_avl_rsp_width_adapter: "mm_interconnect_0" instantiated altera_merlin_width_adapter "sram_multiplexer_avl_rsp_width_adapter"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_address_alignment.sv
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
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Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
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Info: avalon_st_adapter_003: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter_003"
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Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
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Info: router_001: "mm_interconnect_1" instantiated altera_merlin_router "router_001"
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Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
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Info: router_006: "mm_interconnect_1" instantiated altera_merlin_router "router_006"
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Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
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Info: cmd_demux_001: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_001"
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Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: cmd_mux_004: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_004"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
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Info: rsp_demux_004: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_004"
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Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_mux_001: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux_001"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: router: "mm_interconnect_2" instantiated altera_merlin_router "router"
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Info: router_012: "mm_interconnect_2" instantiated altera_merlin_router "router_012"
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Info: router_014: "mm_interconnect_2" instantiated altera_merlin_router "router_014"
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Info: cmd_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "cmd_demux"
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Info: cmd_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "cmd_mux"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "rsp_demux"
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Info: rsp_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux"
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Info: Reusing file C:/Users/xuyh0/Desktop/zjui-ece385/final/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
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Info: error_adapter_0: "avalon_st_adapter_003" instantiated error_adapter "error_adapter_0"
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Info: ECE385: Done "ECE385" with 105 modules, 150 files
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Info: qsys-generate succeeded.
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Info: Finished: Create HDL design files for synthesis
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