106 lines
6.1 KiB
Groff
Executable File
106 lines
6.1 KiB
Groff
Executable File
Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate C:\Users\xuyh0\Desktop\zjui-ece385\final\ECE385.qsys --synthesis=VERILOG --output-directory=C:\Users\xuyh0\Desktop\zjui-ece385\final\qsys\synthesis --family="Cyclone IV E" --part=EP4CE115F29C7
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Progress: Loading final/ECE385.qsys
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Progress: Reading input file
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Progress: Adding audio_mem [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module audio_mem
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Progress: Adding audio_position [altera_avalon_pio 18.1]
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Progress: Parameterizing module audio_position
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Progress: Adding audio_position_end [altera_avalon_pio 18.1]
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Progress: Parameterizing module audio_position_end
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Progress: Adding clk_0 [clock_source 18.1]
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Progress: Parameterizing module clk_0
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Progress: Adding eth0_mdio [lantian_mdio 1.0]
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Progress: Parameterizing module eth0_mdio
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Progress: Adding eth1_mdio [lantian_mdio 1.0]
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Progress: Parameterizing module eth1_mdio
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Progress: Adding eth_pll [altpll 18.1]
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Progress: Parameterizing module eth_pll
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Progress: Adding io_hex [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_hex
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Progress: Adding io_hwrng [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_hwrng
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Progress: Adding io_keys [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_keys
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Progress: Adding io_led_green [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_led_green
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Progress: Adding io_led_red [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_led_red
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Progress: Adding io_switches [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_switches
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Progress: Adding io_vga_sync [altera_avalon_pio 18.1]
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Progress: Parameterizing module io_vga_sync
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Progress: Adding nios2_cpu [altera_nios2_gen2 18.1]
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Progress: Parameterizing module nios2_cpu
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Progress: Adding nios2_jtag_uart [altera_avalon_jtag_uart 18.1]
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Progress: Parameterizing module nios2_jtag_uart
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Progress: Adding nios2_onchip_mem [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module nios2_onchip_mem
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Progress: Adding nios2_pll [altpll 18.1]
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Progress: Parameterizing module nios2_pll
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Progress: Adding nios2_sysid [altera_avalon_sysid_qsys 18.1]
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Progress: Parameterizing module nios2_sysid
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Progress: Adding nios2_timer [altera_avalon_timer 18.1]
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Progress: Parameterizing module nios2_timer
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Progress: Adding sdram [altera_avalon_new_sdram_controller 18.1]
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Progress: Parameterizing module sdram
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Progress: Adding sram_multiplexer [sram_multiplexer 1.0]
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Progress: Parameterizing module sram_multiplexer
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Progress: Adding usb_clk [clock_source 18.1]
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Progress: Parameterizing module usb_clk
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Progress: Adding usb_hpi_address [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_address
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Progress: Adding usb_hpi_cs [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_cs
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Progress: Adding usb_hpi_data [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_data
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Progress: Adding usb_hpi_r [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_r
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Progress: Adding usb_hpi_reset [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_reset
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Progress: Adding usb_hpi_w [altera_avalon_pio 18.1]
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Progress: Parameterizing module usb_hpi_w
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Progress: Adding usb_keycode [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module usb_keycode
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Progress: Adding usb_nios2_cpu [altera_nios2_gen2 18.1]
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Progress: Parameterizing module usb_nios2_cpu
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Progress: Adding usb_nios2_onchip_mem [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module usb_nios2_onchip_mem
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Progress: Adding usb_nios2_sysid [altera_avalon_sysid_qsys 18.1]
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Progress: Parameterizing module usb_nios2_sysid
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Progress: Adding vga_sprite_0 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_0
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Progress: Adding vga_sprite_1 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_1
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Progress: Adding vga_sprite_2 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_2
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Progress: Adding vga_sprite_3 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_3
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Progress: Adding vga_sprite_4 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_4
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Progress: Adding vga_sprite_5 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_5
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Progress: Adding vga_sprite_6 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_6
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Progress: Adding vga_sprite_7 [altera_avalon_onchip_memory2 18.1]
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Progress: Parameterizing module vga_sprite_7
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Progress: Adding vga_sprite_params [avalon_mm_passthrough 1.0]
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Progress: Parameterizing module vga_sprite_params
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: ECE385.audio_position: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.io_hwrng: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.io_keys: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.io_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.io_vga_sync: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.nios2_jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
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Info: ECE385.nios2_sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
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Info: ECE385.nios2_sysid: Time stamp will be automatically updated when this component is generated.
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Info: ECE385.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
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Info: ECE385.usb_hpi_data: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ECE385.usb_nios2_sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
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Info: ECE385.usb_nios2_sysid: Time stamp will be automatically updated when this component is generated.
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Info: ECE385: Generating ECE385 "ECE385" for QUARTUS_SYNTH
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