690 lines
20 KiB
Systemverilog
690 lines
20 KiB
Systemverilog
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//=======================================================
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// This code is generated by Terasic System Builder
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//=======================================================
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module project_top(
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//////////// Sma //////////
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// input logic SMA_CLKIN,
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// output logic SMA_CLKOUT,
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//////////// LED //////////
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output logic [8:0] LEDG,
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output logic [17:0] LEDR,
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//////////// KEY //////////
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input logic [3:0] KEY,
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//////////// EX_IO //////////
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// inout logic [6:0] EX_IO,
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//////////// SW //////////
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input logic [17:0] SW,
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//////////// SEG7 //////////
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output logic [6:0] HEX0,
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output logic [6:0] HEX1,
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output logic [6:0] HEX2,
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output logic [6:0] HEX3,
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output logic [6:0] HEX4,
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output logic [6:0] HEX5,
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output logic [6:0] HEX6,
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output logic [6:0] HEX7,
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//////////// LCD //////////
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// output logic LCD_BLON,
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// inout logic [7:0] LCD_DATA,
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// output logic LCD_EN,
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// output logic LCD_ON,
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// output logic LCD_RS,
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// output logic LCD_RW,
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//////////// RS232 //////////
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// input logic UART_CTS,
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// output logic UART_RTS,
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// input logic UART_RXD,
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// output logic UART_TXD,
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//////////// PS2 for Keyboard and Mouse //////////
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// inout logic PS2_CLK,
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// inout logic PS2_CLK2,
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// inout logic PS2_DAT,
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// inout logic PS2_DAT2,
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//////////// SDCARD //////////
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// output logic SD_CLK,
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// inout logic SD_CMD,
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// inout logic [3:0] SD_DAT,
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// input logic SD_WP_N,
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//////////// VGA //////////
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output logic [7:0] VGA_B,
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output logic VGA_BLANK_N,
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output logic VGA_CLK,
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output logic [7:0] VGA_G,
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output logic VGA_HS,
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output logic [7:0] VGA_R,
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output logic VGA_SYNC_N,
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output logic VGA_VS,
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//////////// Audio //////////
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input logic AUD_ADCDAT,
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inout logic AUD_ADCLRCK,
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inout logic AUD_BCLK,
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output logic AUD_DACDAT,
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inout logic AUD_DACLRCK,
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output logic AUD_XCK,
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//////////// I2C for EEPROM //////////
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// output logic EEP_I2C_SCLK,
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// inout logic EEP_I2C_SDAT,
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//////////// I2C for Audio Tv-Decoder HSMC //////////
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output logic I2C_SCLK,
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inout logic I2C_SDAT,
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//////////// Ethernet 0 //////////
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output logic ENET0_GTX_CLK,
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input logic ENET0_INT_N,
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input logic ENET0_LINK100,
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output logic ENET0_MDC,
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inout logic ENET0_MDIO,
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output logic ENET0_RST_N,
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input logic ENET0_RX_CLK,
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input logic ENET0_RX_COL,
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input logic ENET0_RX_CRS,
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input logic [3:0] ENET0_RX_DATA,
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input logic ENET0_RX_DV,
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input logic ENET0_RX_ER,
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input logic ENET0_TX_CLK,
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output logic [3:0] ENET0_TX_DATA,
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output logic ENET0_TX_EN,
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output logic ENET0_TX_ER,
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input logic ENETCLK_25,
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//////////// Ethernet 1 //////////
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output logic ENET1_GTX_CLK,
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input logic ENET1_INT_N,
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input logic ENET1_LINK100,
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output logic ENET1_MDC,
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inout logic ENET1_MDIO,
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output logic ENET1_RST_N,
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input logic ENET1_RX_CLK,
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input logic ENET1_RX_COL,
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input logic ENET1_RX_CRS,
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input logic [3:0] ENET1_RX_DATA,
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input logic ENET1_RX_DV,
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input logic ENET1_RX_ER,
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input logic ENET1_TX_CLK,
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output logic [3:0] ENET1_TX_DATA,
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output logic ENET1_TX_EN,
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output logic ENET1_TX_ER,
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//////////// TV Decoder //////////
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// input logic TD_CLK27,
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// input logic [7:0] TD_DATA,
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// input logic TD_HS,
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// output logic TD_RESET_N,
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// input logic TD_VS,
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//////////// USB 2.0 OTG (Cypress CY7C67200) //////////
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output logic [1:0] OTG_ADDR,
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output logic OTG_CS_N,
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inout [15:0] OTG_DATA,
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input logic OTG_INT,
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output logic OTG_RD_N,
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output logic OTG_RST_N,
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output logic OTG_WE_N,
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//////////// IR Receiver //////////
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// input logic IRDA_RXD,
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//////////// SDRAM //////////
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output logic [12:0] DRAM_ADDR,
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output logic [1:0] DRAM_BA,
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output logic DRAM_CAS_N,
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output logic DRAM_CKE,
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output logic DRAM_CLK,
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output logic DRAM_CS_N,
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inout logic [31:0] DRAM_DQ,
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output logic [3:0] DRAM_DQM,
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output logic DRAM_RAS_N,
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output logic DRAM_WE_N,
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//////////// SRAM //////////
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output logic [19:0] SRAM_ADDR,
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output logic SRAM_CE_N,
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inout logic [15:0] SRAM_DQ,
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output logic SRAM_LB_N,
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output logic SRAM_OE_N,
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output logic SRAM_UB_N,
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output logic SRAM_WE_N,
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//////////// Flash //////////
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// output logic [22:0] FL_ADDR,
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// output logic FL_CE_N,
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// inout logic [7:0] FL_DQ,
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// output logic FL_OE_N,
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// output logic FL_RST_N,
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// input logic FL_RY,
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// output logic FL_WE_N,
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// output logic FL_WP_N,
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//////////// GPIO, GPIO connect to GPIO Default //////////
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// inout logic [35:0] GPIO,
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//////////// HSMC, HSMC connect to HSMC Default //////////
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// input logic HSMC_CLKIN_N1,
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// input logic HSMC_CLKIN_N2,
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// input logic HSMC_CLKIN_P1,
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// input logic HSMC_CLKIN_P2,
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// input logic HSMC_CLKIN0,
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// output logic HSMC_CLKOUT_N1,
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// output logic HSMC_CLKOUT_N2,
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// output logic HSMC_CLKOUT_P1,
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// output logic HSMC_CLKOUT_P2,
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// output logic HSMC_CLKOUT0,
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// inout logic [3:0] HSMC_D,
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// inout logic [16:0] HSMC_RX_D_N,
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// inout logic [16:0] HSMC_RX_D_P,
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// inout logic [16:0] HSMC_TX_D_N,
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// inout logic [16:0] HSMC_TX_D_P,
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//////////// CLOCK //////////
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input logic CLOCK_50,
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input logic CLOCK2_50,
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input logic CLOCK3_50
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);
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// Reset signal
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logic RESET, RESET_USB;
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always_ff @ (posedge CLOCK_50) begin
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RESET <= KEY[0];
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RESET_USB <= KEY[1];
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end
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// USB OTG
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logic [1:0] hpi_addr;
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logic [15:0] hpi_data_in, hpi_data_out;
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logic hpi_r, hpi_w, hpi_cs, hpi_reset;
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hpi_io_intf hpi_io_inst(
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.Clk(CLOCK_50), .Reset(~RESET_USB),
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// signals connected to NIOS II
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.from_sw_address(hpi_addr),
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.from_sw_data_in(hpi_data_in),
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.from_sw_data_out(hpi_data_out),
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.from_sw_r(hpi_r),
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.from_sw_w(hpi_w),
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.from_sw_cs(hpi_cs),
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.from_sw_reset(hpi_reset),
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// signals connected to EZ-OTG chip
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.OTG_DATA(OTG_DATA),
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.OTG_ADDR(OTG_ADDR),
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.OTG_RD_N(OTG_RD_N),
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.OTG_WR_N(OTG_WE_N),
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.OTG_CS_N(OTG_CS_N),
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.OTG_RST_N(OTG_RST_N)
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);
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//logic [15:0] OTG_DATA_OUT;
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//assign OTG_DATA = OTG_WE_N ? {16{1'bZ}} : OTG_DATA_OUT;
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// Hex display
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logic[31:0] HEX_EXPORT;
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hexdriver hexdrv0 (
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.In(HEX_EXPORT[3:0]),
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.Out(HEX0)
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);
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hexdriver hexdrv1 (
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.In(HEX_EXPORT[7:4]),
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.Out(HEX1)
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);
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hexdriver hexdrv2 (
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.In(HEX_EXPORT[11:8]),
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.Out(HEX2)
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);
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hexdriver hexdrv3 (
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.In(HEX_EXPORT[15:12]),
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.Out(HEX3)
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);
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hexdriver hexdrv4 (
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.In(HEX_EXPORT[19:16]),
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.Out(HEX4)
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);
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hexdriver hexdrv5 (
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.In(HEX_EXPORT[23:20]),
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.Out(HEX5)
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);
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hexdriver hexdrv6 (
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.In(HEX_EXPORT[27:24]),
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.Out(HEX6)
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);
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hexdriver hexdrv7 (
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.In(HEX_EXPORT[31:28]),
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.Out(HEX7)
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);
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logic ETH_CLK_125;
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// Ethernet 0 external logic
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logic ETH0_MDIO_IN, ETH0_MDIO_OEN, ETH0_MDIO_OUT;
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assign ETH0_MDIO_IN = ENET0_MDIO;
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assign ENET0_MDIO = ETH0_MDIO_OEN ? 1'bZ : ETH0_MDIO_OUT;
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assign ENET0_RST_N = RESET;
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assign ENET0_TX_ER = 1'b0;
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logic ETH0_CLK_TX, ETH0_CLK_RX;
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logic [31:0] ETH0_TX_FIFO_DATA;
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logic [1:0] ETH0_TX_FIFO_EMPTY;
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logic ETH0_TX_FIFO_VALID, ETH0_TX_FIFO_READY, ETH0_TX_FIFO_SOP, ETH0_TX_FIFO_EOP;
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logic [7:0] ETH0_TX_DATA;
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logic ETH0_TX_VALID, ETH0_TX_READY, ETH0_TX_SOP, ETH0_TX_EOP;
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logic [7:0] ETH0_RX_DATA;
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logic ETH0_RX_VALID, ETH0_RX_EOP, ETH0_RX_SOP;
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logic [2:0] ETH0_RX_ERROR;
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eth_mac_1g_rgmii #(
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.ENABLE_PADDING(1),
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.MIN_FRAME_LENGTH(64)
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) ETH0 (
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.gtx_clk(ETH_CLK_125),
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.gtx_rst(~RESET),
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.tx_clk(ETH0_CLK_TX),
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.tx_rst(~RESET),
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.tx_axis_tdata(ETH0_TX_DATA),
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.tx_axis_tvalid(ETH0_TX_VALID),
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.tx_axis_tready(ETH0_TX_READY),
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.tx_axis_tlast(ETH0_TX_EOP),
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.rx_clk(ETH0_CLK_RX),
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.rx_rst(~RESET),
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.rx_axis_tdata(ETH0_RX_DATA),
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.rx_axis_tvalid(ETH0_RX_VALID),
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.rx_axis_tlast(ETH0_RX_EOP),
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.rx_axis_tuser(ETH0_RX_ERROR[0]),
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.rx_start_packet(ETH0_RX_SOP),
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.rx_error_bad_frame(ETH0_RX_ERROR[1]),
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.rx_error_bad_fcs(ETH0_RX_ERROR[2]),
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.rgmii_rx_clk(ENET0_RX_CLK),
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.rgmii_rxd(ENET0_RX_DATA),
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.rgmii_rx_ctl(ENET0_RX_DV),
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.rgmii_tx_clk(ENET0_GTX_CLK),
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.rgmii_txd(ENET0_TX_DATA),
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.rgmii_tx_ctl(ENET0_TX_EN),
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.ifg_delay(8'd12)
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);
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// Ethernet 1 external logic
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logic ETH1_MDIO_IN, ETH1_MDIO_OEN, ETH1_MDIO_OUT;
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assign ETH1_MDIO_IN = ENET1_MDIO;
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assign ENET1_MDIO = ETH1_MDIO_OEN ? 1'bZ : ETH1_MDIO_OUT;
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assign ENET1_RST_N = RESET;
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assign ENET1_TX_ER = 1'b0;
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logic ETH1_CLK_TX, ETH1_CLK_RX;
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logic [31:0] ETH1_TX_FIFO_DATA;
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logic [1:0] ETH1_TX_FIFO_EMPTY;
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logic ETH1_TX_FIFO_VALID, ETH1_TX_FIFO_READY, ETH1_TX_FIFO_SOP, ETH1_TX_FIFO_EOP;
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logic [7:0] ETH1_TX_DATA;
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logic ETH1_TX_VALID, ETH1_TX_READY, ETH1_TX_SOP, ETH1_TX_EOP;
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logic [7:0] ETH1_RX_DATA;
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logic ETH1_RX_VALID, ETH1_RX_EOP, ETH1_RX_SOP;
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logic [2:0] ETH1_RX_ERROR;
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eth_mac_1g_rgmii #(
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.ENABLE_PADDING(1),
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.MIN_FRAME_LENGTH(64)
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) ETH1 (
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.gtx_clk(ETH_CLK_125),
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.gtx_rst(~RESET),
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.tx_clk(ETH1_CLK_TX),
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.tx_rst(~RESET),
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.tx_axis_tdata(ETH1_TX_DATA),
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.tx_axis_tvalid(ETH1_TX_VALID),
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.tx_axis_tready(ETH1_TX_READY),
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.tx_axis_tlast(ETH1_TX_EOP),
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.rx_clk(ETH1_CLK_RX),
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.rx_rst(~RESET),
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.rx_axis_tdata(ETH1_RX_DATA),
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.rx_axis_tvalid(ETH1_RX_VALID),
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.rx_axis_tlast(ETH1_RX_EOP),
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.rx_axis_tuser(ETH1_RX_ERROR[0]),
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.rx_start_packet(ETH1_RX_SOP),
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.rx_error_bad_frame(ETH1_RX_ERROR[1]),
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.rx_error_bad_fcs(ETH1_RX_ERROR[2]),
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.rgmii_rx_clk(ENET1_RX_CLK),
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.rgmii_rxd(ENET1_RX_DATA),
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.rgmii_rx_ctl(ENET1_RX_DV),
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.rgmii_tx_clk(ENET1_GTX_CLK),
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.rgmii_txd(ENET1_TX_DATA),
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.rgmii_tx_ctl(ENET1_TX_EN),
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.ifg_delay(8'd12)
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);
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// VGA Controller
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logic[9:0] VGA_DrawX, VGA_DrawY;
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logic [15:0] VGA_VAL;
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logic [7:0][11:0] VGA_SPRITE_ADDR;
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logic [7:0][15:0] VGA_SPRITE_DATA;
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logic [63:0] VGA_SPRITE_ISOBJ;
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logic [63:0][15:0] VGA_SPRITE_PIXEL;
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logic [31:0] VGA_BG_OFFSET;
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VGA_controller VGA(
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.Clk(CLOCK_50), .Reset(~RESET),
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.VGA_HS(VGA_HS), .VGA_VS(VGA_VS), .VGA_CLK, .VGA_BLANK_N(VGA_BLANK_N), .VGA_SYNC_N(VGA_SYNC_N),
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.DrawX(VGA_DrawX), .DrawY(VGA_DrawY)
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);
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VGA_layer VGA_layer_manager(
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.VGA_VAL,
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.VGA_R(VGA_R), .VGA_G(VGA_G), .VGA_B(VGA_B),
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.VGA_DrawY,
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.VGA_SPRITE_ISOBJ, .VGA_SPRITE_PIXEL
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);
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logic VGA_entities_manager_read, VGA_entities_manager_write;
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logic [7:0] VGA_entities_manager_addr;
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logic [31:0] VGA_entities_manager_readdata, VGA_entities_manager_writedata;
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logic [255:0][31:0] VGA_entities_export;
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VGA_entities VGA_entities_manager (
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.CLK(CLOCK_50), .RESET(~RESET),
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.AVL_READ(VGA_entities_manager_read),
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.AVL_WRITE(VGA_entities_manager_write),
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.AVL_ADDR(VGA_entities_manager_addr),
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.AVL_WRITEDATA(VGA_entities_manager_writedata),
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.AVL_READDATA(VGA_entities_manager_readdata),
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.EXPORT_DATA(VGA_entities_export)
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);
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genvar i;
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generate
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for(i = 0; i < 8; i++) begin: generate_vga_sprites
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VGA_sprite VGA_sprite_instance (
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.Clk(CLOCK_50), .Reset(~RESET),
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.VGA_DrawX, .VGA_DrawY,
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.SpriteX(VGA_entities_export[4*i][19:4]),
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.SpriteY(VGA_entities_export[4*i+1][19:4]),
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.SpriteWidth(VGA_entities_export[4*i+2][15:0]),
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.SpriteHeight(VGA_entities_export[4*i+3][15:0]),
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.AVL_Addr(VGA_SPRITE_ADDR[i]),
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.AVL_ReadData(VGA_SPRITE_DATA[i]),
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.VGA_isObject(VGA_SPRITE_ISOBJ[i]),
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.VGA_Pixel(VGA_SPRITE_PIXEL[i])
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);
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end
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for(i = 8; i < 64; i++) begin: generate_vga_bullets
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bullet bullet_instance (
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.BulletX(VGA_entities_export[4*i][19:4]),
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.BulletY(VGA_entities_export[4*i+1][19:4]),
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.BulletRadius(VGA_entities_export[4*i+2][15:0]),
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.BulletColor(VGA_entities_export[4*i+3][15:0]),
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.DrawX(VGA_DrawX), .DrawY(VGA_DrawY),
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.VGA_isObject(VGA_SPRITE_ISOBJ[i]),
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.VGA_Pixel(VGA_SPRITE_PIXEL[i])
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);
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end
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endgenerate
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// Wolfson 8731 Music chip
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logic [15:0] WM8731_LDATA, WM8731_RDATA;
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logic WM8731_DATA_OVER, WM8731_DATA_OVER_PREV;
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logic WM8731_READY;
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wm8731 wm8731_inst(
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.clk(CLOCK_50), .Reset(~RESET), .INIT(1'b1),
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.AUD_ADCDAT(AUD_ADCDAT), .AUD_ADCLRCK(AUD_ADCLRCK), .AUD_BCLK(AUD_BCLK),
|
|
.AUD_DACDAT(AUD_DACDAT), .AUD_DACLRCK(AUD_DACLRCK), .AUD_MCLK(AUD_XCK),
|
|
.I2C_SDAT(I2C_SDAT), .I2C_SCLK(I2C_SCLK),
|
|
|
|
.LDATA(WM8731_LDATA), .RDATA(WM8731_RDATA),
|
|
.data_over(WM8731_DATA_OVER),
|
|
);
|
|
|
|
// VGA Scrolling & Statusbar
|
|
logic [9:0] VGA_RealDrawY;
|
|
always_comb begin
|
|
if(VGA_DrawY >= 464) begin
|
|
VGA_RealDrawY = VGA_DrawY;
|
|
end else if(VGA_DrawY + VGA_BG_OFFSET >= 464) begin
|
|
VGA_RealDrawY = VGA_DrawY + VGA_BG_OFFSET - 464;
|
|
end else begin
|
|
VGA_RealDrawY = VGA_DrawY + VGA_BG_OFFSET;
|
|
end
|
|
end
|
|
|
|
// Main system
|
|
ECE385 ECE385_sys(
|
|
.clk_clk(CLOCK_50),
|
|
.reset_reset_n(RESET),
|
|
|
|
.usb_clk_clk(CLOCK_50),
|
|
.usb_reset_reset_n(RESET_USB),
|
|
|
|
.io_keys_export(KEY),
|
|
.io_led_green_export(LEDG),
|
|
.io_led_red_export(LEDR),
|
|
.io_switches_export(SW),
|
|
.io_hex_export(HEX_EXPORT),
|
|
.io_vga_sync_export(VGA_VS),
|
|
|
|
.sdram_addr(DRAM_ADDR),
|
|
.sdram_ba(DRAM_BA),
|
|
.sdram_cas_n(DRAM_CAS_N),
|
|
.sdram_cke(DRAM_CKE),
|
|
.sdram_cs_n(DRAM_CS_N),
|
|
.sdram_dq(DRAM_DQ),
|
|
.sdram_dqm(DRAM_DQM),
|
|
.sdram_ras_n(DRAM_RAS_N),
|
|
.sdram_we_n(DRAM_WE_N),
|
|
.nios2_pll_sdram_clk(DRAM_CLK),
|
|
|
|
.sram_sram_addr(SRAM_ADDR),
|
|
.sram_sram_ce_n(SRAM_CE_N),
|
|
.sram_sram_dq(SRAM_DQ),
|
|
.sram_sram_lb_n(SRAM_LB_N),
|
|
.sram_sram_oe_n(SRAM_OE_N),
|
|
.sram_sram_ub_n(SRAM_UB_N),
|
|
.sram_sram_we_n(SRAM_WE_N),
|
|
|
|
.vga_vga_val(VGA_VAL),
|
|
.vga_vga_drawx(VGA_DrawX),
|
|
.vga_vga_drawy(VGA_RealDrawY),
|
|
.vga_background_offset_export(VGA_BG_OFFSET),
|
|
.nios2_pll_vga_clk(VGA_CLK),
|
|
|
|
.vga_sprite_0_clk2_clk(CLOCK_50),
|
|
.vga_sprite_0_reset2_reset(~RESET),
|
|
.vga_sprite_0_s2_address(VGA_SPRITE_ADDR[0]),
|
|
.vga_sprite_0_s2_chipselect(1'b1),
|
|
.vga_sprite_0_s2_clken(1'b1),
|
|
.vga_sprite_0_s2_write(1'b0),
|
|
.vga_sprite_0_s2_readdata(VGA_SPRITE_DATA[0]),
|
|
.vga_sprite_0_s2_writedata(16'b0),
|
|
.vga_sprite_0_s2_byteenable(2'b11),
|
|
|
|
.vga_sprite_1_clk2_clk(CLOCK_50),
|
|
.vga_sprite_1_reset2_reset(~RESET),
|
|
.vga_sprite_1_s2_address(VGA_SPRITE_ADDR[1]),
|
|
.vga_sprite_1_s2_chipselect(1'b1),
|
|
.vga_sprite_1_s2_clken(1'b1),
|
|
.vga_sprite_1_s2_write(1'b0),
|
|
.vga_sprite_1_s2_readdata(VGA_SPRITE_DATA[1]),
|
|
.vga_sprite_1_s2_writedata(16'b0),
|
|
.vga_sprite_1_s2_byteenable(2'b11),
|
|
|
|
.vga_sprite_2_clk2_clk(CLOCK_50),
|
|
.vga_sprite_2_reset2_reset(~RESET),
|
|
.vga_sprite_2_s2_address(VGA_SPRITE_ADDR[2]),
|
|
.vga_sprite_2_s2_chipselect(1'b1),
|
|
.vga_sprite_2_s2_clken(1'b1),
|
|
.vga_sprite_2_s2_write(1'b0),
|
|
.vga_sprite_2_s2_readdata(VGA_SPRITE_DATA[2]),
|
|
.vga_sprite_2_s2_writedata(16'b0),
|
|
.vga_sprite_2_s2_byteenable(2'b11),
|
|
|
|
.vga_sprite_3_clk2_clk(CLOCK_50),
|
|
.vga_sprite_3_reset2_reset(~RESET),
|
|
.vga_sprite_3_s2_address(VGA_SPRITE_ADDR[3]),
|
|
.vga_sprite_3_s2_chipselect(1'b1),
|
|
.vga_sprite_3_s2_clken(1'b1),
|
|
.vga_sprite_3_s2_write(1'b0),
|
|
.vga_sprite_3_s2_readdata(VGA_SPRITE_DATA[3]),
|
|
.vga_sprite_3_s2_writedata(16'b0),
|
|
.vga_sprite_3_s2_byteenable(2'b11),
|
|
|
|
.vga_sprite_4_clk2_clk(CLOCK_50),
|
|
.vga_sprite_4_reset2_reset(~RESET),
|
|
.vga_sprite_4_s2_address(VGA_SPRITE_ADDR[4]),
|
|
.vga_sprite_4_s2_chipselect(1'b1),
|
|
.vga_sprite_4_s2_clken(1'b1),
|
|
.vga_sprite_4_s2_write(1'b0),
|
|
.vga_sprite_4_s2_readdata(VGA_SPRITE_DATA[4]),
|
|
.vga_sprite_4_s2_writedata(16'b0),
|
|
.vga_sprite_4_s2_byteenable(2'b11),
|
|
|
|
.vga_sprite_5_clk2_clk(CLOCK_50),
|
|
.vga_sprite_5_reset2_reset(~RESET),
|
|
.vga_sprite_5_s2_address(VGA_SPRITE_ADDR[5]),
|
|
.vga_sprite_5_s2_chipselect(1'b1),
|
|
.vga_sprite_5_s2_clken(1'b1),
|
|
.vga_sprite_5_s2_write(1'b0),
|
|
.vga_sprite_5_s2_readdata(VGA_SPRITE_DATA[5]),
|
|
.vga_sprite_5_s2_writedata(16'b0),
|
|
.vga_sprite_5_s2_byteenable(2'b11),
|
|
|
|
.vga_sprite_6_clk2_clk(CLOCK_50),
|
|
.vga_sprite_6_reset2_reset(~RESET),
|
|
.vga_sprite_6_s2_address(VGA_SPRITE_ADDR[6]),
|
|
.vga_sprite_6_s2_chipselect(1'b1),
|
|
.vga_sprite_6_s2_clken(1'b1),
|
|
.vga_sprite_6_s2_write(1'b0),
|
|
.vga_sprite_6_s2_readdata(VGA_SPRITE_DATA[6]),
|
|
.vga_sprite_6_s2_writedata(16'b0),
|
|
.vga_sprite_6_s2_byteenable(2'b11),
|
|
|
|
.vga_sprite_7_clk2_clk(CLOCK_50),
|
|
.vga_sprite_7_reset2_reset(~RESET),
|
|
.vga_sprite_7_s2_address(VGA_SPRITE_ADDR[7]),
|
|
.vga_sprite_7_s2_chipselect(1'b1),
|
|
.vga_sprite_7_s2_clken(1'b1),
|
|
.vga_sprite_7_s2_write(1'b0),
|
|
.vga_sprite_7_s2_readdata(VGA_SPRITE_DATA[7]),
|
|
.vga_sprite_7_s2_writedata(16'b0),
|
|
.vga_sprite_7_s2_byteenable(2'b11),
|
|
|
|
.vga_sprite_params_pass_address(VGA_entities_manager_addr),
|
|
.vga_sprite_params_pass_write(VGA_entities_manager_write),
|
|
.vga_sprite_params_pass_read(VGA_entities_manager_read),
|
|
.vga_sprite_params_pass_readdata(VGA_entities_manager_readdata),
|
|
.vga_sprite_params_pass_writedata(VGA_entities_manager_writedata),
|
|
|
|
.nios2_pll_ethernet_clk(ETH_CLK_125),
|
|
.eth0_mdio_mdc(ENET0_MDC),
|
|
.eth0_mdio_mdio_in(ETH0_MDIO_IN),
|
|
.eth0_mdio_mdio_out(ETH0_MDIO_OUT),
|
|
.eth0_mdio_mdio_oen(ETH0_MDIO_OEN),
|
|
.eth0_mdio_phy_addr(5'b10000),
|
|
|
|
.eth0_rx_fifo_in_data(ETH0_RX_DATA),
|
|
.eth0_rx_fifo_in_valid(ETH0_RX_VALID),
|
|
.eth0_rx_fifo_in_startofpacket(ETH0_RX_SOP),
|
|
.eth0_rx_fifo_in_endofpacket(ETH0_RX_EOP),
|
|
.eth0_rx_fifo_in_error(ETH0_RX_ERROR),
|
|
.eth0_rx_fifo_in_clk_clk(ETH0_CLK_RX),
|
|
.eth0_rx_fifo_in_clk_reset_reset_n(RESET),
|
|
|
|
.eth0_tx_fifo_out_data(ETH0_TX_FIFO_DATA),
|
|
.eth0_tx_fifo_out_valid(ETH0_TX_FIFO_VALID),
|
|
.eth0_tx_fifo_out_ready(ETH0_TX_FIFO_READY),
|
|
.eth0_tx_fifo_out_startofpacket(ETH0_TX_FIFO_SOP),
|
|
.eth0_tx_fifo_out_endofpacket(ETH0_TX_FIFO_EOP),
|
|
.eth0_tx_fifo_out_empty(ETH0_TX_FIFO_EMPTY),
|
|
.eth0_tx_fifo_out_clk_clk(ETH0_CLK_TX),
|
|
.eth0_tx_fifo_out_clk_reset_reset_n(RESET),
|
|
|
|
.eth0_tx_dma_buffer_in_0_data(ETH0_TX_FIFO_DATA),
|
|
.eth0_tx_dma_buffer_in_0_valid(ETH0_TX_FIFO_VALID),
|
|
.eth0_tx_dma_buffer_in_0_ready(ETH0_TX_FIFO_READY),
|
|
.eth0_tx_dma_buffer_in_0_startofpacket(ETH0_TX_FIFO_SOP),
|
|
.eth0_tx_dma_buffer_in_0_endofpacket(ETH0_TX_FIFO_EOP),
|
|
.eth0_tx_dma_buffer_in_0_empty(ETH0_TX_FIFO_EMPTY),
|
|
.eth0_tx_dma_buffer_in_clk_0_clk(ETH0_CLK_TX),
|
|
.eth0_tx_dma_buffer_in_rst_0_reset(~RESET),
|
|
.eth0_tx_dma_buffer_out_0_data(ETH0_TX_DATA),
|
|
.eth0_tx_dma_buffer_out_0_valid(ETH0_TX_VALID),
|
|
.eth0_tx_dma_buffer_out_0_ready(ETH0_TX_READY),
|
|
.eth0_tx_dma_buffer_out_0_startofpacket(ETH0_TX_SOP),
|
|
.eth0_tx_dma_buffer_out_0_endofpacket(ETH0_TX_EOP),
|
|
|
|
.eth1_mdio_mdc(ENET1_MDC),
|
|
.eth1_mdio_mdio_in(ETH1_MDIO_IN),
|
|
.eth1_mdio_mdio_out(ETH1_MDIO_OUT),
|
|
.eth1_mdio_mdio_oen(ETH1_MDIO_OEN),
|
|
.eth1_mdio_phy_addr(5'b10001),
|
|
|
|
.eth1_rx_fifo_in_data(ETH1_RX_DATA),
|
|
.eth1_rx_fifo_in_valid(ETH1_RX_VALID),
|
|
.eth1_rx_fifo_in_startofpacket(ETH1_RX_SOP),
|
|
.eth1_rx_fifo_in_endofpacket(ETH1_RX_EOP),
|
|
.eth1_rx_fifo_in_error(ETH1_RX_ERROR),
|
|
.eth1_rx_fifo_in_clk_clk(ETH1_CLK_RX),
|
|
.eth1_rx_fifo_in_clk_reset_reset_n(RESET),
|
|
|
|
.eth1_tx_fifo_out_data(ETH1_TX_FIFO_DATA),
|
|
.eth1_tx_fifo_out_valid(ETH1_TX_FIFO_VALID),
|
|
.eth1_tx_fifo_out_ready(ETH1_TX_FIFO_READY),
|
|
.eth1_tx_fifo_out_startofpacket(ETH1_TX_FIFO_SOP),
|
|
.eth1_tx_fifo_out_endofpacket(ETH1_TX_FIFO_EOP),
|
|
.eth1_tx_fifo_out_empty(ETH1_TX_FIFO_EMPTY),
|
|
.eth1_tx_fifo_out_clk_clk(ETH1_CLK_TX),
|
|
.eth1_tx_fifo_out_clk_reset_reset_n(RESET),
|
|
|
|
.eth1_tx_dma_buffer_in_0_data(ETH1_TX_FIFO_DATA),
|
|
.eth1_tx_dma_buffer_in_0_valid(ETH1_TX_FIFO_VALID),
|
|
.eth1_tx_dma_buffer_in_0_ready(ETH1_TX_FIFO_READY),
|
|
.eth1_tx_dma_buffer_in_0_startofpacket(ETH1_TX_FIFO_SOP),
|
|
.eth1_tx_dma_buffer_in_0_endofpacket(ETH1_TX_FIFO_EOP),
|
|
.eth1_tx_dma_buffer_in_0_empty(ETH1_TX_FIFO_EMPTY),
|
|
.eth1_tx_dma_buffer_in_clk_0_clk(ETH1_CLK_TX),
|
|
.eth1_tx_dma_buffer_in_rst_0_reset(~RESET),
|
|
.eth1_tx_dma_buffer_out_0_data(ETH1_TX_DATA),
|
|
.eth1_tx_dma_buffer_out_0_valid(ETH1_TX_VALID),
|
|
.eth1_tx_dma_buffer_out_0_ready(ETH1_TX_READY),
|
|
.eth1_tx_dma_buffer_out_0_startofpacket(ETH1_TX_SOP),
|
|
.eth1_tx_dma_buffer_out_0_endofpacket(ETH1_TX_EOP),
|
|
|
|
.otg_hpi_address_export(hpi_addr),
|
|
.otg_hpi_data_in_port(hpi_data_in),
|
|
.otg_hpi_data_out_port(hpi_data_out),
|
|
.otg_hpi_cs_export(hpi_cs),
|
|
.otg_hpi_r_export(hpi_r),
|
|
.otg_hpi_w_export(hpi_w),
|
|
.otg_hpi_reset_export(hpi_reset),
|
|
|
|
.audio_pio_export({WM8731_RDATA, WM8731_LDATA})
|
|
);
|
|
|
|
endmodule
|