147 lines
4.9 KiB
Tcl
147 lines
4.9 KiB
Tcl
# TCL File Generated by Component Editor 18.1
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# Wed May 08 22:12:59 CST 2019
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# DO NOT MODIFY
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#
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# lantian_mdio "Lan Tian Ethernet MDIO Clause 22" v1.0
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# 2019.05.08.22:12:59
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#
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module lantian_mdio
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME lantian_mdio
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME "Lan Tian Ethernet MDIO Clause 22"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL lantian_mdio
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
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add_fileset_file lantian_mdio.sv SYSTEM_VERILOG PATH comp/lantian_mdio/lantian_mdio.sv TOP_LEVEL_FILE
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#
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# parameters
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#
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add_parameter CLOCK_DIVIDER STD_LOGIC_VECTOR 40
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set_parameter_property CLOCK_DIVIDER DEFAULT_VALUE 40
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set_parameter_property CLOCK_DIVIDER DISPLAY_NAME CLOCK_DIVIDER
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set_parameter_property CLOCK_DIVIDER TYPE STD_LOGIC_VECTOR
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set_parameter_property CLOCK_DIVIDER UNITS None
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set_parameter_property CLOCK_DIVIDER ALLOWED_RANGES 0:255
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set_parameter_property CLOCK_DIVIDER HDL_PARAMETER true
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#
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# display items
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#
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#
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# connection point avalon_slave
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#
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add_interface avalon_slave avalon end
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set_interface_property avalon_slave addressUnits WORDS
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set_interface_property avalon_slave associatedClock clock
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set_interface_property avalon_slave associatedReset reset
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set_interface_property avalon_slave bitsPerSymbol 8
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set_interface_property avalon_slave burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave burstcountUnits WORDS
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set_interface_property avalon_slave explicitAddressSpan 0
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set_interface_property avalon_slave holdTime 0
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set_interface_property avalon_slave linewrapBursts false
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set_interface_property avalon_slave maximumPendingReadTransactions 0
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set_interface_property avalon_slave maximumPendingWriteTransactions 0
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set_interface_property avalon_slave readLatency 0
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set_interface_property avalon_slave readWaitTime 1
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set_interface_property avalon_slave setupTime 0
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set_interface_property avalon_slave timingUnits Cycles
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set_interface_property avalon_slave writeWaitTime 0
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set_interface_property avalon_slave ENABLED true
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set_interface_property avalon_slave EXPORT_OF ""
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set_interface_property avalon_slave PORT_NAME_MAP ""
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set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave avalon_slave_address address Input 5
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add_interface_port avalon_slave avalon_slave_read read Input 1
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add_interface_port avalon_slave avalon_slave_readdata readdata Output 32
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add_interface_port avalon_slave avalon_slave_waitrequest waitrequest Output 1
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add_interface_port avalon_slave avalon_slave_write write Input 1
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add_interface_port avalon_slave avalon_slave_writedata writedata Input 32
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set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset reset Input 1
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#
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# connection point mdio
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#
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add_interface mdio conduit end
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set_interface_property mdio associatedClock clock
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set_interface_property mdio associatedReset ""
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set_interface_property mdio ENABLED true
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set_interface_property mdio EXPORT_OF ""
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set_interface_property mdio PORT_NAME_MAP ""
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set_interface_property mdio CMSIS_SVD_VARIABLES ""
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set_interface_property mdio SVD_ADDRESS_GROUP ""
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add_interface_port mdio mdc mdc Output 1
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add_interface_port mdio mdio_in mdio_in Input 1
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add_interface_port mdio mdio_out mdio_out Output 1
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add_interface_port mdio mdio_oen mdio_oen Output 1
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add_interface_port mdio phy_addr phy_addr Input 5
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