47 lines
1.8 KiB
Systemverilog
47 lines
1.8 KiB
Systemverilog
// Interface between NIOS II and EZ-OTG chip
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module hpi_io_intf( input Clk, Reset,
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input [1:0] from_sw_address,
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output[15:0] from_sw_data_in,
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input [15:0] from_sw_data_out,
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input from_sw_r, from_sw_w, from_sw_cs, from_sw_reset, // Active low
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inout [15:0] OTG_DATA,
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output[1:0] OTG_ADDR,
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output OTG_RD_N, OTG_WR_N, OTG_CS_N, OTG_RST_N // Active low
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);
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// Buffer (register) for from_sw_data_out because inout bus should be driven
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// by a register, not combinational logic.
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logic [15:0] from_sw_data_out_buffer;
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// TODO: Fill in the blanks below.
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always_ff @ (posedge Clk)
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begin
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if(Reset)
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begin
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from_sw_data_out_buffer <= 16'b0;
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OTG_ADDR <= 2'b0;
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OTG_RD_N <= 1'b1;
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OTG_WR_N <= 1'b1;
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OTG_CS_N <= 1'b1;
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OTG_RST_N <= 1'b1;
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from_sw_data_in <= 16'b0;
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end
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else
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begin
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// from_sw_data_out_buffer <= from_sw_w ? from_sw_data_out_buffer : from_sw_data_out;
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from_sw_data_out_buffer <= from_sw_data_out;
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OTG_ADDR <= from_sw_address;
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OTG_RD_N <= from_sw_r;
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OTG_WR_N <= from_sw_w;
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OTG_CS_N <= from_sw_cs;
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OTG_RST_N <= from_sw_reset;
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// from_sw_data_in <= from_sw_r ? from_sw_data_in : OTG_DATA;
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from_sw_data_in <= OTG_DATA;
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end
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end
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// OTG_DATA should be high Z (tristated) when NIOS is not writing to OTG_DATA inout bus.
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// Look at tristate.sv in lab 6 for an example.
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assign OTG_DATA = from_sw_w ? {16{1'bZ}} : from_sw_data_out_buffer;
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endmodule
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