36 lines
858 B
Systemverilog
36 lines
858 B
Systemverilog
module VGA_entities #(
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parameter REGISTERS = 256
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) (
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// Avalon Clock Input
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input logic CLK,
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// Avalon Reset Input
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input logic RESET,
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// Avalon-MM Slave Signals
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input logic AVL_READ, // Avalon-MM Read
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input logic AVL_WRITE, // Avalon-MM Write
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input logic [7:0] AVL_ADDR, // Avalon-MM Address
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input logic [31:0] AVL_WRITEDATA, // Avalon-MM Write Data
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output logic [31:0] AVL_READDATA, // Avalon-MM Read Data
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// Exported Conduit
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output logic [REGISTERS-1:0][31:0] EXPORT_DATA // Exported Conduit Signal
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);
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genvar i;
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generate
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for(i = 0; i < REGISTERS; i++) begin: generate_vga_entity_registers
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register #(32) entity_register (
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.Clk(CLK), .Reset(RESET),
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.Load((AVL_ADDR == i) && AVL_WRITE),
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.Din(AVL_WRITEDATA),
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.Dout(EXPORT_DATA[i])
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);
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end
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endgenerate
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assign AVL_READDATA = EXPORT_DATA[AVL_ADDR];
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endmodule
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