78 lines
3.1 KiB
Systemverilog
78 lines
3.1 KiB
Systemverilog
module VGA_controller (input Clk, // 50 MHz clock
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Reset, // Active-high reset signal
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output logic VGA_HS, // Horizontal sync pulse. Active low
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VGA_VS, // Vertical sync pulse. Active low
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input VGA_CLK, // 25 MHz VGA clock input
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output logic VGA_BLANK_N, // Blanking interval indicator. Active low.
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VGA_SYNC_N, // Composite Sync signal. Active low. We don't use it in this lab,
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// but the video DAC on the DE2 board requires an input for it.
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output logic [9:0] DrawX, // horizontal coordinate
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DrawY // vertical coordinate
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);
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// 800 pixels per line (including front/back porch)
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// 525 lines per frame (including front/back porch)
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parameter [9:0] H_TOTAL = 10'd800;
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parameter [9:0] V_TOTAL = 10'd525;
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logic VGA_HS_in, VGA_VS_in, VGA_BLANK_N_in;
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logic [9:0] h_counter, v_counter;
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logic [9:0] h_counter_in, v_counter_in;
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assign VGA_SYNC_N = 1'b0;
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assign DrawX = h_counter_in;
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assign DrawY = v_counter_in;
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// VGA control signals.
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// VGA_CLK is generated by PLL, so you will have to manually generate it in simulation.
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always_ff @ (posedge VGA_CLK)
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begin
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if (Reset)
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begin
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VGA_HS <= 1'b0;
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VGA_VS <= 1'b0;
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VGA_BLANK_N <= 1'b0;
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h_counter <= 10'd0;
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v_counter <= 10'd0;
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end
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else
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begin
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VGA_HS <= VGA_HS_in;
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VGA_VS <= VGA_VS_in;
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VGA_BLANK_N <= VGA_BLANK_N_in;
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h_counter <= h_counter_in;
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v_counter <= v_counter_in;
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end
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end
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always_comb
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begin
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// horizontal and vertical counter
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h_counter_in = h_counter + 10'd1;
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v_counter_in = v_counter;
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if(h_counter + 10'd1 == H_TOTAL)
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begin
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h_counter_in = 10'd0;
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if(v_counter + 10'd1 == V_TOTAL)
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v_counter_in = 10'd0;
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else
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v_counter_in = v_counter + 10'd1;
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end
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// Horizontal sync pulse is 96 pixels long at pixels 656-752
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// (Signal is registered to ensure clean output waveform)
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VGA_HS_in = 1'b1;
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if(h_counter_in >= 10'd656 && h_counter_in < 10'd752)
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VGA_HS_in = 1'b0;
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// Vertical sync pulse is 2 lines (800 pixels each) long at line 490-491
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//(Signal is registered to ensure clean output waveform)
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VGA_VS_in = 1'b1;
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if(v_counter_in >= 10'd490 && v_counter_in < 10'd492)
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VGA_VS_in = 1'b0;
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// Display pixels (inhibit blanking) between horizontal 0-639 and vertical 0-479 (640x480)
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VGA_BLANK_N_in = 1'b0;
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if(h_counter_in < 10'd640 && v_counter_in < 10'd480)
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VGA_BLANK_N_in = 1'b1;
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end
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endmodule
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