77 lines
2.2 KiB
Verilog
77 lines
2.2 KiB
Verilog
/*
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Copyright (c) 2016-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Generic ODDR module
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*/
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module oddr #
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(
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire clk,
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input wire [WIDTH-1:0] d1,
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input wire [WIDTH-1:0] d2,
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output wire [WIDTH-1:0] q
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);
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/*
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Provides a consistent output DDR flip flop across multiple FPGA families
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_____ _____ _____ _____
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clk ____/ \_____/ \_____/ \_____/ \_____
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_ ___________ ___________ ___________ ___________ __
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d1 _X____D0_____X____D2_____X____D4_____X____D6_____X__
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_ ___________ ___________ ___________ ___________ __
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d2 _X____D1_____X____D3_____X____D5_____X____D7_____X__
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_____ _____ _____ _____ _____ _____ _____ _____ ____
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d _____X_D0__X_D1__X_D2__X_D3__X_D4__X_D5__X_D6__X_D7_
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*/
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altddio_out #(
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.WIDTH(WIDTH),
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.POWER_UP_HIGH("OFF"),
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.OE_REG("UNUSED")
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)
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altddio_out_inst (
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.aset(1'b0),
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.datain_h(d1),
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.datain_l(d2),
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.outclocken(1'b1),
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.outclock(clk),
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.aclr(1'b0),
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.dataout(q)
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);
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endmodule
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