194 lines
6.5 KiB
Tcl
194 lines
6.5 KiB
Tcl
# TCL File Generated by Component Editor 18.1
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# Mon May 20 23:23:36 CST 2019
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# DO NOT MODIFY
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#
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# avalon_mm_passthrough "Lan Tian Avalon MM Passthrough" v1.0
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# 2019.05.20.23:23:36
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#
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module avalon_mm_passthrough
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME avalon_mm_passthrough
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME "Lan Tian Avalon MM Passthrough"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_mm_passthrough
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file avalon_mm_passthrough.sv SYSTEM_VERILOG PATH comp/avalon_mm_passthrough/avalon_mm_passthrough.sv TOP_LEVEL_FILE
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#
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# parameters
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#
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add_parameter ADDR_WIDTH INTEGER 8
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set_parameter_property ADDR_WIDTH DEFAULT_VALUE 8
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set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
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set_parameter_property ADDR_WIDTH TYPE INTEGER
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set_parameter_property ADDR_WIDTH UNITS None
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set_parameter_property ADDR_WIDTH ALLOWED_RANGES -2147483648:2147483647
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set_parameter_property ADDR_WIDTH HDL_PARAMETER true
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock CLK clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset RESET reset Input 1
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#
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# connection point avl
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#
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add_interface avl avalon end
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set_interface_property avl addressUnits WORDS
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set_interface_property avl associatedClock clock
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set_interface_property avl associatedReset reset
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set_interface_property avl bitsPerSymbol 8
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set_interface_property avl burstOnBurstBoundariesOnly false
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set_interface_property avl burstcountUnits WORDS
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set_interface_property avl explicitAddressSpan 0
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set_interface_property avl holdTime 0
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set_interface_property avl linewrapBursts false
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set_interface_property avl maximumPendingReadTransactions 0
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set_interface_property avl maximumPendingWriteTransactions 0
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set_interface_property avl readLatency 0
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set_interface_property avl readWaitTime 1
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set_interface_property avl setupTime 0
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set_interface_property avl timingUnits Cycles
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set_interface_property avl writeWaitTime 0
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set_interface_property avl ENABLED true
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set_interface_property avl EXPORT_OF ""
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set_interface_property avl PORT_NAME_MAP ""
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set_interface_property avl CMSIS_SVD_VARIABLES ""
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set_interface_property avl SVD_ADDRESS_GROUP ""
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add_interface_port avl AVL_READ read Input 1
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add_interface_port avl AVL_WRITE write Input 1
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add_interface_port avl AVL_WRITEDATA writedata Input 32
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add_interface_port avl AVL_READDATA readdata Output 32
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add_interface_port avl AVL_ADDR address Input 8
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set_interface_assignment avl embeddedsw.configuration.isFlash 0
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set_interface_assignment avl embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avl embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avl embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point clock_source
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#
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add_interface clock_source clock start
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set_interface_property clock_source associatedDirectClock ""
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set_interface_property clock_source clockRate 0
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set_interface_property clock_source clockRateKnown false
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set_interface_property clock_source ENABLED true
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set_interface_property clock_source EXPORT_OF ""
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set_interface_property clock_source PORT_NAME_MAP ""
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set_interface_property clock_source CMSIS_SVD_VARIABLES ""
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set_interface_property clock_source SVD_ADDRESS_GROUP ""
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add_interface_port clock_source PASS_CLK clk Output 1
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#
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# connection point reset_source
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#
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add_interface reset_source reset start
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set_interface_property reset_source associatedClock clock
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set_interface_property reset_source associatedDirectReset ""
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set_interface_property reset_source associatedResetSinks reset
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set_interface_property reset_source synchronousEdges DEASSERT
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set_interface_property reset_source ENABLED true
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set_interface_property reset_source EXPORT_OF ""
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set_interface_property reset_source PORT_NAME_MAP ""
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set_interface_property reset_source CMSIS_SVD_VARIABLES ""
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set_interface_property reset_source SVD_ADDRESS_GROUP ""
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add_interface_port reset_source PASS_RESET reset Output 1
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#
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# connection point pass
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#
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add_interface pass avalon start
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set_interface_property pass addressUnits WORDS
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set_interface_property pass associatedClock clock
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set_interface_property pass associatedReset reset
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set_interface_property pass bitsPerSymbol 8
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set_interface_property pass burstOnBurstBoundariesOnly false
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set_interface_property pass burstcountUnits WORDS
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set_interface_property pass doStreamReads false
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set_interface_property pass doStreamWrites false
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set_interface_property pass holdTime 0
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set_interface_property pass linewrapBursts false
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set_interface_property pass maximumPendingReadTransactions 0
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set_interface_property pass maximumPendingWriteTransactions 0
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set_interface_property pass readLatency 0
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set_interface_property pass readWaitTime 1
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set_interface_property pass setupTime 0
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set_interface_property pass timingUnits Cycles
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set_interface_property pass writeWaitTime 0
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set_interface_property pass ENABLED true
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set_interface_property pass EXPORT_OF ""
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set_interface_property pass PORT_NAME_MAP ""
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set_interface_property pass CMSIS_SVD_VARIABLES ""
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set_interface_property pass SVD_ADDRESS_GROUP ""
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add_interface_port pass PASS_ADDR address Output 8
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add_interface_port pass PASS_READ read Output 1
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add_interface_port pass PASS_READDATA readdata Input 32
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add_interface_port pass PASS_WRITE write Output 1
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add_interface_port pass PASS_WRITEDATA writedata Output 32
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