zjui-ece385-final/ECE385_bsp/system.h

/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'nios2_cpu' in SOPC Builder design 'ECE385'
 * SOPC Builder design path: ../ECE385.sopcinfo
 *
 * Generated: Tue Jun 04 17:31:29 CST 2019
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x00008820
#define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "tiny"
#define ALT_CPU_DATA_ADDR_WIDTH 0x1c
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x00040020
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 0
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_ICACHE_SIZE 0
#define ALT_CPU_INST_ADDR_WIDTH 0x1c
#define ALT_CPU_NAME "nios2_cpu"
#define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00040000


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x00008820
#define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "tiny"
#define NIOS2_DATA_ADDR_WIDTH 0x1c
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x00040020
#define NIOS2_FLASH_ACCELERATOR_LINES 0
#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_ICACHE_SIZE 0
#define NIOS2_INST_ADDR_WIDTH 0x1c
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00040000


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SGDMA
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER
#define __ALTERA_NIOS2_GEN2
#define __ALTPLL
#define __AVALON_MM_PASSTHROUGH
#define __LANTIAN_MDIO
#define __SRAM_MULTIPLEXER


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "Cyclone IV E"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/nios2_jtag_uart"
#define ALT_STDERR_BASE 0x9b60
#define ALT_STDERR_DEV nios2_jtag_uart
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/nios2_jtag_uart"
#define ALT_STDIN_BASE 0x9b60
#define ALT_STDIN_DEV nios2_jtag_uart
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/nios2_jtag_uart"
#define ALT_STDOUT_BASE 0x9b60
#define ALT_STDOUT_DEV nios2_jtag_uart
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "ECE385"


/*
 * audio_pio configuration
 *
 */

#define ALT_MODULE_CLASS_audio_pio altera_avalon_pio
#define AUDIO_PIO_BASE 0x9af0
#define AUDIO_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define AUDIO_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define AUDIO_PIO_CAPTURE 0
#define AUDIO_PIO_DATA_WIDTH 32
#define AUDIO_PIO_DO_TEST_BENCH_WIRING 0
#define AUDIO_PIO_DRIVEN_SIM_VALUE 0
#define AUDIO_PIO_EDGE_TYPE "NONE"
#define AUDIO_PIO_FREQ 50000000
#define AUDIO_PIO_HAS_IN 0
#define AUDIO_PIO_HAS_OUT 1
#define AUDIO_PIO_HAS_TRI 0
#define AUDIO_PIO_IRQ -1
#define AUDIO_PIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define AUDIO_PIO_IRQ_TYPE "NONE"
#define AUDIO_PIO_NAME "/dev/audio_pio"
#define AUDIO_PIO_RESET_VALUE 0
#define AUDIO_PIO_SPAN 16
#define AUDIO_PIO_TYPE "altera_avalon_pio"


/*
 * audio_timer configuration
 *
 */

#define ALT_MODULE_CLASS_audio_timer altera_avalon_timer
#define AUDIO_TIMER_ALWAYS_RUN 1
#define AUDIO_TIMER_BASE 0x9a40
#define AUDIO_TIMER_COUNTER_SIZE 32
#define AUDIO_TIMER_FIXED_PERIOD 1
#define AUDIO_TIMER_FREQ 50000000
#define AUDIO_TIMER_IRQ 7
#define AUDIO_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define AUDIO_TIMER_LOAD_VALUE 6249
#define AUDIO_TIMER_MULT 1.0E-6
#define AUDIO_TIMER_NAME "/dev/audio_timer"
#define AUDIO_TIMER_PERIOD 125
#define AUDIO_TIMER_PERIOD_UNITS "us"
#define AUDIO_TIMER_RESET_OUTPUT 0
#define AUDIO_TIMER_SNAPSHOT 0
#define AUDIO_TIMER_SPAN 32
#define AUDIO_TIMER_TICKS_PER_SEC 8000
#define AUDIO_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define AUDIO_TIMER_TYPE "altera_avalon_timer"


/*
 * eth0_mdio configuration
 *
 */

#define ALT_MODULE_CLASS_eth0_mdio lantian_mdio
#define ETH0_MDIO_BASE 0x9800
#define ETH0_MDIO_IRQ -1
#define ETH0_MDIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETH0_MDIO_NAME "/dev/eth0_mdio"
#define ETH0_MDIO_SPAN 128
#define ETH0_MDIO_TYPE "lantian_mdio"


/*
 * eth0_mdio configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_ETH0_MDIO_BASE 0x9800
#define NIOS2_DMA_M_READ_ETH0_MDIO_IRQ -1
#define NIOS2_DMA_M_READ_ETH0_MDIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH0_MDIO_NAME "/dev/eth0_mdio"
#define NIOS2_DMA_M_READ_ETH0_MDIO_SPAN 128
#define NIOS2_DMA_M_READ_ETH0_MDIO_TYPE "lantian_mdio"


/*
 * eth0_mdio configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_ETH0_MDIO_BASE 0x9800
#define NIOS2_DMA_M_WRITE_ETH0_MDIO_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH0_MDIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH0_MDIO_NAME "/dev/eth0_mdio"
#define NIOS2_DMA_M_WRITE_ETH0_MDIO_SPAN 128
#define NIOS2_DMA_M_WRITE_ETH0_MDIO_TYPE "lantian_mdio"


/*
 * eth0_rx_dma configuration
 *
 */

#define ALT_MODULE_CLASS_eth0_rx_dma altera_avalon_sgdma
#define ETH0_RX_DMA_ADDRESS_WIDTH 32
#define ETH0_RX_DMA_ALWAYS_DO_MAX_BURST 1
#define ETH0_RX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define ETH0_RX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define ETH0_RX_DMA_BASE 0x9a00
#define ETH0_RX_DMA_BURST_DATA_WIDTH 8
#define ETH0_RX_DMA_BURST_TRANSFER 0
#define ETH0_RX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define ETH0_RX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define ETH0_RX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define ETH0_RX_DMA_CONTROL_DATA_WIDTH 8
#define ETH0_RX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define ETH0_RX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define ETH0_RX_DMA_DESCRIPTOR_READ_BURST 0
#define ETH0_RX_DMA_DESC_DATA_WIDTH 32
#define ETH0_RX_DMA_HAS_READ_BLOCK 0
#define ETH0_RX_DMA_HAS_WRITE_BLOCK 1
#define ETH0_RX_DMA_IN_ERROR_WIDTH 3
#define ETH0_RX_DMA_IRQ 2
#define ETH0_RX_DMA_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ETH0_RX_DMA_NAME "/dev/eth0_rx_dma"
#define ETH0_RX_DMA_OUT_ERROR_WIDTH 3
#define ETH0_RX_DMA_READ_BLOCK_DATA_WIDTH 8
#define ETH0_RX_DMA_READ_BURSTCOUNT_WIDTH 4
#define ETH0_RX_DMA_SPAN 64
#define ETH0_RX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define ETH0_RX_DMA_STREAM_DATA_WIDTH 8
#define ETH0_RX_DMA_SYMBOLS_PER_BEAT 1
#define ETH0_RX_DMA_TYPE "altera_avalon_sgdma"
#define ETH0_RX_DMA_UNALIGNED_TRANSFER 0
#define ETH0_RX_DMA_WRITE_BLOCK_DATA_WIDTH 8
#define ETH0_RX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth0_rx_dma configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_ETH0_RX_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_BASE 0x9a00
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_HAS_READ_BLOCK 0
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_HAS_WRITE_BLOCK 1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_IN_ERROR_WIDTH 3
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_IRQ -1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_NAME "/dev/eth0_rx_dma"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_OUT_ERROR_WIDTH 3
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_READ_BLOCK_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_SPAN 64
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_STREAM_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_SYMBOLS_PER_BEAT 1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_UNALIGNED_TRANSFER 0
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_WRITE_BLOCK_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth0_rx_dma configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_BASE 0x9a00
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_HAS_READ_BLOCK 0
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_HAS_WRITE_BLOCK 1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_IN_ERROR_WIDTH 3
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_NAME "/dev/eth0_rx_dma"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_OUT_ERROR_WIDTH 3
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_READ_BLOCK_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_SPAN 64
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_STREAM_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_SYMBOLS_PER_BEAT 1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_UNALIGNED_TRANSFER 0
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_WRITE_BLOCK_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth0_tx_dma configuration
 *
 */

#define ALT_MODULE_CLASS_eth0_tx_dma altera_avalon_sgdma
#define ETH0_TX_DMA_ADDRESS_WIDTH 32
#define ETH0_TX_DMA_ALWAYS_DO_MAX_BURST 1
#define ETH0_TX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define ETH0_TX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define ETH0_TX_DMA_BASE 0x99c0
#define ETH0_TX_DMA_BURST_DATA_WIDTH 8
#define ETH0_TX_DMA_BURST_TRANSFER 0
#define ETH0_TX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define ETH0_TX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define ETH0_TX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define ETH0_TX_DMA_CONTROL_DATA_WIDTH 8
#define ETH0_TX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define ETH0_TX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define ETH0_TX_DMA_DESCRIPTOR_READ_BURST 0
#define ETH0_TX_DMA_DESC_DATA_WIDTH 32
#define ETH0_TX_DMA_HAS_READ_BLOCK 1
#define ETH0_TX_DMA_HAS_WRITE_BLOCK 0
#define ETH0_TX_DMA_IN_ERROR_WIDTH 0
#define ETH0_TX_DMA_IRQ 3
#define ETH0_TX_DMA_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ETH0_TX_DMA_NAME "/dev/eth0_tx_dma"
#define ETH0_TX_DMA_OUT_ERROR_WIDTH 0
#define ETH0_TX_DMA_READ_BLOCK_DATA_WIDTH 32
#define ETH0_TX_DMA_READ_BURSTCOUNT_WIDTH 4
#define ETH0_TX_DMA_SPAN 64
#define ETH0_TX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define ETH0_TX_DMA_STREAM_DATA_WIDTH 32
#define ETH0_TX_DMA_SYMBOLS_PER_BEAT 4
#define ETH0_TX_DMA_TYPE "altera_avalon_sgdma"
#define ETH0_TX_DMA_UNALIGNED_TRANSFER 0
#define ETH0_TX_DMA_WRITE_BLOCK_DATA_WIDTH 32
#define ETH0_TX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth0_tx_dma configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_ETH0_TX_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_BASE 0x99c0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_HAS_READ_BLOCK 1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_HAS_WRITE_BLOCK 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_IN_ERROR_WIDTH 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_IRQ -1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_NAME "/dev/eth0_tx_dma"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_OUT_ERROR_WIDTH 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_READ_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_SPAN 64
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_STREAM_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_SYMBOLS_PER_BEAT 4
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_UNALIGNED_TRANSFER 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_WRITE_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth0_tx_dma configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_BASE 0x99c0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_HAS_READ_BLOCK 1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_HAS_WRITE_BLOCK 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_IN_ERROR_WIDTH 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_NAME "/dev/eth0_tx_dma"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_OUT_ERROR_WIDTH 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_READ_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_SPAN 64
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_STREAM_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_SYMBOLS_PER_BEAT 4
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_UNALIGNED_TRANSFER 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_WRITE_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth1_mdio configuration
 *
 */

#define ALT_MODULE_CLASS_eth1_mdio lantian_mdio
#define ETH1_MDIO_BASE 0x9880
#define ETH1_MDIO_IRQ -1
#define ETH1_MDIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETH1_MDIO_NAME "/dev/eth1_mdio"
#define ETH1_MDIO_SPAN 128
#define ETH1_MDIO_TYPE "lantian_mdio"


/*
 * eth1_mdio configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_ETH1_MDIO_BASE 0x9880
#define NIOS2_DMA_M_READ_ETH1_MDIO_IRQ -1
#define NIOS2_DMA_M_READ_ETH1_MDIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH1_MDIO_NAME "/dev/eth1_mdio"
#define NIOS2_DMA_M_READ_ETH1_MDIO_SPAN 128
#define NIOS2_DMA_M_READ_ETH1_MDIO_TYPE "lantian_mdio"


/*
 * eth1_mdio configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_ETH1_MDIO_BASE 0x9880
#define NIOS2_DMA_M_WRITE_ETH1_MDIO_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH1_MDIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH1_MDIO_NAME "/dev/eth1_mdio"
#define NIOS2_DMA_M_WRITE_ETH1_MDIO_SPAN 128
#define NIOS2_DMA_M_WRITE_ETH1_MDIO_TYPE "lantian_mdio"


/*
 * eth1_rx_dma configuration
 *
 */

#define ALT_MODULE_CLASS_eth1_rx_dma altera_avalon_sgdma
#define ETH1_RX_DMA_ADDRESS_WIDTH 32
#define ETH1_RX_DMA_ALWAYS_DO_MAX_BURST 1
#define ETH1_RX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define ETH1_RX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define ETH1_RX_DMA_BASE 0x9980
#define ETH1_RX_DMA_BURST_DATA_WIDTH 8
#define ETH1_RX_DMA_BURST_TRANSFER 0
#define ETH1_RX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define ETH1_RX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define ETH1_RX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define ETH1_RX_DMA_CONTROL_DATA_WIDTH 8
#define ETH1_RX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define ETH1_RX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define ETH1_RX_DMA_DESCRIPTOR_READ_BURST 0
#define ETH1_RX_DMA_DESC_DATA_WIDTH 32
#define ETH1_RX_DMA_HAS_READ_BLOCK 0
#define ETH1_RX_DMA_HAS_WRITE_BLOCK 1
#define ETH1_RX_DMA_IN_ERROR_WIDTH 3
#define ETH1_RX_DMA_IRQ 4
#define ETH1_RX_DMA_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ETH1_RX_DMA_NAME "/dev/eth1_rx_dma"
#define ETH1_RX_DMA_OUT_ERROR_WIDTH 3
#define ETH1_RX_DMA_READ_BLOCK_DATA_WIDTH 8
#define ETH1_RX_DMA_READ_BURSTCOUNT_WIDTH 4
#define ETH1_RX_DMA_SPAN 64
#define ETH1_RX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define ETH1_RX_DMA_STREAM_DATA_WIDTH 8
#define ETH1_RX_DMA_SYMBOLS_PER_BEAT 1
#define ETH1_RX_DMA_TYPE "altera_avalon_sgdma"
#define ETH1_RX_DMA_UNALIGNED_TRANSFER 0
#define ETH1_RX_DMA_WRITE_BLOCK_DATA_WIDTH 8
#define ETH1_RX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth1_rx_dma configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_ETH1_RX_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_BASE 0x9980
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_HAS_READ_BLOCK 0
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_HAS_WRITE_BLOCK 1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_IN_ERROR_WIDTH 3
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_IRQ -1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_NAME "/dev/eth1_rx_dma"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_OUT_ERROR_WIDTH 3
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_READ_BLOCK_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_SPAN 64
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_STREAM_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_SYMBOLS_PER_BEAT 1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_UNALIGNED_TRANSFER 0
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_WRITE_BLOCK_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth1_rx_dma configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_BASE 0x9980
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_HAS_READ_BLOCK 0
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_HAS_WRITE_BLOCK 1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_IN_ERROR_WIDTH 3
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_NAME "/dev/eth1_rx_dma"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_OUT_ERROR_WIDTH 3
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_READ_BLOCK_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_SPAN 64
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_STREAM_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_SYMBOLS_PER_BEAT 1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_UNALIGNED_TRANSFER 0
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_WRITE_BLOCK_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth1_tx_dma configuration
 *
 */

#define ALT_MODULE_CLASS_eth1_tx_dma altera_avalon_sgdma
#define ETH1_TX_DMA_ADDRESS_WIDTH 32
#define ETH1_TX_DMA_ALWAYS_DO_MAX_BURST 1
#define ETH1_TX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define ETH1_TX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define ETH1_TX_DMA_BASE 0x9940
#define ETH1_TX_DMA_BURST_DATA_WIDTH 8
#define ETH1_TX_DMA_BURST_TRANSFER 0
#define ETH1_TX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define ETH1_TX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define ETH1_TX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define ETH1_TX_DMA_CONTROL_DATA_WIDTH 8
#define ETH1_TX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define ETH1_TX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define ETH1_TX_DMA_DESCRIPTOR_READ_BURST 0
#define ETH1_TX_DMA_DESC_DATA_WIDTH 32
#define ETH1_TX_DMA_HAS_READ_BLOCK 1
#define ETH1_TX_DMA_HAS_WRITE_BLOCK 0
#define ETH1_TX_DMA_IN_ERROR_WIDTH 3
#define ETH1_TX_DMA_IRQ 5
#define ETH1_TX_DMA_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ETH1_TX_DMA_NAME "/dev/eth1_tx_dma"
#define ETH1_TX_DMA_OUT_ERROR_WIDTH 0
#define ETH1_TX_DMA_READ_BLOCK_DATA_WIDTH 32
#define ETH1_TX_DMA_READ_BURSTCOUNT_WIDTH 4
#define ETH1_TX_DMA_SPAN 64
#define ETH1_TX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define ETH1_TX_DMA_STREAM_DATA_WIDTH 32
#define ETH1_TX_DMA_SYMBOLS_PER_BEAT 4
#define ETH1_TX_DMA_TYPE "altera_avalon_sgdma"
#define ETH1_TX_DMA_UNALIGNED_TRANSFER 0
#define ETH1_TX_DMA_WRITE_BLOCK_DATA_WIDTH 32
#define ETH1_TX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth1_tx_dma configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_ETH1_TX_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_BASE 0x9940
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_HAS_READ_BLOCK 1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_HAS_WRITE_BLOCK 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_IN_ERROR_WIDTH 3
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_IRQ -1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_NAME "/dev/eth1_tx_dma"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_OUT_ERROR_WIDTH 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_READ_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_SPAN 64
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_STREAM_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_SYMBOLS_PER_BEAT 4
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_UNALIGNED_TRANSFER 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_WRITE_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * eth1_tx_dma configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_BASE 0x9940
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_HAS_READ_BLOCK 1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_HAS_WRITE_BLOCK 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_IN_ERROR_WIDTH 3
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_NAME "/dev/eth1_tx_dma"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_OUT_ERROR_WIDTH 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_READ_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_SPAN 64
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_STREAM_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_SYMBOLS_PER_BEAT 4
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_UNALIGNED_TRANSFER 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_WRITE_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * hal configuration
 *
 */

#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
#define ALT_MAX_FD 32
#define ALT_SYS_CLK NIOS2_TIMER
#define ALT_TIMESTAMP_CLK NIOS2_TIMER


/*
 * io_hex configuration
 *
 */

#define ALT_MODULE_CLASS_io_hex altera_avalon_pio
#define IO_HEX_BASE 0x9a60
#define IO_HEX_BIT_CLEARING_EDGE_REGISTER 0
#define IO_HEX_BIT_MODIFYING_OUTPUT_REGISTER 1
#define IO_HEX_CAPTURE 0
#define IO_HEX_DATA_WIDTH 32
#define IO_HEX_DO_TEST_BENCH_WIRING 0
#define IO_HEX_DRIVEN_SIM_VALUE 0
#define IO_HEX_EDGE_TYPE "NONE"
#define IO_HEX_FREQ 50000000
#define IO_HEX_HAS_IN 0
#define IO_HEX_HAS_OUT 1
#define IO_HEX_HAS_TRI 0
#define IO_HEX_IRQ -1
#define IO_HEX_IRQ_INTERRUPT_CONTROLLER_ID -1
#define IO_HEX_IRQ_TYPE "NONE"
#define IO_HEX_NAME "/dev/io_hex"
#define IO_HEX_RESET_VALUE 0
#define IO_HEX_SPAN 32
#define IO_HEX_TYPE "altera_avalon_pio"


/*
 * io_hex configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_IO_HEX_BASE 0x9a60
#define NIOS2_DMA_M_READ_IO_HEX_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_READ_IO_HEX_BIT_MODIFYING_OUTPUT_REGISTER 1
#define NIOS2_DMA_M_READ_IO_HEX_CAPTURE 0
#define NIOS2_DMA_M_READ_IO_HEX_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_IO_HEX_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_READ_IO_HEX_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_READ_IO_HEX_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_HEX_FREQ 50000000
#define NIOS2_DMA_M_READ_IO_HEX_HAS_IN 0
#define NIOS2_DMA_M_READ_IO_HEX_HAS_OUT 1
#define NIOS2_DMA_M_READ_IO_HEX_HAS_TRI 0
#define NIOS2_DMA_M_READ_IO_HEX_IRQ -1
#define NIOS2_DMA_M_READ_IO_HEX_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_IO_HEX_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_HEX_NAME "/dev/io_hex"
#define NIOS2_DMA_M_READ_IO_HEX_RESET_VALUE 0
#define NIOS2_DMA_M_READ_IO_HEX_SPAN 32
#define NIOS2_DMA_M_READ_IO_HEX_TYPE "altera_avalon_pio"


/*
 * io_hex configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_IO_HEX_BASE 0x9a60
#define NIOS2_DMA_M_WRITE_IO_HEX_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_WRITE_IO_HEX_BIT_MODIFYING_OUTPUT_REGISTER 1
#define NIOS2_DMA_M_WRITE_IO_HEX_CAPTURE 0
#define NIOS2_DMA_M_WRITE_IO_HEX_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_IO_HEX_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_WRITE_IO_HEX_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_WRITE_IO_HEX_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_WRITE_IO_HEX_FREQ 50000000
#define NIOS2_DMA_M_WRITE_IO_HEX_HAS_IN 0
#define NIOS2_DMA_M_WRITE_IO_HEX_HAS_OUT 1
#define NIOS2_DMA_M_WRITE_IO_HEX_HAS_TRI 0
#define NIOS2_DMA_M_WRITE_IO_HEX_IRQ -1
#define NIOS2_DMA_M_WRITE_IO_HEX_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_IO_HEX_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_WRITE_IO_HEX_NAME "/dev/io_hex"
#define NIOS2_DMA_M_WRITE_IO_HEX_RESET_VALUE 0
#define NIOS2_DMA_M_WRITE_IO_HEX_SPAN 32
#define NIOS2_DMA_M_WRITE_IO_HEX_TYPE "altera_avalon_pio"


/*
 * io_keys configuration
 *
 */

#define ALT_MODULE_CLASS_io_keys altera_avalon_pio
#define IO_KEYS_BASE 0x9b30
#define IO_KEYS_BIT_CLEARING_EDGE_REGISTER 0
#define IO_KEYS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define IO_KEYS_CAPTURE 0
#define IO_KEYS_DATA_WIDTH 4
#define IO_KEYS_DO_TEST_BENCH_WIRING 0
#define IO_KEYS_DRIVEN_SIM_VALUE 0
#define IO_KEYS_EDGE_TYPE "NONE"
#define IO_KEYS_FREQ 50000000
#define IO_KEYS_HAS_IN 1
#define IO_KEYS_HAS_OUT 0
#define IO_KEYS_HAS_TRI 0
#define IO_KEYS_IRQ -1
#define IO_KEYS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define IO_KEYS_IRQ_TYPE "NONE"
#define IO_KEYS_NAME "/dev/io_keys"
#define IO_KEYS_RESET_VALUE 0
#define IO_KEYS_SPAN 16
#define IO_KEYS_TYPE "altera_avalon_pio"


/*
 * io_keys configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_IO_KEYS_BASE 0x9b30
#define NIOS2_DMA_M_READ_IO_KEYS_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_READ_IO_KEYS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NIOS2_DMA_M_READ_IO_KEYS_CAPTURE 0
#define NIOS2_DMA_M_READ_IO_KEYS_DATA_WIDTH 4
#define NIOS2_DMA_M_READ_IO_KEYS_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_READ_IO_KEYS_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_READ_IO_KEYS_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_KEYS_FREQ 50000000
#define NIOS2_DMA_M_READ_IO_KEYS_HAS_IN 1
#define NIOS2_DMA_M_READ_IO_KEYS_HAS_OUT 0
#define NIOS2_DMA_M_READ_IO_KEYS_HAS_TRI 0
#define NIOS2_DMA_M_READ_IO_KEYS_IRQ -1
#define NIOS2_DMA_M_READ_IO_KEYS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_IO_KEYS_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_KEYS_NAME "/dev/io_keys"
#define NIOS2_DMA_M_READ_IO_KEYS_RESET_VALUE 0
#define NIOS2_DMA_M_READ_IO_KEYS_SPAN 16
#define NIOS2_DMA_M_READ_IO_KEYS_TYPE "altera_avalon_pio"


/*
 * io_led_green configuration
 *
 */

#define ALT_MODULE_CLASS_io_led_green altera_avalon_pio
#define IO_LED_GREEN_BASE 0x9a80
#define IO_LED_GREEN_BIT_CLEARING_EDGE_REGISTER 0
#define IO_LED_GREEN_BIT_MODIFYING_OUTPUT_REGISTER 1
#define IO_LED_GREEN_CAPTURE 0
#define IO_LED_GREEN_DATA_WIDTH 9
#define IO_LED_GREEN_DO_TEST_BENCH_WIRING 0
#define IO_LED_GREEN_DRIVEN_SIM_VALUE 0
#define IO_LED_GREEN_EDGE_TYPE "NONE"
#define IO_LED_GREEN_FREQ 50000000
#define IO_LED_GREEN_HAS_IN 0
#define IO_LED_GREEN_HAS_OUT 1
#define IO_LED_GREEN_HAS_TRI 0
#define IO_LED_GREEN_IRQ -1
#define IO_LED_GREEN_IRQ_INTERRUPT_CONTROLLER_ID -1
#define IO_LED_GREEN_IRQ_TYPE "NONE"
#define IO_LED_GREEN_NAME "/dev/io_led_green"
#define IO_LED_GREEN_RESET_VALUE 0
#define IO_LED_GREEN_SPAN 32
#define IO_LED_GREEN_TYPE "altera_avalon_pio"


/*
 * io_led_green configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_IO_LED_GREEN_BASE 0x9a80
#define NIOS2_DMA_M_READ_IO_LED_GREEN_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_READ_IO_LED_GREEN_BIT_MODIFYING_OUTPUT_REGISTER 1
#define NIOS2_DMA_M_READ_IO_LED_GREEN_CAPTURE 0
#define NIOS2_DMA_M_READ_IO_LED_GREEN_DATA_WIDTH 9
#define NIOS2_DMA_M_READ_IO_LED_GREEN_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_READ_IO_LED_GREEN_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_READ_IO_LED_GREEN_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_LED_GREEN_FREQ 50000000
#define NIOS2_DMA_M_READ_IO_LED_GREEN_HAS_IN 0
#define NIOS2_DMA_M_READ_IO_LED_GREEN_HAS_OUT 1
#define NIOS2_DMA_M_READ_IO_LED_GREEN_HAS_TRI 0
#define NIOS2_DMA_M_READ_IO_LED_GREEN_IRQ -1
#define NIOS2_DMA_M_READ_IO_LED_GREEN_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_IO_LED_GREEN_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_LED_GREEN_NAME "/dev/io_led_green"
#define NIOS2_DMA_M_READ_IO_LED_GREEN_RESET_VALUE 0
#define NIOS2_DMA_M_READ_IO_LED_GREEN_SPAN 32
#define NIOS2_DMA_M_READ_IO_LED_GREEN_TYPE "altera_avalon_pio"


/*
 * io_led_green configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_BASE 0x9a80
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_BIT_MODIFYING_OUTPUT_REGISTER 1
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_CAPTURE 0
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_DATA_WIDTH 9
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_FREQ 50000000
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_HAS_IN 0
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_HAS_OUT 1
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_HAS_TRI 0
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_IRQ -1
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_NAME "/dev/io_led_green"
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_RESET_VALUE 0
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_SPAN 32
#define NIOS2_DMA_M_WRITE_IO_LED_GREEN_TYPE "altera_avalon_pio"


/*
 * io_led_red configuration
 *
 */

#define ALT_MODULE_CLASS_io_led_red altera_avalon_pio
#define IO_LED_RED_BASE 0x9ac0
#define IO_LED_RED_BIT_CLEARING_EDGE_REGISTER 0
#define IO_LED_RED_BIT_MODIFYING_OUTPUT_REGISTER 1
#define IO_LED_RED_CAPTURE 0
#define IO_LED_RED_DATA_WIDTH 18
#define IO_LED_RED_DO_TEST_BENCH_WIRING 0
#define IO_LED_RED_DRIVEN_SIM_VALUE 0
#define IO_LED_RED_EDGE_TYPE "NONE"
#define IO_LED_RED_FREQ 50000000
#define IO_LED_RED_HAS_IN 0
#define IO_LED_RED_HAS_OUT 1
#define IO_LED_RED_HAS_TRI 0
#define IO_LED_RED_IRQ -1
#define IO_LED_RED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define IO_LED_RED_IRQ_TYPE "NONE"
#define IO_LED_RED_NAME "/dev/io_led_red"
#define IO_LED_RED_RESET_VALUE 0
#define IO_LED_RED_SPAN 32
#define IO_LED_RED_TYPE "altera_avalon_pio"


/*
 * io_led_red configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_IO_LED_RED_BASE 0x9ac0
#define NIOS2_DMA_M_READ_IO_LED_RED_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_READ_IO_LED_RED_BIT_MODIFYING_OUTPUT_REGISTER 1
#define NIOS2_DMA_M_READ_IO_LED_RED_CAPTURE 0
#define NIOS2_DMA_M_READ_IO_LED_RED_DATA_WIDTH 18
#define NIOS2_DMA_M_READ_IO_LED_RED_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_READ_IO_LED_RED_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_READ_IO_LED_RED_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_LED_RED_FREQ 50000000
#define NIOS2_DMA_M_READ_IO_LED_RED_HAS_IN 0
#define NIOS2_DMA_M_READ_IO_LED_RED_HAS_OUT 1
#define NIOS2_DMA_M_READ_IO_LED_RED_HAS_TRI 0
#define NIOS2_DMA_M_READ_IO_LED_RED_IRQ -1
#define NIOS2_DMA_M_READ_IO_LED_RED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_IO_LED_RED_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_LED_RED_NAME "/dev/io_led_red"
#define NIOS2_DMA_M_READ_IO_LED_RED_RESET_VALUE 0
#define NIOS2_DMA_M_READ_IO_LED_RED_SPAN 32
#define NIOS2_DMA_M_READ_IO_LED_RED_TYPE "altera_avalon_pio"


/*
 * io_led_red configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_IO_LED_RED_BASE 0x9ac0
#define NIOS2_DMA_M_WRITE_IO_LED_RED_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_WRITE_IO_LED_RED_BIT_MODIFYING_OUTPUT_REGISTER 1
#define NIOS2_DMA_M_WRITE_IO_LED_RED_CAPTURE 0
#define NIOS2_DMA_M_WRITE_IO_LED_RED_DATA_WIDTH 18
#define NIOS2_DMA_M_WRITE_IO_LED_RED_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_WRITE_IO_LED_RED_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_WRITE_IO_LED_RED_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_WRITE_IO_LED_RED_FREQ 50000000
#define NIOS2_DMA_M_WRITE_IO_LED_RED_HAS_IN 0
#define NIOS2_DMA_M_WRITE_IO_LED_RED_HAS_OUT 1
#define NIOS2_DMA_M_WRITE_IO_LED_RED_HAS_TRI 0
#define NIOS2_DMA_M_WRITE_IO_LED_RED_IRQ -1
#define NIOS2_DMA_M_WRITE_IO_LED_RED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_IO_LED_RED_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_WRITE_IO_LED_RED_NAME "/dev/io_led_red"
#define NIOS2_DMA_M_WRITE_IO_LED_RED_RESET_VALUE 0
#define NIOS2_DMA_M_WRITE_IO_LED_RED_SPAN 32
#define NIOS2_DMA_M_WRITE_IO_LED_RED_TYPE "altera_avalon_pio"


/*
 * io_switches configuration
 *
 */

#define ALT_MODULE_CLASS_io_switches altera_avalon_pio
#define IO_SWITCHES_BASE 0x9b20
#define IO_SWITCHES_BIT_CLEARING_EDGE_REGISTER 0
#define IO_SWITCHES_BIT_MODIFYING_OUTPUT_REGISTER 0
#define IO_SWITCHES_CAPTURE 0
#define IO_SWITCHES_DATA_WIDTH 18
#define IO_SWITCHES_DO_TEST_BENCH_WIRING 0
#define IO_SWITCHES_DRIVEN_SIM_VALUE 0
#define IO_SWITCHES_EDGE_TYPE "NONE"
#define IO_SWITCHES_FREQ 50000000
#define IO_SWITCHES_HAS_IN 1
#define IO_SWITCHES_HAS_OUT 0
#define IO_SWITCHES_HAS_TRI 0
#define IO_SWITCHES_IRQ -1
#define IO_SWITCHES_IRQ_INTERRUPT_CONTROLLER_ID -1
#define IO_SWITCHES_IRQ_TYPE "NONE"
#define IO_SWITCHES_NAME "/dev/io_switches"
#define IO_SWITCHES_RESET_VALUE 0
#define IO_SWITCHES_SPAN 16
#define IO_SWITCHES_TYPE "altera_avalon_pio"


/*
 * io_switches configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_IO_SWITCHES_BASE 0x9b20
#define NIOS2_DMA_M_READ_IO_SWITCHES_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_READ_IO_SWITCHES_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NIOS2_DMA_M_READ_IO_SWITCHES_CAPTURE 0
#define NIOS2_DMA_M_READ_IO_SWITCHES_DATA_WIDTH 18
#define NIOS2_DMA_M_READ_IO_SWITCHES_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_READ_IO_SWITCHES_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_READ_IO_SWITCHES_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_SWITCHES_FREQ 50000000
#define NIOS2_DMA_M_READ_IO_SWITCHES_HAS_IN 1
#define NIOS2_DMA_M_READ_IO_SWITCHES_HAS_OUT 0
#define NIOS2_DMA_M_READ_IO_SWITCHES_HAS_TRI 0
#define NIOS2_DMA_M_READ_IO_SWITCHES_IRQ -1
#define NIOS2_DMA_M_READ_IO_SWITCHES_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_IO_SWITCHES_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_SWITCHES_NAME "/dev/io_switches"
#define NIOS2_DMA_M_READ_IO_SWITCHES_RESET_VALUE 0
#define NIOS2_DMA_M_READ_IO_SWITCHES_SPAN 16
#define NIOS2_DMA_M_READ_IO_SWITCHES_TYPE "altera_avalon_pio"


/*
 * io_vga_sync configuration
 *
 */

#define ALT_MODULE_CLASS_io_vga_sync altera_avalon_pio
#define IO_VGA_SYNC_BASE 0x9b10
#define IO_VGA_SYNC_BIT_CLEARING_EDGE_REGISTER 0
#define IO_VGA_SYNC_BIT_MODIFYING_OUTPUT_REGISTER 0
#define IO_VGA_SYNC_CAPTURE 0
#define IO_VGA_SYNC_DATA_WIDTH 1
#define IO_VGA_SYNC_DO_TEST_BENCH_WIRING 0
#define IO_VGA_SYNC_DRIVEN_SIM_VALUE 0
#define IO_VGA_SYNC_EDGE_TYPE "NONE"
#define IO_VGA_SYNC_FREQ 50000000
#define IO_VGA_SYNC_HAS_IN 1
#define IO_VGA_SYNC_HAS_OUT 0
#define IO_VGA_SYNC_HAS_TRI 0
#define IO_VGA_SYNC_IRQ -1
#define IO_VGA_SYNC_IRQ_INTERRUPT_CONTROLLER_ID -1
#define IO_VGA_SYNC_IRQ_TYPE "NONE"
#define IO_VGA_SYNC_NAME "/dev/io_vga_sync"
#define IO_VGA_SYNC_RESET_VALUE 0
#define IO_VGA_SYNC_SPAN 16
#define IO_VGA_SYNC_TYPE "altera_avalon_pio"


/*
 * io_vga_sync configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_IO_VGA_SYNC_BASE 0x9b10
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_CAPTURE 0
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_DATA_WIDTH 1
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_FREQ 50000000
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_HAS_IN 1
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_HAS_OUT 0
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_HAS_TRI 0
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_IRQ -1
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_NAME "/dev/io_vga_sync"
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_RESET_VALUE 0
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_SPAN 16
#define NIOS2_DMA_M_READ_IO_VGA_SYNC_TYPE "altera_avalon_pio"


/*
 * nios2_dma configuration
 *
 */

#define ALT_MODULE_CLASS_nios2_dma altera_avalon_sgdma
#define NIOS2_DMA_ADDRESS_WIDTH 32
#define NIOS2_DMA_ALWAYS_DO_MAX_BURST 1
#define NIOS2_DMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define NIOS2_DMA_AVALON_MM_BYTE_REORDER_MODE 0
#define NIOS2_DMA_BASE 0x9900
#define NIOS2_DMA_BURST_DATA_WIDTH 8
#define NIOS2_DMA_BURST_TRANSFER 0
#define NIOS2_DMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define NIOS2_DMA_CHAIN_WRITEBACK_DATA_WIDTH 32
#define NIOS2_DMA_COMMAND_FIFO_DATA_WIDTH 104
#define NIOS2_DMA_CONTROL_DATA_WIDTH 8
#define NIOS2_DMA_CONTROL_SLAVE_ADDRESS_WIDTH 0x4
#define NIOS2_DMA_CONTROL_SLAVE_DATA_WIDTH 32
#define NIOS2_DMA_DESCRIPTOR_READ_BURST 0
#define NIOS2_DMA_DESC_DATA_WIDTH 32
#define NIOS2_DMA_HAS_READ_BLOCK 1
#define NIOS2_DMA_HAS_WRITE_BLOCK 1
#define NIOS2_DMA_IN_ERROR_WIDTH 0
#define NIOS2_DMA_IRQ 6
#define NIOS2_DMA_IRQ_INTERRUPT_CONTROLLER_ID 0
#define NIOS2_DMA_NAME "/dev/nios2_dma"
#define NIOS2_DMA_OUT_ERROR_WIDTH 0
#define NIOS2_DMA_READ_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_READ_BURSTCOUNT_WIDTH 4
#define NIOS2_DMA_SPAN 64
#define NIOS2_DMA_STATUS_TOKEN_DATA_WIDTH 24
#define NIOS2_DMA_STREAM_DATA_WIDTH 32
#define NIOS2_DMA_TYPE "altera_avalon_sgdma"
#define NIOS2_DMA_UNALIGNED_TRANSFER 1
#define NIOS2_DMA_WRITE_BLOCK_DATA_WIDTH 32
#define NIOS2_DMA_WRITE_BURSTCOUNT_WIDTH 4


/*
 * nios2_jtag_uart configuration
 *
 */

#define ALT_MODULE_CLASS_nios2_jtag_uart altera_avalon_jtag_uart
#define NIOS2_JTAG_UART_BASE 0x9b60
#define NIOS2_JTAG_UART_IRQ 0
#define NIOS2_JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define NIOS2_JTAG_UART_NAME "/dev/nios2_jtag_uart"
#define NIOS2_JTAG_UART_READ_DEPTH 64
#define NIOS2_JTAG_UART_READ_THRESHOLD 8
#define NIOS2_JTAG_UART_SPAN 8
#define NIOS2_JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define NIOS2_JTAG_UART_WRITE_DEPTH 64
#define NIOS2_JTAG_UART_WRITE_THRESHOLD 8


/*
 * nios2_jtag_uart configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_BASE 0x9b60
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_IRQ -1
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_NAME "/dev/nios2_jtag_uart"
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_READ_DEPTH 64
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_READ_THRESHOLD 8
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_SPAN 8
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_WRITE_DEPTH 64
#define NIOS2_DMA_M_READ_NIOS2_JTAG_UART_WRITE_THRESHOLD 8


/*
 * nios2_jtag_uart configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_BASE 0x9b60
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_IRQ -1
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_NAME "/dev/nios2_jtag_uart"
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_READ_DEPTH 64
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_READ_THRESHOLD 8
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_SPAN 8
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_WRITE_DEPTH 64
#define NIOS2_DMA_M_WRITE_NIOS2_JTAG_UART_WRITE_THRESHOLD 8


/*
 * nios2_onchip_mem configuration
 *
 */

#define ALT_MODULE_CLASS_nios2_onchip_mem altera_avalon_onchip_memory2
#define NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by eth0_rx_dma_m_write
 *
 */

#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_BASE 0x40000
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ -1
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SPAN 262144
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by eth0_tx_dma_m_read
 *
 */

#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_BASE 0x40000
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ -1
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SPAN 262144
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by eth1_rx_dma_m_write
 *
 */

#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_BASE 0x40000
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ -1
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SPAN 262144
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by eth1_tx_dma_m_read
 *
 */

#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_BASE 0x40000
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ -1
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SPAN 262144
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_read as viewed by eth0_rx_dma_m_write
 *
 */

#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_read as viewed by eth0_tx_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_read as viewed by eth1_rx_dma_m_write
 *
 */

#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_read as viewed by eth1_tx_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_write as viewed by eth0_rx_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_ETH0_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_write as viewed by eth0_tx_dma_m_read
 *
 */

#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_ETH0_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_write as viewed by eth1_rx_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_ETH1_RX_DMA_M_WRITE_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_onchip_mem configuration as viewed by nios2_dma_m_write as viewed by eth1_tx_dma_m_read
 *
 */

#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_BASE 0x40000
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_CONTENTS_FILE "ECE385_nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ -1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NAME "/dev/nios2_onchip_mem"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SINGLE_CLOCK_OP 1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SIZE_VALUE 262144
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_SPAN 262144
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_ETH1_TX_DMA_M_READ_NIOS2_ONCHIP_MEM_WRITABLE 1


/*
 * nios2_pll configuration
 *
 */

#define ALT_MODULE_CLASS_nios2_pll altpll
#define NIOS2_PLL_BASE 0x9b40
#define NIOS2_PLL_IRQ -1
#define NIOS2_PLL_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_PLL_NAME "/dev/nios2_pll"
#define NIOS2_PLL_SPAN 16
#define NIOS2_PLL_TYPE "altpll"


/*
 * nios2_pll configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_NIOS2_PLL_BASE 0x9b40
#define NIOS2_DMA_M_READ_NIOS2_PLL_IRQ -1
#define NIOS2_DMA_M_READ_NIOS2_PLL_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_NIOS2_PLL_NAME "/dev/nios2_pll"
#define NIOS2_DMA_M_READ_NIOS2_PLL_SPAN 16
#define NIOS2_DMA_M_READ_NIOS2_PLL_TYPE "altpll"


/*
 * nios2_pll configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_NIOS2_PLL_BASE 0x9b40
#define NIOS2_DMA_M_WRITE_NIOS2_PLL_IRQ -1
#define NIOS2_DMA_M_WRITE_NIOS2_PLL_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_NIOS2_PLL_NAME "/dev/nios2_pll"
#define NIOS2_DMA_M_WRITE_NIOS2_PLL_SPAN 16
#define NIOS2_DMA_M_WRITE_NIOS2_PLL_TYPE "altpll"


/*
 * nios2_sysid configuration
 *
 */

#define ALT_MODULE_CLASS_nios2_sysid altera_avalon_sysid_qsys
#define NIOS2_SYSID_BASE 0x9b58
#define NIOS2_SYSID_ID 0
#define NIOS2_SYSID_IRQ -1
#define NIOS2_SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_SYSID_NAME "/dev/nios2_sysid"
#define NIOS2_SYSID_SPAN 8
#define NIOS2_SYSID_TIMESTAMP 1559640077
#define NIOS2_SYSID_TYPE "altera_avalon_sysid_qsys"


/*
 * nios2_sysid configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_NIOS2_SYSID_BASE 0x9b58
#define NIOS2_DMA_M_READ_NIOS2_SYSID_ID 0
#define NIOS2_DMA_M_READ_NIOS2_SYSID_IRQ -1
#define NIOS2_DMA_M_READ_NIOS2_SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_NIOS2_SYSID_NAME "/dev/nios2_sysid"
#define NIOS2_DMA_M_READ_NIOS2_SYSID_SPAN 8
#define NIOS2_DMA_M_READ_NIOS2_SYSID_TIMESTAMP 1559640077
#define NIOS2_DMA_M_READ_NIOS2_SYSID_TYPE "altera_avalon_sysid_qsys"


/*
 * nios2_timer configuration
 *
 */

#define ALT_MODULE_CLASS_nios2_timer altera_avalon_timer
#define NIOS2_TIMER_ALWAYS_RUN 1
#define NIOS2_TIMER_BASE 0x9aa0
#define NIOS2_TIMER_COUNTER_SIZE 32
#define NIOS2_TIMER_FIXED_PERIOD 1
#define NIOS2_TIMER_FREQ 50000000
#define NIOS2_TIMER_IRQ 1
#define NIOS2_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define NIOS2_TIMER_LOAD_VALUE 49999
#define NIOS2_TIMER_MULT 0.001
#define NIOS2_TIMER_NAME "/dev/nios2_timer"
#define NIOS2_TIMER_PERIOD 1
#define NIOS2_TIMER_PERIOD_UNITS "ms"
#define NIOS2_TIMER_RESET_OUTPUT 0
#define NIOS2_TIMER_SNAPSHOT 0
#define NIOS2_TIMER_SPAN 32
#define NIOS2_TIMER_TICKS_PER_SEC 1000
#define NIOS2_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define NIOS2_TIMER_TYPE "altera_avalon_timer"


/*
 * nios2_timer configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_NIOS2_TIMER_ALWAYS_RUN 1
#define NIOS2_DMA_M_READ_NIOS2_TIMER_BASE 0x9aa0
#define NIOS2_DMA_M_READ_NIOS2_TIMER_COUNTER_SIZE 32
#define NIOS2_DMA_M_READ_NIOS2_TIMER_FIXED_PERIOD 1
#define NIOS2_DMA_M_READ_NIOS2_TIMER_FREQ 50000000
#define NIOS2_DMA_M_READ_NIOS2_TIMER_IRQ -1
#define NIOS2_DMA_M_READ_NIOS2_TIMER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_NIOS2_TIMER_LOAD_VALUE 49999
#define NIOS2_DMA_M_READ_NIOS2_TIMER_MULT 0.001
#define NIOS2_DMA_M_READ_NIOS2_TIMER_NAME "/dev/nios2_timer"
#define NIOS2_DMA_M_READ_NIOS2_TIMER_PERIOD 1
#define NIOS2_DMA_M_READ_NIOS2_TIMER_PERIOD_UNITS "ms"
#define NIOS2_DMA_M_READ_NIOS2_TIMER_RESET_OUTPUT 0
#define NIOS2_DMA_M_READ_NIOS2_TIMER_SNAPSHOT 0
#define NIOS2_DMA_M_READ_NIOS2_TIMER_SPAN 32
#define NIOS2_DMA_M_READ_NIOS2_TIMER_TICKS_PER_SEC 1000
#define NIOS2_DMA_M_READ_NIOS2_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define NIOS2_DMA_M_READ_NIOS2_TIMER_TYPE "altera_avalon_timer"


/*
 * nios2_timer configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_ALWAYS_RUN 1
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_BASE 0x9aa0
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_COUNTER_SIZE 32
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_FIXED_PERIOD 1
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_FREQ 50000000
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_IRQ -1
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_LOAD_VALUE 49999
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_MULT 0.001
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_NAME "/dev/nios2_timer"
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_PERIOD 1
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_PERIOD_UNITS "ms"
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_RESET_OUTPUT 0
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_SNAPSHOT 0
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_SPAN 32
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_TICKS_PER_SEC 1000
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define NIOS2_DMA_M_WRITE_NIOS2_TIMER_TYPE "altera_avalon_timer"


/*
 * sdram configuration
 *
 */

#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller
#define SDRAM_BASE 0x8000000
#define SDRAM_CAS_LATENCY 2
#define SDRAM_CONTENTS_INFO
#define SDRAM_INIT_NOP_DELAY 0.0
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_IRQ -1
#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_NAME "/dev/sdram"
#define SDRAM_POWERUP_DELAY 200.0
#define SDRAM_REFRESH_PERIOD 10.0
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SDRAM_ADDR_WIDTH 0x19
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_SDRAM_COL_WIDTH 10
#define SDRAM_SDRAM_DATA_WIDTH 32
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_ROW_WIDTH 13
#define SDRAM_SHARED_DATA 0
#define SDRAM_SIM_MODEL_BASE 0
#define SDRAM_SPAN 134217728
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_T_AC 5.5
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 15.0
#define SDRAM_T_RFC 60.0
#define SDRAM_T_RP 15.0
#define SDRAM_T_WR 14.0


/*
 * sdram configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_SDRAM_BASE 0x8000000
#define NIOS2_DMA_M_READ_SDRAM_CAS_LATENCY 2
#define NIOS2_DMA_M_READ_SDRAM_CONTENTS_INFO
#define NIOS2_DMA_M_READ_SDRAM_INIT_NOP_DELAY 0.0
#define NIOS2_DMA_M_READ_SDRAM_INIT_REFRESH_COMMANDS 2
#define NIOS2_DMA_M_READ_SDRAM_IRQ -1
#define NIOS2_DMA_M_READ_SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_SDRAM_IS_INITIALIZED 1
#define NIOS2_DMA_M_READ_SDRAM_NAME "/dev/sdram"
#define NIOS2_DMA_M_READ_SDRAM_POWERUP_DELAY 200.0
#define NIOS2_DMA_M_READ_SDRAM_REFRESH_PERIOD 10.0
#define NIOS2_DMA_M_READ_SDRAM_REGISTER_DATA_IN 1
#define NIOS2_DMA_M_READ_SDRAM_SDRAM_ADDR_WIDTH 0x19
#define NIOS2_DMA_M_READ_SDRAM_SDRAM_BANK_WIDTH 2
#define NIOS2_DMA_M_READ_SDRAM_SDRAM_COL_WIDTH 10
#define NIOS2_DMA_M_READ_SDRAM_SDRAM_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_SDRAM_SDRAM_NUM_BANKS 4
#define NIOS2_DMA_M_READ_SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define NIOS2_DMA_M_READ_SDRAM_SDRAM_ROW_WIDTH 13
#define NIOS2_DMA_M_READ_SDRAM_SHARED_DATA 0
#define NIOS2_DMA_M_READ_SDRAM_SIM_MODEL_BASE 0
#define NIOS2_DMA_M_READ_SDRAM_SPAN 134217728
#define NIOS2_DMA_M_READ_SDRAM_STARVATION_INDICATOR 0
#define NIOS2_DMA_M_READ_SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define NIOS2_DMA_M_READ_SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define NIOS2_DMA_M_READ_SDRAM_T_AC 5.5
#define NIOS2_DMA_M_READ_SDRAM_T_MRD 3
#define NIOS2_DMA_M_READ_SDRAM_T_RCD 15.0
#define NIOS2_DMA_M_READ_SDRAM_T_RFC 60.0
#define NIOS2_DMA_M_READ_SDRAM_T_RP 15.0
#define NIOS2_DMA_M_READ_SDRAM_T_WR 14.0


/*
 * sdram configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_SDRAM_BASE 0x8000000
#define NIOS2_DMA_M_WRITE_SDRAM_CAS_LATENCY 2
#define NIOS2_DMA_M_WRITE_SDRAM_CONTENTS_INFO
#define NIOS2_DMA_M_WRITE_SDRAM_INIT_NOP_DELAY 0.0
#define NIOS2_DMA_M_WRITE_SDRAM_INIT_REFRESH_COMMANDS 2
#define NIOS2_DMA_M_WRITE_SDRAM_IRQ -1
#define NIOS2_DMA_M_WRITE_SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_SDRAM_IS_INITIALIZED 1
#define NIOS2_DMA_M_WRITE_SDRAM_NAME "/dev/sdram"
#define NIOS2_DMA_M_WRITE_SDRAM_POWERUP_DELAY 200.0
#define NIOS2_DMA_M_WRITE_SDRAM_REFRESH_PERIOD 10.0
#define NIOS2_DMA_M_WRITE_SDRAM_REGISTER_DATA_IN 1
#define NIOS2_DMA_M_WRITE_SDRAM_SDRAM_ADDR_WIDTH 0x19
#define NIOS2_DMA_M_WRITE_SDRAM_SDRAM_BANK_WIDTH 2
#define NIOS2_DMA_M_WRITE_SDRAM_SDRAM_COL_WIDTH 10
#define NIOS2_DMA_M_WRITE_SDRAM_SDRAM_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_SDRAM_SDRAM_NUM_BANKS 4
#define NIOS2_DMA_M_WRITE_SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define NIOS2_DMA_M_WRITE_SDRAM_SDRAM_ROW_WIDTH 13
#define NIOS2_DMA_M_WRITE_SDRAM_SHARED_DATA 0
#define NIOS2_DMA_M_WRITE_SDRAM_SIM_MODEL_BASE 0
#define NIOS2_DMA_M_WRITE_SDRAM_SPAN 134217728
#define NIOS2_DMA_M_WRITE_SDRAM_STARVATION_INDICATOR 0
#define NIOS2_DMA_M_WRITE_SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define NIOS2_DMA_M_WRITE_SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define NIOS2_DMA_M_WRITE_SDRAM_T_AC 5.5
#define NIOS2_DMA_M_WRITE_SDRAM_T_MRD 3
#define NIOS2_DMA_M_WRITE_SDRAM_T_RCD 15.0
#define NIOS2_DMA_M_WRITE_SDRAM_T_RFC 60.0
#define NIOS2_DMA_M_WRITE_SDRAM_T_RP 15.0
#define NIOS2_DMA_M_WRITE_SDRAM_T_WR 14.0


/*
 * sram_multiplexer configuration
 *
 */

#define ALT_MODULE_CLASS_sram_multiplexer sram_multiplexer
#define SRAM_MULTIPLEXER_BASE 0x400000
#define SRAM_MULTIPLEXER_IRQ -1
#define SRAM_MULTIPLEXER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SRAM_MULTIPLEXER_NAME "/dev/sram_multiplexer"
#define SRAM_MULTIPLEXER_SPAN 2097152
#define SRAM_MULTIPLEXER_TYPE "sram_multiplexer"


/*
 * sram_multiplexer configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_SRAM_MULTIPLEXER_BASE 0x400000
#define NIOS2_DMA_M_READ_SRAM_MULTIPLEXER_IRQ -1
#define NIOS2_DMA_M_READ_SRAM_MULTIPLEXER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_SRAM_MULTIPLEXER_NAME "/dev/sram_multiplexer"
#define NIOS2_DMA_M_READ_SRAM_MULTIPLEXER_SPAN 2097152
#define NIOS2_DMA_M_READ_SRAM_MULTIPLEXER_TYPE "sram_multiplexer"


/*
 * sram_multiplexer configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_SRAM_MULTIPLEXER_BASE 0x400000
#define NIOS2_DMA_M_WRITE_SRAM_MULTIPLEXER_IRQ -1
#define NIOS2_DMA_M_WRITE_SRAM_MULTIPLEXER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_SRAM_MULTIPLEXER_NAME "/dev/sram_multiplexer"
#define NIOS2_DMA_M_WRITE_SRAM_MULTIPLEXER_SPAN 2097152
#define NIOS2_DMA_M_WRITE_SRAM_MULTIPLEXER_TYPE "sram_multiplexer"


/*
 * usb_keycode configuration
 *
 */

#define ALT_MODULE_CLASS_usb_keycode altera_avalon_onchip_memory2
#define USB_KEYCODE_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define USB_KEYCODE_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define USB_KEYCODE_BASE 0x9000
#define USB_KEYCODE_CONTENTS_INFO ""
#define USB_KEYCODE_DUAL_PORT 1
#define USB_KEYCODE_GUI_RAM_BLOCK_TYPE "AUTO"
#define USB_KEYCODE_INIT_CONTENTS_FILE "ECE385_usb_keycode"
#define USB_KEYCODE_INIT_MEM_CONTENT 1
#define USB_KEYCODE_INSTANCE_ID "NONE"
#define USB_KEYCODE_IRQ -1
#define USB_KEYCODE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define USB_KEYCODE_NAME "/dev/usb_keycode"
#define USB_KEYCODE_NON_DEFAULT_INIT_FILE_ENABLED 0
#define USB_KEYCODE_RAM_BLOCK_TYPE "AUTO"
#define USB_KEYCODE_READ_DURING_WRITE_MODE "OLD_DATA"
#define USB_KEYCODE_SINGLE_CLOCK_OP 0
#define USB_KEYCODE_SIZE_MULTIPLE 1
#define USB_KEYCODE_SIZE_VALUE 1024
#define USB_KEYCODE_SPAN 1024
#define USB_KEYCODE_TYPE "altera_avalon_onchip_memory2"
#define USB_KEYCODE_WRITABLE 1


/*
 * usb_keycode configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_USB_KEYCODE_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_USB_KEYCODE_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_USB_KEYCODE_BASE 0x9000
#define NIOS2_DMA_M_READ_USB_KEYCODE_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_USB_KEYCODE_DUAL_PORT 1
#define NIOS2_DMA_M_READ_USB_KEYCODE_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_USB_KEYCODE_INIT_CONTENTS_FILE "ECE385_usb_keycode"
#define NIOS2_DMA_M_READ_USB_KEYCODE_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_USB_KEYCODE_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_USB_KEYCODE_IRQ -1
#define NIOS2_DMA_M_READ_USB_KEYCODE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_USB_KEYCODE_NAME "/dev/usb_keycode"
#define NIOS2_DMA_M_READ_USB_KEYCODE_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_USB_KEYCODE_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_USB_KEYCODE_READ_DURING_WRITE_MODE "OLD_DATA"
#define NIOS2_DMA_M_READ_USB_KEYCODE_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_USB_KEYCODE_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_USB_KEYCODE_SIZE_VALUE 1024
#define NIOS2_DMA_M_READ_USB_KEYCODE_SPAN 1024
#define NIOS2_DMA_M_READ_USB_KEYCODE_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_USB_KEYCODE_WRITABLE 1


/*
 * usb_keycode configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_USB_KEYCODE_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_BASE 0x9000
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_INIT_CONTENTS_FILE "ECE385_usb_keycode"
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_IRQ -1
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_NAME "/dev/usb_keycode"
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_READ_DURING_WRITE_MODE "OLD_DATA"
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_SIZE_VALUE 1024
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_SPAN 1024
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_USB_KEYCODE_WRITABLE 1


/*
 * vga_background_offset configuration
 *
 */

#define ALT_MODULE_CLASS_vga_background_offset altera_avalon_pio
#define VGA_BACKGROUND_OFFSET_BASE 0x9b00
#define VGA_BACKGROUND_OFFSET_BIT_CLEARING_EDGE_REGISTER 0
#define VGA_BACKGROUND_OFFSET_BIT_MODIFYING_OUTPUT_REGISTER 0
#define VGA_BACKGROUND_OFFSET_CAPTURE 0
#define VGA_BACKGROUND_OFFSET_DATA_WIDTH 32
#define VGA_BACKGROUND_OFFSET_DO_TEST_BENCH_WIRING 0
#define VGA_BACKGROUND_OFFSET_DRIVEN_SIM_VALUE 0
#define VGA_BACKGROUND_OFFSET_EDGE_TYPE "NONE"
#define VGA_BACKGROUND_OFFSET_FREQ 50000000
#define VGA_BACKGROUND_OFFSET_HAS_IN 0
#define VGA_BACKGROUND_OFFSET_HAS_OUT 1
#define VGA_BACKGROUND_OFFSET_HAS_TRI 0
#define VGA_BACKGROUND_OFFSET_IRQ -1
#define VGA_BACKGROUND_OFFSET_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_BACKGROUND_OFFSET_IRQ_TYPE "NONE"
#define VGA_BACKGROUND_OFFSET_NAME "/dev/vga_background_offset"
#define VGA_BACKGROUND_OFFSET_RESET_VALUE 0
#define VGA_BACKGROUND_OFFSET_SPAN 16
#define VGA_BACKGROUND_OFFSET_TYPE "altera_avalon_pio"


/*
 * vga_background_offset configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_BASE 0x9b00
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_CAPTURE 0
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_DATA_WIDTH 32
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_FREQ 50000000
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_HAS_IN 0
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_HAS_OUT 1
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_HAS_TRI 0
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_IRQ -1
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_NAME "/dev/vga_background_offset"
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_RESET_VALUE 0
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_SPAN 16
#define NIOS2_DMA_M_READ_VGA_BACKGROUND_OFFSET_TYPE "altera_avalon_pio"


/*
 * vga_background_offset configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_BASE 0x9b00
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_BIT_CLEARING_EDGE_REGISTER 0
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_BIT_MODIFYING_OUTPUT_REGISTER 0
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_CAPTURE 0
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_DATA_WIDTH 32
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_DO_TEST_BENCH_WIRING 0
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_DRIVEN_SIM_VALUE 0
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_EDGE_TYPE "NONE"
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_FREQ 50000000
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_HAS_IN 0
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_HAS_OUT 1
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_HAS_TRI 0
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_IRQ_TYPE "NONE"
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_NAME "/dev/vga_background_offset"
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_RESET_VALUE 0
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_SPAN 16
#define NIOS2_DMA_M_WRITE_VGA_BACKGROUND_OFFSET_TYPE "altera_avalon_pio"


/*
 * vga_sprite_0 configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_0 altera_avalon_onchip_memory2
#define VGA_SPRITE_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define VGA_SPRITE_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define VGA_SPRITE_0_BASE 0x7000
#define VGA_SPRITE_0_CONTENTS_INFO ""
#define VGA_SPRITE_0_DUAL_PORT 1
#define VGA_SPRITE_0_GUI_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_0_INIT_CONTENTS_FILE "ECE385_vga_sprite_0"
#define VGA_SPRITE_0_INIT_MEM_CONTENT 1
#define VGA_SPRITE_0_INSTANCE_ID "NONE"
#define VGA_SPRITE_0_IRQ -1
#define VGA_SPRITE_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_0_NAME "/dev/vga_sprite_0"
#define VGA_SPRITE_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define VGA_SPRITE_0_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define VGA_SPRITE_0_SINGLE_CLOCK_OP 0
#define VGA_SPRITE_0_SIZE_MULTIPLE 1
#define VGA_SPRITE_0_SIZE_VALUE 4096
#define VGA_SPRITE_0_SPAN 4096
#define VGA_SPRITE_0_TYPE "altera_avalon_onchip_memory2"
#define VGA_SPRITE_0_WRITABLE 1


/*
 * vga_sprite_0 configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_BASE 0x7000
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_DUAL_PORT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_INIT_CONTENTS_FILE "ECE385_vga_sprite_0"
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_NAME "/dev/vga_sprite_0"
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_SIZE_VALUE 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_SPAN 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_0_WRITABLE 1


/*
 * vga_sprite_0 configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_BASE 0x7000
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_INIT_CONTENTS_FILE "ECE385_vga_sprite_0"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_NAME "/dev/vga_sprite_0"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_SIZE_VALUE 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_SPAN 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_0_WRITABLE 1


/*
 * vga_sprite_1 configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_1 altera_avalon_onchip_memory2
#define VGA_SPRITE_1_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define VGA_SPRITE_1_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define VGA_SPRITE_1_BASE 0x6000
#define VGA_SPRITE_1_CONTENTS_INFO ""
#define VGA_SPRITE_1_DUAL_PORT 1
#define VGA_SPRITE_1_GUI_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_1_INIT_CONTENTS_FILE "ECE385_vga_sprite_1"
#define VGA_SPRITE_1_INIT_MEM_CONTENT 1
#define VGA_SPRITE_1_INSTANCE_ID "NONE"
#define VGA_SPRITE_1_IRQ -1
#define VGA_SPRITE_1_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_1_NAME "/dev/vga_sprite_1"
#define VGA_SPRITE_1_NON_DEFAULT_INIT_FILE_ENABLED 0
#define VGA_SPRITE_1_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_1_READ_DURING_WRITE_MODE "DONT_CARE"
#define VGA_SPRITE_1_SINGLE_CLOCK_OP 0
#define VGA_SPRITE_1_SIZE_MULTIPLE 1
#define VGA_SPRITE_1_SIZE_VALUE 4096
#define VGA_SPRITE_1_SPAN 4096
#define VGA_SPRITE_1_TYPE "altera_avalon_onchip_memory2"
#define VGA_SPRITE_1_WRITABLE 1


/*
 * vga_sprite_1 configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_1_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_BASE 0x6000
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_DUAL_PORT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_INIT_CONTENTS_FILE "ECE385_vga_sprite_1"
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_NAME "/dev/vga_sprite_1"
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_SIZE_VALUE 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_SPAN 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_1_WRITABLE 1


/*
 * vga_sprite_1 configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_BASE 0x6000
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_INIT_CONTENTS_FILE "ECE385_vga_sprite_1"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_NAME "/dev/vga_sprite_1"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_SIZE_VALUE 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_SPAN 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_1_WRITABLE 1


/*
 * vga_sprite_2 configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_2 altera_avalon_onchip_memory2
#define VGA_SPRITE_2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define VGA_SPRITE_2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define VGA_SPRITE_2_BASE 0x5000
#define VGA_SPRITE_2_CONTENTS_INFO ""
#define VGA_SPRITE_2_DUAL_PORT 1
#define VGA_SPRITE_2_GUI_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_2_INIT_CONTENTS_FILE "ECE385_vga_sprite_2"
#define VGA_SPRITE_2_INIT_MEM_CONTENT 1
#define VGA_SPRITE_2_INSTANCE_ID "NONE"
#define VGA_SPRITE_2_IRQ -1
#define VGA_SPRITE_2_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_2_NAME "/dev/vga_sprite_2"
#define VGA_SPRITE_2_NON_DEFAULT_INIT_FILE_ENABLED 0
#define VGA_SPRITE_2_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_2_READ_DURING_WRITE_MODE "DONT_CARE"
#define VGA_SPRITE_2_SINGLE_CLOCK_OP 0
#define VGA_SPRITE_2_SIZE_MULTIPLE 1
#define VGA_SPRITE_2_SIZE_VALUE 4096
#define VGA_SPRITE_2_SPAN 4096
#define VGA_SPRITE_2_TYPE "altera_avalon_onchip_memory2"
#define VGA_SPRITE_2_WRITABLE 1


/*
 * vga_sprite_2 configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_BASE 0x5000
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_DUAL_PORT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_INIT_CONTENTS_FILE "ECE385_vga_sprite_2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_NAME "/dev/vga_sprite_2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_SIZE_VALUE 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_SPAN 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_2_WRITABLE 1


/*
 * vga_sprite_2 configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_BASE 0x5000
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_INIT_CONTENTS_FILE "ECE385_vga_sprite_2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_NAME "/dev/vga_sprite_2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_SIZE_VALUE 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_SPAN 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_2_WRITABLE 1


/*
 * vga_sprite_3 configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_3 altera_avalon_onchip_memory2
#define VGA_SPRITE_3_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define VGA_SPRITE_3_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define VGA_SPRITE_3_BASE 0x4000
#define VGA_SPRITE_3_CONTENTS_INFO ""
#define VGA_SPRITE_3_DUAL_PORT 1
#define VGA_SPRITE_3_GUI_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_3_INIT_CONTENTS_FILE "ECE385_vga_sprite_3"
#define VGA_SPRITE_3_INIT_MEM_CONTENT 1
#define VGA_SPRITE_3_INSTANCE_ID "NONE"
#define VGA_SPRITE_3_IRQ -1
#define VGA_SPRITE_3_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_3_NAME "/dev/vga_sprite_3"
#define VGA_SPRITE_3_NON_DEFAULT_INIT_FILE_ENABLED 0
#define VGA_SPRITE_3_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_3_READ_DURING_WRITE_MODE "DONT_CARE"
#define VGA_SPRITE_3_SINGLE_CLOCK_OP 0
#define VGA_SPRITE_3_SIZE_MULTIPLE 1
#define VGA_SPRITE_3_SIZE_VALUE 4096
#define VGA_SPRITE_3_SPAN 4096
#define VGA_SPRITE_3_TYPE "altera_avalon_onchip_memory2"
#define VGA_SPRITE_3_WRITABLE 1


/*
 * vga_sprite_3 configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_3_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_BASE 0x4000
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_DUAL_PORT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_INIT_CONTENTS_FILE "ECE385_vga_sprite_3"
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_NAME "/dev/vga_sprite_3"
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_SIZE_VALUE 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_SPAN 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_3_WRITABLE 1


/*
 * vga_sprite_3 configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_BASE 0x4000
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_INIT_CONTENTS_FILE "ECE385_vga_sprite_3"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_NAME "/dev/vga_sprite_3"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_SIZE_VALUE 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_SPAN 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_3_WRITABLE 1


/*
 * vga_sprite_4 configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_4 altera_avalon_onchip_memory2
#define VGA_SPRITE_4_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define VGA_SPRITE_4_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define VGA_SPRITE_4_BASE 0x3000
#define VGA_SPRITE_4_CONTENTS_INFO ""
#define VGA_SPRITE_4_DUAL_PORT 1
#define VGA_SPRITE_4_GUI_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_4_INIT_CONTENTS_FILE "ECE385_vga_sprite_4"
#define VGA_SPRITE_4_INIT_MEM_CONTENT 1
#define VGA_SPRITE_4_INSTANCE_ID "NONE"
#define VGA_SPRITE_4_IRQ -1
#define VGA_SPRITE_4_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_4_NAME "/dev/vga_sprite_4"
#define VGA_SPRITE_4_NON_DEFAULT_INIT_FILE_ENABLED 0
#define VGA_SPRITE_4_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_4_READ_DURING_WRITE_MODE "DONT_CARE"
#define VGA_SPRITE_4_SINGLE_CLOCK_OP 0
#define VGA_SPRITE_4_SIZE_MULTIPLE 1
#define VGA_SPRITE_4_SIZE_VALUE 4096
#define VGA_SPRITE_4_SPAN 4096
#define VGA_SPRITE_4_TYPE "altera_avalon_onchip_memory2"
#define VGA_SPRITE_4_WRITABLE 1


/*
 * vga_sprite_4 configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_4_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_BASE 0x3000
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_DUAL_PORT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_INIT_CONTENTS_FILE "ECE385_vga_sprite_4"
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_NAME "/dev/vga_sprite_4"
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_SIZE_VALUE 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_SPAN 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_4_WRITABLE 1


/*
 * vga_sprite_4 configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_BASE 0x3000
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_INIT_CONTENTS_FILE "ECE385_vga_sprite_4"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_NAME "/dev/vga_sprite_4"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_SIZE_VALUE 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_SPAN 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_4_WRITABLE 1


/*
 * vga_sprite_5 configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_5 altera_avalon_onchip_memory2
#define VGA_SPRITE_5_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define VGA_SPRITE_5_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define VGA_SPRITE_5_BASE 0x2000
#define VGA_SPRITE_5_CONTENTS_INFO ""
#define VGA_SPRITE_5_DUAL_PORT 1
#define VGA_SPRITE_5_GUI_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_5_INIT_CONTENTS_FILE "ECE385_vga_sprite_5"
#define VGA_SPRITE_5_INIT_MEM_CONTENT 1
#define VGA_SPRITE_5_INSTANCE_ID "NONE"
#define VGA_SPRITE_5_IRQ -1
#define VGA_SPRITE_5_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_5_NAME "/dev/vga_sprite_5"
#define VGA_SPRITE_5_NON_DEFAULT_INIT_FILE_ENABLED 0
#define VGA_SPRITE_5_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_5_READ_DURING_WRITE_MODE "DONT_CARE"
#define VGA_SPRITE_5_SINGLE_CLOCK_OP 0
#define VGA_SPRITE_5_SIZE_MULTIPLE 1
#define VGA_SPRITE_5_SIZE_VALUE 4096
#define VGA_SPRITE_5_SPAN 4096
#define VGA_SPRITE_5_TYPE "altera_avalon_onchip_memory2"
#define VGA_SPRITE_5_WRITABLE 1


/*
 * vga_sprite_5 configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_5_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_BASE 0x2000
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_DUAL_PORT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_INIT_CONTENTS_FILE "ECE385_vga_sprite_5"
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_NAME "/dev/vga_sprite_5"
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_SIZE_VALUE 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_SPAN 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_5_WRITABLE 1


/*
 * vga_sprite_5 configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_BASE 0x2000
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_INIT_CONTENTS_FILE "ECE385_vga_sprite_5"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_NAME "/dev/vga_sprite_5"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_SIZE_VALUE 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_SPAN 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_5_WRITABLE 1


/*
 * vga_sprite_6 configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_6 altera_avalon_onchip_memory2
#define VGA_SPRITE_6_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define VGA_SPRITE_6_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define VGA_SPRITE_6_BASE 0x1000
#define VGA_SPRITE_6_CONTENTS_INFO ""
#define VGA_SPRITE_6_DUAL_PORT 1
#define VGA_SPRITE_6_GUI_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_6_INIT_CONTENTS_FILE "ECE385_vga_sprite_6"
#define VGA_SPRITE_6_INIT_MEM_CONTENT 1
#define VGA_SPRITE_6_INSTANCE_ID "NONE"
#define VGA_SPRITE_6_IRQ -1
#define VGA_SPRITE_6_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_6_NAME "/dev/vga_sprite_6"
#define VGA_SPRITE_6_NON_DEFAULT_INIT_FILE_ENABLED 0
#define VGA_SPRITE_6_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_6_READ_DURING_WRITE_MODE "DONT_CARE"
#define VGA_SPRITE_6_SINGLE_CLOCK_OP 0
#define VGA_SPRITE_6_SIZE_MULTIPLE 1
#define VGA_SPRITE_6_SIZE_VALUE 4096
#define VGA_SPRITE_6_SPAN 4096
#define VGA_SPRITE_6_TYPE "altera_avalon_onchip_memory2"
#define VGA_SPRITE_6_WRITABLE 1


/*
 * vga_sprite_6 configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_6_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_BASE 0x1000
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_DUAL_PORT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_INIT_CONTENTS_FILE "ECE385_vga_sprite_6"
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_NAME "/dev/vga_sprite_6"
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_SIZE_VALUE 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_SPAN 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_6_WRITABLE 1


/*
 * vga_sprite_6 configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_BASE 0x1000
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_INIT_CONTENTS_FILE "ECE385_vga_sprite_6"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_NAME "/dev/vga_sprite_6"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_SIZE_VALUE 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_SPAN 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_6_WRITABLE 1


/*
 * vga_sprite_7 configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_7 altera_avalon_onchip_memory2
#define VGA_SPRITE_7_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define VGA_SPRITE_7_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define VGA_SPRITE_7_BASE 0x0
#define VGA_SPRITE_7_CONTENTS_INFO ""
#define VGA_SPRITE_7_DUAL_PORT 1
#define VGA_SPRITE_7_GUI_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_7_INIT_CONTENTS_FILE "ECE385_vga_sprite_7"
#define VGA_SPRITE_7_INIT_MEM_CONTENT 1
#define VGA_SPRITE_7_INSTANCE_ID "NONE"
#define VGA_SPRITE_7_IRQ -1
#define VGA_SPRITE_7_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_7_NAME "/dev/vga_sprite_7"
#define VGA_SPRITE_7_NON_DEFAULT_INIT_FILE_ENABLED 0
#define VGA_SPRITE_7_RAM_BLOCK_TYPE "AUTO"
#define VGA_SPRITE_7_READ_DURING_WRITE_MODE "DONT_CARE"
#define VGA_SPRITE_7_SINGLE_CLOCK_OP 0
#define VGA_SPRITE_7_SIZE_MULTIPLE 1
#define VGA_SPRITE_7_SIZE_VALUE 4096
#define VGA_SPRITE_7_SPAN 4096
#define VGA_SPRITE_7_TYPE "altera_avalon_onchip_memory2"
#define VGA_SPRITE_7_WRITABLE 1


/*
 * vga_sprite_7 configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_7_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_BASE 0x0
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_CONTENTS_INFO ""
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_DUAL_PORT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_INIT_CONTENTS_FILE "ECE385_vga_sprite_7"
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_NAME "/dev/vga_sprite_7"
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_SIZE_VALUE 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_SPAN 4096
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_READ_VGA_SPRITE_7_WRITABLE 1


/*
 * vga_sprite_7 configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_BASE 0x0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_CONTENTS_INFO ""
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_DUAL_PORT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_GUI_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_INIT_CONTENTS_FILE "ECE385_vga_sprite_7"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_INIT_MEM_CONTENT 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_INSTANCE_ID "NONE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_NAME "/dev/vga_sprite_7"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_NON_DEFAULT_INIT_FILE_ENABLED 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_RAM_BLOCK_TYPE "AUTO"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_READ_DURING_WRITE_MODE "DONT_CARE"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_SINGLE_CLOCK_OP 0
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_SIZE_MULTIPLE 1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_SIZE_VALUE 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_SPAN 4096
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_TYPE "altera_avalon_onchip_memory2"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_7_WRITABLE 1


/*
 * vga_sprite_params configuration
 *
 */

#define ALT_MODULE_CLASS_vga_sprite_params avalon_mm_passthrough
#define VGA_SPRITE_PARAMS_BASE 0x9400
#define VGA_SPRITE_PARAMS_IRQ -1
#define VGA_SPRITE_PARAMS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_SPRITE_PARAMS_NAME "/dev/vga_sprite_params"
#define VGA_SPRITE_PARAMS_SPAN 1024
#define VGA_SPRITE_PARAMS_TYPE "avalon_mm_passthrough"


/*
 * vga_sprite_params configuration as viewed by nios2_dma_m_read
 *
 */

#define NIOS2_DMA_M_READ_VGA_SPRITE_PARAMS_BASE 0x9400
#define NIOS2_DMA_M_READ_VGA_SPRITE_PARAMS_IRQ -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_PARAMS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_READ_VGA_SPRITE_PARAMS_NAME "/dev/vga_sprite_params"
#define NIOS2_DMA_M_READ_VGA_SPRITE_PARAMS_SPAN 1024
#define NIOS2_DMA_M_READ_VGA_SPRITE_PARAMS_TYPE "avalon_mm_passthrough"


/*
 * vga_sprite_params configuration as viewed by nios2_dma_m_write
 *
 */

#define NIOS2_DMA_M_WRITE_VGA_SPRITE_PARAMS_BASE 0x9400
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_PARAMS_IRQ -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_PARAMS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_PARAMS_NAME "/dev/vga_sprite_params"
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_PARAMS_SPAN 1024
#define NIOS2_DMA_M_WRITE_VGA_SPRITE_PARAMS_TYPE "avalon_mm_passthrough"

#endif /* __SYSTEM_H_ */