71 lines
3.9 KiB
C
71 lines
3.9 KiB
C
/******************************************************************************
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* *
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* License Agreement *
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* *
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* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. *
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* All rights reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included in *
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* all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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* This agreement shall be governed in all respects by the laws of the State *
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* of California and by the laws of the United States of America. *
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* Altera does not recommend, suggest or require that this reference design *
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* file be used in conjunction or combination with any other product. *
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******************************************************************************/
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#ifndef ALTERA_MSGDMA_RESPONSE_REGS_H_
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#define ALTERA_MSGDMA_RESPONSE_REGS_H_
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#include "io.h"
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/*
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The response slave port only carries the actual bytes transferred,
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error, and early termination bits. Reading from the upper most byte
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of the 2nd register pops the response FIFO. For proper FIFO popping
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always read the actual bytes transferred followed by the error and early
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termination bits using 'little endian' accesses. If a big endian
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master accesses the response slave port make sure that address 0x7 is the
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last byte lane access as it's the one that pops the reponse FIFO.
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If you use a pre-fetching descriptor master in front of the dispatcher
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port then you do not need to access this response slave port.
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*/
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#define ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG 0x0
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#define ALTERA_MSGDMA_RESPONSE_ERRORS_REG 0x4
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/* bits making up the "errors" register */
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#define ALTERA_MSGDMA_RESPONSE_ERROR_MASK 0xFF
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#define ALTERA_MSGDMA_RESPONSE_ERROR_OFFSET 0
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#define ALTERA_MSGDMA_RESPONSE_EARLY_TERMINATION_MASK (1 << 8)
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#define ALTERA_MSGDMA_RESPONSE_EARLY_TERMINATION_OFFSET 8
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/* read macros for each 32 bit register */
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#define IORD_ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED(base) \
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IORD_32DIRECT(base, ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG)
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/* this read pops the response FIFO */
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#define IORD_ALTERA_MSGDMA_RESPONSE_ERRORS_REG(base) \
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IORD_32DIRECT(base, ALTERA_MSGDMA_RESPONSE_ERRORS_REG)
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#endif /*ALTERA_MSGDMA_RESPONSE_REGS_H_*/
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