176 lines
8.7 KiB
C
176 lines
8.7 KiB
C
/******************************************************************************
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* *
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* License Agreement *
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* *
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* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. *
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* All rights reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included in *
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* all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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* This agreement shall be governed in all respects by the laws of the State *
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* of California and by the laws of the United States of America. *
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* Altera does not recommend, suggest or require that this reference design *
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* file be used in conjunction or combination with any other product. *
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******************************************************************************/
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#ifndef ALTERA_MSGDMA_CSR_REGS_H_
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#define ALTERA_MSGDMA_CSR_REGS_H_
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#include "io.h"
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/*
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Enhanced features off:
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Bytes Access Type Description
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----- ----------- -----------
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0-3 R/Clr Status(1)
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4-7 R/W Control(2)
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8-12 R Descriptor Fill Level(write fill level[15:0], read
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fill level[15:0])
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13-15 R Response Fill Level[15:0]
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16-31 N/A <Reserved>
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Enhanced features on:
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Bytes Access Type Description
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----- ----------- -----------
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0-3 R/Clr Status(1)
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4-7 R/W Control(2)
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8-12 R Descriptor Fill Level (write fill level[15:0], read
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fill level[15:0])
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13-15 R Response Fill Level[15:0]
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16-20 R Sequence Number (write sequence number[15:0], read
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sequence number[15:0])
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21-31 N/A <Reserved>
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(1) Writing a '1' to the interrupt bit of the status register clears the
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interrupt bit (when applicable), all other bits are unaffected by writes.
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(2) Writing to the software reset bit will clear the entire register
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(as well as all the registers for the entire msgdma).
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Status Register:
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Bits Description
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---- -----------
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0 Busy
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1 Descriptor Buffer Empty
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2 Descriptor Buffer Full
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3 Response Buffer Empty
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4 Response Buffer Full
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5 Stop State
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6 Reset State
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7 Stopped on Error
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8 Stopped on Early Termination
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9 IRQ
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10-31 <Reserved>
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Control Register:
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Bits Description
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---- -----------
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0 Stop (will also be set if a stop on error/early termination
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condition occurs)
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1 Software Reset
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2 Stop on Error
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3 Stop on Early Termination
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4 Global Interrupt Enable Mask
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5 Stop dispatcher (stops the dispatcher from issuing more read/write
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commands)
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6-31 <Reserved>
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*/
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#define ALTERA_MSGDMA_CSR_STATUS_REG 0x0
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#define ALTERA_MSGDMA_CSR_CONTROL_REG 0x4
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#define ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL_REG 0x8
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#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_REG 0xC
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/* this register only exists when the enhanced features are enabled */
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#define ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER_REG 0x10
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/* masks for the status register bits */
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#define ALTERA_MSGDMA_CSR_BUSY_MASK 1
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#define ALTERA_MSGDMA_CSR_BUSY_OFFSET 0
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#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_EMPTY_MASK (1 << 1)
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#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_EMPTY_OFFSET 1
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#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK (1 << 2)
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#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_OFFSET 2
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#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_EMPTY_MASK (1 << 3)
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#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_EMPTY_OFFSET 3
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#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_FULL_MASK (1 << 4)
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#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_FULL_OFFSET 4
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#define ALTERA_MSGDMA_CSR_STOP_STATE_MASK (1 << 5)
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#define ALTERA_MSGDMA_CSR_STOP_STATE_OFFSET 5
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#define ALTERA_MSGDMA_CSR_RESET_STATE_MASK (1 << 6)
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#define ALTERA_MSGDMA_CSR_RESET_STATE_OFFSET 6
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#define ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK (1 << 7)
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#define ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_OFFSET 7
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#define ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_MASK (1 << 8)
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#define ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_OFFSET 8
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#define ALTERA_MSGDMA_CSR_IRQ_SET_MASK (1 << 9)
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#define ALTERA_MSGDMA_CSR_IRQ_SET_OFFSET 9
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/* masks for the control register bits */
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#define ALTERA_MSGDMA_CSR_STOP_MASK 1
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#define ALTERA_MSGDMA_CSR_STOP_OFFSET 0
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#define ALTERA_MSGDMA_CSR_RESET_MASK (1 << 1)
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#define ALTERA_MSGDMA_CSR_RESET_OFFSET 1
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#define ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK (1 << 2)
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#define ALTERA_MSGDMA_CSR_STOP_ON_ERROR_OFFSET 2
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#define ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_MASK (1 << 3)
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#define ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_OFFSET 3
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#define ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK (1 << 4)
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#define ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_OFFSET 4
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#define ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK (1 << 5)
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#define ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_OFFSET 5
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/* masks for the FIFO fill levels and sequence number */
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#define ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK 0xFFFF
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#define ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET 0
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#define ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK 0xFFFF0000
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#define ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET 16
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#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_MASK 0xFFFF
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#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_OFFSET 0
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#define ALTERA_MSGDMA_CSR_READ_SEQUENCE_NUMBER_MASK 0xFFFF
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#define ALTERA_MSGDMA_CSR_READ_SEQUENCE_NUMBER_OFFSET 0
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#define ALTERA_MSGDMA_CSR_WRITE_SEQUENCE_NUMBER_MASK 0xFFFF0000
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#define ALTERA_MSGDMA_CSR_WRITE_SEQUENCE_NUMBER_OFFSET 16
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/* read/write macros for each 32 bit register of the CSR port */
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#define IOWR_ALTERA_MSGDMA_CSR_STATUS(base, data) \
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IOWR_32DIRECT(base, ALTERA_MSGDMA_CSR_STATUS_REG, data)
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#define IOWR_ALTERA_MSGDMA_CSR_CONTROL(base, data) \
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IOWR_32DIRECT(base, ALTERA_MSGDMA_CSR_CONTROL_REG, data)
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#define IORD_ALTERA_MSGDMA_CSR_STATUS(base) \
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IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_STATUS_REG)
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#define IORD_ALTERA_MSGDMA_CSR_CONTROL(base) \
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IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_CONTROL_REG)
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#define IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(base) \
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IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL_REG)
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#define IORD_ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL(base) \
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IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_REG)
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#define IORD_ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER(base) \
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IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER_REG)
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#endif /*ALTERA_MSGDMA_ALTERA_MSGDMA_CSR_REGS_H_*/
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