453 lines
36 KiB
Tcl
453 lines
36 KiB
Tcl
#**************************************************************
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# This .sdc file is created by Terasic Tool.
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# Users are recommended to modify this file to match users logic.
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#**************************************************************
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -period 20.000ns [get_ports CLOCK_50]
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create_clock -period 20.000ns [get_ports CLOCK2_50]
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create_clock -period 20.000ns [get_ports CLOCK3_50]
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create_clock -period 8.000ns [get_ports ENET0_RX_CLK]
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create_clock -period 8.000ns [get_ports ENET0_TX_CLK]
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create_clock -period 8.000ns [get_ports ENET1_RX_CLK]
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create_clock -period 8.000ns [get_ports ENET1_TX_CLK]
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create_clock -period 400.000ns [get_ports ECE385:ECE385_sys|lantian_mdio:eth0_mdio|counter[1]]
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create_clock -period 400.000ns [get_ports ECE385:ECE385_sys|lantian_mdio:eth1_mdio|counter[1]]
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create_clock -period 20833.33ns [get_ports wm8731:wm8731_inst|flag1]
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create_clock -period 1000.000ns [get_ports wm8731:wm8731_inst|i2c_counter[9]]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {KEY[0]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {KEY[0]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {KEY[1]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {KEY[1]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {KEY[2]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {KEY[2]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {KEY[3]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {KEY[3]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[0]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[0]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[1]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[1]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[2]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[2]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[3]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[3]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[4]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[4]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[5]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[5]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[6]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[6]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[7]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[7]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[8]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[8]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[9]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[9]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[10]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[10]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[11]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[11]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[12]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[12]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[13]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[13]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[14]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[14]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[15]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[15]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[16]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[16]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SW[17]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SW[17]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[0]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[0]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[1]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[1]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[2]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[2]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[3]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[3]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[4]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[4]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[5]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[5]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[6]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[6]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[7]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[7]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[8]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[8]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[9]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[9]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[10]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[10]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[11]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[11]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[12]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[12]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[13]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[13]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[14]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[14]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[15]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[15]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[16]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[16]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[17]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[17]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[18]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[18]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[19]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[19]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[20]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[20]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[21]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[21]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[22]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[22]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[23]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[23]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[24]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[24]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[25]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[25]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[26]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[26]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[27]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[27]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[28]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[28]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[29]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[29]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[30]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[30]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {DRAM_DQ[31]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[31]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[0]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[0]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[1]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[1]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[2]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[2]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[3]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[3]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[4]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[4]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[5]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[5]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[6]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[6]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[7]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[7]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[8]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[8]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[9]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[9]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[10]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[10]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[11]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[11]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[12]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[12]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[13]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[13]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[14]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[14]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {OTG_DATA[15]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_DATA[15]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[0]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[0]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[1]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[1]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[2]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[2]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[3]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[3]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[4]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[4]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[5]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[5]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[6]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[6]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[7]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[7]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[8]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[8]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[9]}]
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set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[9]}]
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set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[10]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[10]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[11]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[11]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[12]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[12]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[13]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[13]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[14]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[14]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {SRAM_DQ[15]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[15]}]
|
|
|
|
set_input_delay -add_delay -max -clock [get_clocks {wm8731:wm8731_inst|flag1}] 3.000 [get_ports {AUD_ADCDAT}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_ADCDAT}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {wm8731:wm8731_inst|flag1}] 3.000 [get_ports {AUD_ADCLRCK}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_ADCLRCK}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {wm8731:wm8731_inst|flag1}] 3.000 [get_ports {AUD_BCLK}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_BCLK}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {wm8731:wm8731_inst|flag1}] 3.000 [get_ports {AUD_DACLRCK}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_DACLRCK}]
|
|
|
|
set_input_delay -add_delay -max -clock [get_clocks {wm8731:wm8731_inst|i2c_counter[9]}] 3.000 [get_ports {I2C_SDAT}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {wm8731:wm8731_inst|i2c_counter[9]}] 2.000 [get_ports {I2C_SDAT}]
|
|
|
|
set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {altera_reserved_tck}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {altera_reserved_tck}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {altera_reserved_tdi}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {altera_reserved_tdi}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}] 3.000 [get_ports {altera_reserved_tms}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {altera_reserved_tms}]
|
|
|
|
set_input_delay -add_delay -max -clock [get_clocks {ECE385:ECE385_sys|lantian_mdio:eth0_mdio|counter[1]}] 3.000 [get_ports {ENET0_MDIO}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ECE385:ECE385_sys|lantian_mdio:eth0_mdio|counter[1]}] 2.000 [get_ports {ENET0_MDIO}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET0_RX_CLK}] 3.000 [get_ports {ENET0_RX_DATA[0]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET0_RX_CLK}] 2.000 [get_ports {ENET0_RX_DATA[0]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET0_RX_CLK}] 3.000 [get_ports {ENET0_RX_DATA[1]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET0_RX_CLK}] 2.000 [get_ports {ENET0_RX_DATA[1]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET0_RX_CLK}] 3.000 [get_ports {ENET0_RX_DATA[2]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET0_RX_CLK}] 2.000 [get_ports {ENET0_RX_DATA[2]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET0_RX_CLK}] 3.000 [get_ports {ENET0_RX_DATA[3]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET0_RX_CLK}] 2.000 [get_ports {ENET0_RX_DATA[3]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET0_RX_CLK}] 3.000 [get_ports {ENET0_RX_DV}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET0_RX_CLK}] 2.000 [get_ports {ENET0_RX_DV}]
|
|
|
|
set_input_delay -add_delay -max -clock [get_clocks {ECE385:ECE385_sys|lantian_mdio:eth1_mdio|counter[1]}] 3.000 [get_ports {ENET1_MDIO}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ECE385:ECE385_sys|lantian_mdio:eth1_mdio|counter[1]}] 2.000 [get_ports {ENET1_MDIO}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET1_RX_CLK}] 3.000 [get_ports {ENET1_RX_DATA[0]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET1_RX_CLK}] 2.000 [get_ports {ENET1_RX_DATA[0]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET1_RX_CLK}] 3.000 [get_ports {ENET1_RX_DATA[1]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET1_RX_CLK}] 2.000 [get_ports {ENET1_RX_DATA[1]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET1_RX_CLK}] 3.000 [get_ports {ENET1_RX_DATA[2]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET1_RX_CLK}] 2.000 [get_ports {ENET1_RX_DATA[2]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET1_RX_CLK}] 3.000 [get_ports {ENET1_RX_DATA[3]}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET1_RX_CLK}] 2.000 [get_ports {ENET1_RX_DATA[3]}]
|
|
set_input_delay -add_delay -max -clock [get_clocks {ENET1_RX_CLK}] 3.000 [get_ports {ENET1_RX_DV}]
|
|
set_input_delay -add_delay -min -clock [get_clocks {ENET1_RX_CLK}] 2.000 [get_ports {ENET1_RX_DV}]
|
|
|
|
#**************************************************************
|
|
# Set Output Delay
|
|
#**************************************************************
|
|
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[0]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[1]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[2]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[3]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[4]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[5]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[6]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[7]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[8]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[9]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[10]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[11]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_ADDR[12]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_BA[0]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_BA[1]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_CAS_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_CKE}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_CS_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQM[0]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQM[1]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQM[2]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQM[3]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[0]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[1]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[2]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[3]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[4]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[5]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[6]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[7]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[8]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[9]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[10]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[11]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[12]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[13]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[14]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[15]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[16]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[17]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[18]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[19]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[20]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[21]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[22]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[23]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[24]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[25]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[26]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[27]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[28]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[29]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[30]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_DQ[31]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_RAS_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_WE_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {DRAM_CLK}]
|
|
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_ADDR[0]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_ADDR[1]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_CS_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_RD_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_WE_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {OTG_RST_N}]
|
|
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[0]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[1]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[2]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[3]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[4]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[5]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[6]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[7]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[8]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[9]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[10]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[11]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[12]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[13]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[14]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[15]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[16]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[17]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[18]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_ADDR[19]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_CE_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[0]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[1]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[2]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[3]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[4]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[5]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[6]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[7]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[8]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[9]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[10]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[11]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[12]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[13]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[14]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_DQ[15]}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_LB_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_OE_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_UB_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {SRAM_WE_N}]
|
|
|
|
set_output_delay -add_delay -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_ADCLRCK}]
|
|
set_output_delay -add_delay -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_BCLK}]
|
|
set_output_delay -add_delay -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_DACDAT}]
|
|
set_output_delay -add_delay -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_DACLRCK}]
|
|
set_output_delay -add_delay -clock [get_clocks {wm8731:wm8731_inst|flag1}] 2.000 [get_ports {AUD_XCK}]
|
|
|
|
set_output_delay -add_delay -clock [get_clocks {wm8731:wm8731_inst|i2c_counter[9]}] 2.000 [get_ports {I2C_SCLK}]
|
|
set_output_delay -add_delay -clock [get_clocks {wm8731:wm8731_inst|i2c_counter[9]}] 2.000 [get_ports {I2C_SDAT}]
|
|
|
|
set_output_delay -add_delay -clock [get_clocks {ECE385:ECE385_sys|lantian_mdio:eth0_mdio|counter[1]}] 2.000 [get_ports {ENET0_MDC}]
|
|
set_output_delay -add_delay -clock [get_clocks {ECE385:ECE385_sys|lantian_mdio:eth0_mdio|counter[1]}] 2.000 [get_ports {ENET0_MDIO}]
|
|
set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET0_RST_N}]
|
|
set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET0_TX_DATA[0]}]
|
|
set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET0_TX_DATA[1]}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET0_TX_DATA[2]}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET0_TX_DATA[3]}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET0_TX_EN}]
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set_output_delay -add_delay -clock [get_clocks {ECE385:ECE385_sys|lantian_mdio:eth1_mdio|counter[1]}] 2.000 [get_ports {ENET1_MDC}]
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set_output_delay -add_delay -clock [get_clocks {ECE385:ECE385_sys|lantian_mdio:eth1_mdio|counter[1]}] 2.000 [get_ports {ENET1_MDIO}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET1_RST_N}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET1_TX_DATA[0]}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET1_TX_DATA[1]}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET1_TX_DATA[2]}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET1_TX_DATA[3]}]
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set_output_delay -add_delay -clock [get_clocks {ECE385_sys|nios2_pll|sd1|pll7|clk[0]}] 2.000 [get_ports {ENET1_TX_EN}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 2.000 [get_ports {altera_reserved_tdo}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -to [get_ports {KEY*}]
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set_false_path -to [get_ports {SW*}]
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set_false_path -to [get_ports {LED*}]
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set_false_path -to [get_ports {HEX*}]
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set_false_path -to [get_ports {VGA_*}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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#**************************************************************
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# Set Load
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#**************************************************************
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